static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    int res = 0;
    
    cyg_uint16 status;
    cyg_uint16 control;

    cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
    
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;

    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, control);

    if((status & SCSR_RDRF) && (control & SCCR1_RIE))
    {   // Only if the interrupt was caused by the channel
        cyg_uint8 c;
        c = cyg_hal_plf_serial_getc(__ch_data);
	
        if(cyg_hal_is_break(&c, 1))
	    *__ctrlc = 1;
	
	HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
	res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

//static 
cyg_bool
cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint16 fdr, sr;
    cyg_bool res = false;

    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    if (sr & CYGARC_REG_SCIF_SCSSR_ER) {
        cyg_uint8 ssr2;
        HAL_WRITE_UINT16(base+_REG_SCFER, 0);
        HAL_READ_UINT8(base+_REG_SC2SSR, ssr2);
        ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER;
        HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER));
    }


    HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) {

        HAL_READ_UINT8(base+_REG_SCFRDR, *ch);

        // Clear DR/RDF flags
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR));

        res = true;
    }

    return res;
}

externC cyg_uint16 
_mb93091_pci_cfg_read_uint16(int bus, int devfn, int offset)
{
    cyg_uint32 cfg_addr, addr, status;
    cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;

    if (!_mb93091_has_vdk)
	    return cfg_val;
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
    if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
        // PCI bridge
        addr = _MB93091_PCI_CONFIG + ((offset << 1) ^ 0x02);
    } else {
        cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
        HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
        addr = _MB93091_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
    }
    HAL_READ_UINT16(addr, cfg_val);
    HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
    if (status & _MB93091_PCI_STAT_ERROR_MASK) {
        // Cycle failed - clean up and get out
        cfg_val = (cyg_uint16)0xFFFF;
        HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
    }
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
    HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
    return cfg_val;
}

// Default arbitration ISR for serial interrupts. Although such arbitration
// belongs in the serial device driver, we require this default implementation
// for CTRL-C interrupts to be delivered correctly to any running ROM monitor.
// A device driver that uses more than just receive interrupts may of course
// provide its own arbiter.
externC cyg_uint32
hal_arbitration_isr_sci(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
    cyg_uint32 isr_ret;
	cyg_uint16 scc_sr;
	cyg_uint16 scc_cr;

	// Try SCI0
	HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scc_sr);
	HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, scc_cr);
	if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
		   return isr_ret;
	}

	HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scc_sr);
	HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, scc_cr);
	if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
			return isr_ret;
	}

	return 0;
}

void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint16 fdr, sr;
    CYGARC_HAL_SAVE_GP();

    do {
        HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);

    HAL_WRITE_UINT8(base+_REG_SCFTDR, c);

    // Clear FIFO-empty/transmit end flags (read back SR first)
    HAL_READ_UINT16(base+_REG_SCFSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCFSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK   
                     & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));

    // Hang around until the character has been safely sent.
    do {
        HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    } while ((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) != 0);

    CYGARC_HAL_RESTORE_GP();
}

void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8* base = chan->base;
    cyg_uint16 fdr, sr;
    cyg_uint8 scscr = 0;
    CYGARC_HAL_SAVE_GP();

    HAL_READ_UINT8(base+_REG_SCSCR, scscr);
    if (chan->irda_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE);
    }
#endif

    do {
        HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);

    HAL_WRITE_UINT8(base+_REG_SCFTDR, c);

    // Clear FIFO-empty/transmit end flags (read back SR first)
    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK   
                     & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));

    // Hang around until all characters have been safely sent.
    do {
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
    } while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0);


    if (chan->irda_mode) {
#ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // In IrDA mode there will be generated spurious RX events when
        // the TX unit is switched on. Eat that character.
        cyg_uint8 _junk;
        HAL_READ_UINT8(base+_REG_SCFRDR, _junk);

        // Clear buffer full flag (read back first)
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR, 
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
#endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // Disable transmitter again
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        // Disable transmitter, enable receiver
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX

    CYGARC_HAL_RESTORE_GP();
}

static int
cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc, 
                     CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    cyg_uint8 c;
    cyg_uint16 fdr, sr;
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    int res = 0;
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;
    HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    if ((fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK) != 0) {
        HAL_READ_UINT8(base+_REG_SCFRDR, c);

        // Clear buffer full flag (read back first).
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR, 
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF);

        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint16 ser_port_reg;
    int ret = 0;
    va_list ap;

    CYGARC_HAL_SAVE_GP();
    va_start(ap, __func);

    switch (__func) {
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
        chan->baud_rate = va_arg(ap, cyg_int32);
        // Should we verify this value here?
        cyg_hal_plf_serial_init_channel(chan);
        ret = 0;
        break;
    case __COMMCTL_IRQ_ENABLE:
        irq_state = 1;
        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
        HAL_INTERRUPT_UNMASK(chan->isr_vector);

        HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
        ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
        HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);

        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);

        HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
        ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
        HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);
    default:
        break;
    }

    va_end(ap);
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

externC void
_mb93091_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
    cyg_uint32 cfg_addr, addr, status;

    if (!_mb93091_has_vdk)
	    return;
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
    if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
        // PCI bridge
        addr = _MB93091_PCI_CONFIG + (offset << 1);
    } else {
        cfg_addr = _cfg_addr(bus, devfn, offset);
        HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
        addr = _MB93091_PCI_CONFIG_DATA;
    }
    HAL_WRITE_UINT32(addr, cfg_val);
    HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
    if (status & _MB93091_PCI_STAT_ERROR_MASK) {
        // Cycle failed - clean up and get out
        HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
    }
    HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
}

// Timebase interrupt can be caused by match on either reference A
// or B.  
// Note: If only one interrupt source is assigned per vector, and only
// reference interrupt A or B is used, this ISR is not
// necessary. Attach the timerbase reference A or B ISR directly to
// the LVLx vector instead.
externC cyg_uint32
hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
    cyg_uint32 isr_ret;
    cyg_uint16 tbscr;

    HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
    if (tbscr & CYGARC_REG_IMM_TBSCR_REFA) {
        isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
            return isr_ret;
    }

    if (tbscr & CYGARC_REG_IMM_TBSCR_REFB) {
        isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
            return isr_ret;
    }

    return 0;
}

void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
    cyg_uint8* base = chan->base;
    cyg_uint16 sr;

    // Disable everything.
    HAL_WRITE_UINT16(base+_REG_SCSCR, 0);

    // Reset FIFO.
    HAL_WRITE_UINT16(base+_REG_SCFCR, 
                    CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);

    // 8-1-no parity.
    HAL_WRITE_UINT16(base+_REG_SCSMR, 0);

    chan->baud_rate = CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE;
    cyg_hal_plf_scif_set_baud(base, CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE);

    // Clear status register (read back first).
    HAL_READ_UINT16(base+_REG_SCFSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCFSR, 0);

    // Bring FIFO out of reset and set to trigger on every char in
    // FIFO (or C-c input would not be processed).
    HAL_WRITE_UINT16(base+_REG_SCFCR, 
                    CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);

    // Leave Tx/Rx interrupts disabled, but enable Tx/Rx
    HAL_WRITE_UINT16(base+_REG_SCSCR, 
                    CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}

int
hal_enable_profile_timer(int resolution)
{
    // Run periodic timer interrupt for profile 
    cyg_uint16 piscr;
    int period = resolution / 100;

    // Attach pit arbiter.
    HAL_INTERRUPT_ATTACH (PIT_IRQ,
                          &hal_arbitration_isr_pit, ID_PIT, 0);
    HAL_INTERRUPT_UNMASK (PIT_IRQ);

    // Attach pit isr.
    HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
                          ID_PIT, 0);
    HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, PIT_IRQ_LEVEL);
    HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);


    // Set period.
    HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, 
                      (2*period) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);

    // Enable.
    HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
    piscr |= CYGARC_REG_IMM_PISCR_PTE;
    HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);

    return resolution;
}

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{

    channel_data_t* chan = (channel_data_t*)__ch_data;
    CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base;
    cyg_uint16 esci_sr;
    int res = 0;
    cyg_uint8 ch_in;
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;

    HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
    if (esci_sr & FREESCALE_ESCI_SR_RDRF) {
        HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in);
        if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
        HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF);
    }

    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);

    CYGARC_HAL_RESTORE_GP();
    return res;
}

// Real time clock interrupts can be caused by the alarm or
// once-per-second.
// Note: If only one interrupt source is assigned per vector, and only
// the alarm or once-per-second interrupt is used, this ISR is not
// necessary. Attach the alarm or once-per-second ISR directly to the
// LVLx vector instead.
externC cyg_uint32
hal_arbitration_isr_rtc (CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
    cyg_uint32 isr_ret;
    cyg_uint16 rtcsc;

    HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
    if (rtcsc & CYGARC_REG_IMM_RTCSC_SEC) {
        isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
            return isr_ret;
    }

    if (rtcsc & CYGARC_REG_IMM_RTCSC_ALR) {
        isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
        if (isr_ret & CYG_ISR_HANDLED)
#endif
            return isr_ret;
    }

    return 0;
}

externC cyg_uint32 
_csb281_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
    cyg_uint32 addr;
    cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;

#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
    addr = _cfg_sel(bus, devfn, offset);
    HAL_READ_UINT32LE(addr, cfg_val);
#if 0
    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
        // Cycle failed - clean up and get out
        cfg_val = (cyg_uint32)0xFFFFFFFF;
        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
    }
#endif
#ifdef CYGPKG_IO_PCI_DEBUG
    diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
    return cfg_val;
}

static void 
mn10300_serial_stop_xmit(serial_channel *chan)
{
#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE    
    mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv;
    cyg_uint16 cr;
    cyg_uint16 sr;

    // Wait until the transmitter has actually stopped before turning it off.
    
    do
    {
        sr = mn10300_read_sr( mn10300_chan );
        
    } while( sr & SR_TXF );
    
    HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr );

    DISABLE_TRANSMIT_INTERRUPT(mn10300_chan);
    
    HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr );

    cyg_drv_interrupt_mask(mn10300_chan->tx_int);
    
#endif    
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint16 status;
    cyg_uint16 result;
    cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;

    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
    if((status & SCSR_RDRF) == 0)
        return false;

    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, result);
    *ch = (cyg_uint8)(result & 0x00ff);

    return true;
}

void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
    cyg_uint8* base = chan->base;
    cyg_uint8 tmp;
    cyg_uint16 sr;
    int baud_rate = CYGNUM_HAL_SH_SH2_SCIF_BAUD_RATE;

    // Disable everything.
    HAL_WRITE_UINT8(base+_REG_SCSCR, 0);

    // Reset FIFO.
    HAL_WRITE_UINT8(base+_REG_SCFCR, 
                    CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
    HAL_WRITE_UINT16(base+_REG_SCFER, 0);

    // 8-1-no parity. This is also fine for IrDA mode
    HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
    if (chan->irda_mode)
        HAL_WRITE_UINT8(base+_REG_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD);
    else {
        HAL_WRITE_UINT8(base+_REG_SCIMR, 0);
    }

    // Set speed to CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE
    HAL_READ_UINT8(base+_REG_SCSMR, tmp);
    tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
    tmp |= CYGARC_SCBRR_CKSx(baud_rate);
    HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
    HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(baud_rate));

    // Let things settle: Here we should should wait the equivalent of
    // one bit interval,
    // i.e. 1/CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE second, but
    // until we have something like the Linux delay loop, it's hard to
    // do reliably. So just move on and hope for the best (this is
    // unlikely to cause problems since the CPU has just come out of
    // reset anyway).

    // Clear status register (read back first).
    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCSSR, 0);

    HAL_WRITE_UINT8(base+_REG_SC2SSR, CYGARC_REG_SCIF_SC2SSR_BITRATE_16|CYGARC_REG_SCIF_SC2SSR_EI);

    // Bring FIFO out of reset and set to trigger on every char in
    // FIFO (or C-c input would not be processed).
    HAL_WRITE_UINT8(base+_REG_SCFCR, 
                    CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);

    // Leave Tx/Rx interrupts disabled, but enable Rx/Tx (only Rx for IrDA)
    if (chan->irda_mode)
        HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    else if (chan->async_rxtx_mode)
        HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#endif 
    else
        HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}

// Initialize SDRAM controller
void plf_init_sdramc(void)
{
    cyg_uint16 sdcr;

    
    HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
    
    // Do not initialize SDRAM if it is already active
    if (!(sdcr & MCF5272_SDRAMC_SDCCR_ACT))
    {
#if (CYGHWR_HAL_SYSTEM_CLOCK_MHZ == 66)
        HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
            | MCF5272_SDRAMC_SDCTR_RTP_66MHz
            | MCF5272_SDRAMC_SDCTR_RC(0)
            | MCF5272_SDRAMC_SDCTR_RP(1)
            | MCF5272_SDRAMC_SDCTR_RCD(1)
            | MCF5272_SDRAMC_SDCTR_CLT_2));
#else
        // Clock frequency must be 48 Mhz
        HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
            | MCF5272_SDRAMC_SDCTR_RTP_48MHz
            | MCF5272_SDRAMC_SDCTR_RC(0)
            | MCF5272_SDRAMC_SDCTR_RP(1)
            | MCF5272_SDRAMC_SDCTR_RCD(0)
            | MCF5272_SDRAMC_SDCTR_CLT_2));
#endif

        HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdcr, (0
            | MCF5272_SDRAMC_SDCCR_MCAS_A9
#if (CYGHWR_INSTALLED_SDRAM_SIZE == 4)
            | MCF5272_SDRAMC_SDCCR_BALOC_A21
#else
            | MCF5272_SDRAMC_SDCCR_BALOC_A22
#endif
            | MCF5272_SDRAMC_SDCCR_REG
            | MCF5272_SDRAMC_SDCCR_INIT));

        // Start SDRAM controller with a memory write
        *((volatile char *) CYGMEM_REGION_sdram) = 0;

        // Wait until controller is ready
        do
        {
            HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
        } while(!(sdcr & MCF5272_SDRAMC_SDCCR_ACT));
    }
}

// Read one datum from 16-bit bus 
static int read_data_16(struct dm9000 *p, cyg_uint8 *dest)
{
    cyg_uint16 val;

    HAL_READ_UINT16(p->io_data, val);
    memcpy(dest, &val, 2);
    return 2;
}