本文整理汇总了C++中LibAmdPciRead函数 的典型用法代码示例。如果您正苦于以下问题：C++ LibAmdPciRead函数的具体用法？C++ LibAmdPciRead怎么用？C++ LibAmdPciRead使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了LibAmdPciRead函数 的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: F10PmThermalInit
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 10h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F10PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 LocalPciRegister;
UINT32 Socket;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0;
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}开发者ID:Godkey， 项目名称:coreboot， 代码行数:41， 代码来源:cpuF10SoftwareThermal.c
示例2: F16MlGetNbIddMax
/**
* Get NB pstate current.
*
* @CpuServiceMethod{::F_CPU_GET_NB_IDD_MAX}.
*
* This function returns the NbIddMax.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] NbPstate The NB P-state to check.
* @param[out] NbIddMax NB P-state current in mA.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE NB P-state is enabled, and NbIddMax is valid.
* @retval FALSE NB P-state is disabled
*/
BOOLEAN
F16MlGetNbIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 NbPstate,
OUT UINT32 *NbIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN IsNbPsEnabled;
PCI_ADDR PciAddress;
NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg;
NB_PSTATE_REGISTER NbPstateReg;
IDS_HDT_CONSOLE (CPU_TRACE, " F16MlGetNbIddMax - NB P%d\n", NbPstate);
IsNbPsEnabled = FALSE;
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateCtrlReg, StdHeader);
ASSERT (NbPstate < NM_NB_PS_REG);
if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
// Ensure that requested NbPstate is enabled
if (NbPstateReg.NbPstateEn == 1) {
F16MlCmnCalculateCurrentInmA (NbPstateReg.NbIddValue, NbPstateReg.NbIddDiv, NbIddMax, StdHeader);
IsNbPsEnabled = TRUE;
IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbIddMax %d\n", NbPstate, *NbIddMax);
}
}
return IsNbPsEnabled;
}开发者ID:fishbaoz， 项目名称:MullinsPI， 代码行数:49， 代码来源:F16MlUtilities.c
示例3: F15KvInitializeHtc
/**
* Entry point for enabling Hardware Thermal Control
*
* This function must be run after all P-State routines have been executed
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15KvInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
} else {
// Disable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0;
}
IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
return AGESA_SUCCESS;
}开发者ID:fishbaoz， 项目名称:KaveriPI， 代码行数:47， 代码来源:cpuF15KvHtc.c
示例4: Erratum687Workaround
/**
* Workaround for Erratum #687 for TN processors.
*
* AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
* program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts.
*
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
Erratum687Workaround (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PRODUCT_INFO_REGISTER ProductInfo;
NB_CFG_4_REGISTER NbCfg4;
GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
UINT32 DctSelCnt;
DCT_CFG_SEL_REGISTER DctCfgSel;
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
}
}开发者ID:B-Rich， 项目名称:coreboot， 代码行数:44， 代码来源:F15TnPciTables.c
示例5: F15SetBrandIdRegistersAtEarly
/**
* Set the Processor Name String register based on F5x194/198
*
* This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
UINT32 ExceptionId;
UINT32 MsrIndex;
UINT64 MsrData;
UINT64 *MsrNameStringPtrPtr;
PCI_ADDR PciAddress;
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
if (IsException (&ExceptionId, StdHeader)) {
ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));
MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
} else {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
// check if D18F5x198_x0 is 00000000h.
PciData = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
if (PciData != 0) {
for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = MsrIndex * 2;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = (MsrIndex * 2) + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
}
return;
} else {
// It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
}
}
// Put values into name MSRs, Always write the full 48 bytes
for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
MsrNameStringPtrPtr++;
}
}
}开发者ID:B-Rich， 项目名称:coreboot， 代码行数:69， 代码来源:cpuF15BrandId.c
示例6: F14OptimizeForLowPowerInit
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
* according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
BOOLEAN OptimizeForLowPower;
BOOLEAN IsRevC;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
(CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
OptimizeForLowPower = TRUE;
} else {
OptimizeForLowPower = FALSE;
}
// Get F4x15C [4:2] NumBoostStates
// Get IsRevC
NumBoostStates = 0;
IsRevC = FALSE;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
IsRevC = TRUE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
// F6x94[2:0] CpuPstateThr
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (OptimizeForLowPower) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
} else {
if (NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
}
// F6x94[3] CpuPstateThrEn = 1
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// F4x134[31:27] IntRateCC6DecrRate
PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}开发者ID:AdriDlu， 项目名称:coreboot， 代码行数:70， 代码来源:cpuF14LowPowerInit.c
示例7: F16MlGetNbPstateInfo
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
* @param[in] NbPstate The NB P-state number to check.
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
* @param[out] FreqDivisor The desired node's frequency divisor.
* @param[out] VoltageInuV The desired node's voltage in microvolts.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE NbPstate is valid
* @retval FALSE NbPstate is disabled or invalid
*/
BOOLEAN
F16MlGetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbVid;
BOOLEAN PstateIsValid;
NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg;
NB_PSTATE_REGISTER NbPstateReg;
IDS_HDT_CONSOLE (CPU_TRACE, " F16MlGetNbPstateInfo - NB P%d\n", NbPstate);
ASSERT ((PciAddress->Address.Segment == 0) && (PciAddress->Address.Bus == 0) && (PciAddress->Address.Device == 0x18));
PstateIsValid = FALSE;
// If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled
if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
PciAddress->AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateCtrlReg, StdHeader);
ASSERT ((NbPstate < NM_NB_PS_REG) && (NbPstateCtrlReg.NbPstateMaxVal < NM_NB_PS_REG));
if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
PciAddress->Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateReg, StdHeader);
IDS_HDT_CONSOLE (CPU_TRACE, " En:%d Fid:%x Did:%x Vid:%x\n", NbPstateReg.NbPstateEn, NbPstateReg.NbFid, NbPstateReg.NbDid, GetF16MlNbVid (&NbPstateReg));
// Check if at least NB P0 is enabled.
ASSERT ((NbPstate == 0) ? (NbPstateReg.NbPstateEn == 1) : TRUE);
// Ensure that requested NbPstate is enabled
if (NbPstateReg.NbPstateEn == 1) {
// Check for P-state Bandwidth Requirements on
// "All NB P-states must be defined such that D18F5x1[6C:60][NbFid] <= 2Eh"
ASSERT (NbPstateReg.NbFid <= 0x2E);
F16MlGetNbFreqNumeratorInMHz (NbPstateReg.NbFid, FreqNumeratorInMHz, StdHeader);
F16MlGetNbFreqDivisor (NbPstateReg.NbDid, FreqDivisor, StdHeader);
// Check for P-state Bandwidth Requirements on
// "400MHz <= NBCOF <= 1600MHz"
ASSERT ((*FreqNumeratorInMHz / *FreqDivisor) >= 400);
ASSERT ((*FreqNumeratorInMHz / *FreqDivisor) <= 1600);
NbVid = GetF16MlNbVid (&NbPstateReg);
F16MlCovertVidInuV (NbVid, VoltageInuV, StdHeader);
PstateIsValid = TRUE;
IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbVid=%d VoltageInuV=%d\n", NbPstate, NbVid, *VoltageInuV);
}
}
}
return PstateIsValid;
}开发者ID:fishbaoz， 项目名称:MullinsPI， 代码行数:74， 代码来源:F16MlUtilities.c
示例8: F15OrPmNbAfterResetOnCore
/**
* Support routine for F15OrPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
*
* This function implements steps 1 - 13 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F15OrPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NB_PSTATE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) {
// 4. If MSRC001_0070[NbPstate] = 1, go to step 9
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 7. Set D18F5x170[SwNbPstateLoDis] = 1.
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 13.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and
// D18F5x170[NbPstateThreshold] = Temp3.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}开发者ID:B-Rich， 项目名称:coreboot， 代码行数:65， 代码来源:cpuF15OrNbAfterReset.c
示例9: F16KbInitializeHtc
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Kabini core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 HtcTempLimit;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
UINT32 D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
if (HtcTempLimit < HtcReg.HtcTmpLmt) {
HtcReg.HtcTmpLmt = HtcTempLimit;
}
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}开发者ID:B-Rich， 项目名称:coreboot， 代码行数:69， 代码来源:F16KbHtc.c
示例10: F14InitializeIoCstate
/**
* Enable IO Cstate on a family 14h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Program D18F4x1A8[PService] to the index of lowest-performance
// P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL0_REGISTER *) &PciRegister)->PService = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Program D18F4x1AC[CstPminEn] to 1.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CstPminEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
return AGESA_SUCCESS;
}开发者ID:michaelforney， 项目名称:coreboot， 代码行数:66， 代码来源:F14IoCstate.c
示例11: F10RevDSyncInternalNode1SbiAddr
/**
* A Family Specific Workaround method, to sync internal node 1 SbiAddr setting.
*
* @param[in] Data The table data value (unused in this routine)
* @param[in] StdHeader Config handle for library and services
*
*---------------------------------------------------------------------------------------
**/
VOID
STATIC
F10RevDSyncInternalNode1SbiAddr (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 DataOr;
UINT32 DataAnd;
UINT32 ModuleType;
PCI_ADDR PciAddress;
AGESA_STATUS AgesaStatus;
UINT32 SyncToModule;
AP_MAIL_INFO ApMailboxInfo;
UINT32 LocalPciRegister;
ApMailboxInfo.Info = 0;
GetApMailbox (&ApMailboxInfo.Info, StdHeader);
ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);
ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);
Socket = ApMailboxInfo.Fields.Socket;
Module = ApMailboxInfo.Fields.Module;
ModuleType = ApMailboxInfo.Fields.ModuleType;
// sync is just needed on multinode cpu
if (ModuleType != 0) {
// check if it is internal node 0 of every socket
if (Module == 0) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1E4;
// read internal node 0 F3x1E4[6:4]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
DataOr = LocalPciRegister & ((UINT32) (7 << 4));
DataAnd = ~(UINT32) (7 << 4);
for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) {
if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1E4;
// sync the other internal node F3x1E4[6:4]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LocalPciRegister &= DataAnd;
LocalPciRegister |= DataOr;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
}
}
}开发者ID:AdriDlu， 项目名称:coreboot， 代码行数:61， 代码来源:cpuF10WorkaroundsTable.c
示例12: F16MlInitializeHtc
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Mullins core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16MlInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
D0F0xBC_xC0107097_STRUCT D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_xC0107097_TYPE, D0F0xBC_xC0107097_ADDRESS, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = D0F0xBC_xC0107097.Field.HtcTmpLmt;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
}
return AGESA_SUCCESS;
}开发者ID:fishbaoz， 项目名称:edk2ml， 代码行数:65， 代码来源:F16MlHtc.c
示例13: F15CzInitializeCpb
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15CzInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
PCI_ADDR StcPciAddr;
F15_PSTATE_MSR PstateMsrData;
SW_PS_LIMIT_REGISTER Stc;
UINT32 Pbx;
UINT32 PsMax;
if ((EntryPoint & CPU_FEAT_MID_INIT) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.BoostSrc == 0) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
StcPciAddr.AddressValue = SW_PS_LIMIT_PCI_ADDR;
LibAmdPciRead (AccessWidth32, StcPciAddr, &Stc, StdHeader);
Stc.SwPstateLimitEn = 1;
Stc.SwPstateLimit = CpbControl.NumBoostStates;
LibAmdPciWrite (AccessWidth32, StcPciAddr, &Stc, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, StcPciAddr, AccessWidth32, &Stc);
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &CpbControl);
break;
}
}
}
} else if ((EntryPoint & CPU_FEAT_MID_LATE_INIT) != 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0xDC);
LibAmdPciRead (AccessWidth32, PciAddress, &PsMax, StdHeader);
PsMax = ((PsMax & 0x700) << 20);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0x68);
LibAmdPciWrite (AccessWidth32, PciAddress, &PsMax, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &PsMax);
}
return AGESA_SUCCESS;
}开发者ID:fishbaoz， 项目名称:CarrizoPI， 代码行数:64， 代码来源:cpuF15CzCpb.c
示例14: SetF15KvCacheFlushOnHaltRegister
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF15KvCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
F15_KV_CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set D18F3xDC[CacheFlushOnHaltCtl] != 0
// Set D18F3xDC[CacheFlushOnHaltTmr]
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;
ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x32;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
// Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
CstatePolicyCtrl1.CacheFlushTmr = 0x32;
CstatePolicyCtrl1.CacheFlushSucMonThreshold = 5;
CstatePolicyCtrl1.CacheFlushSucMonMispredictAct = 1;
CstatePolicyCtrl1.CacheFlushSucMonTmrSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
// Set cache flush bits in D18F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
CstateCtrl1.CacheFlushEnCstAct0 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;
CstateCtrl1.ClkDivisorCstAct0 = 0;
// Set C-state Action Field 1
CstateCtrl1.CacheFlushEnCstAct1 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;
CstateCtrl1.ClkDivisorCstAct1 = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}开发者ID:fishbaoz， 项目名称:KaveriPI， 代码行数:57， 代码来源:cpuF15KvCacheFlushOnHalt.c
示例15: F10IsNonOptimalConfig
/**
* Check to see if the input CPU is running in the optimal configuration.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HT Assist is running sub-optimally.
* @retval FALSE HT Assist is running optimally.
*
*/
STATIC BOOLEAN
F10IsNonOptimalConfig (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN IsNonOptimal;
BOOLEAN IsMemoryPresent;
UINT32 Module;
UINT32 PciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
IsNonOptimal = FALSE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
IsMemoryPresent = FALSE;
PciAddress.Address.Function = FUNC_2;
PciAddress.Address.Register = DRAM_CFG_HI_REG0;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
IsMemoryPresent = TRUE;
if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
IsNonOptimal = TRUE;
break;
}
}
PciAddress.Address.Register = DRAM_CFG_HI_REG1;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
IsMemoryPresent = TRUE;
if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
IsNonOptimal = TRUE;
break;
}
}
if (!IsMemoryPresent) {
IsNonOptimal = TRUE;
break;
}
}
}
return IsNonOptimal;
}开发者ID:AdriDlu， 项目名称:coreboot， 代码行数:59， 代码来源:F10RevDHtAssist.c
示例16: F14IsC6Supported
/**
* Is C6 supported on this CPU
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] Socket This core's zero-based socket number.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE C6 state is supported.
* @retval FALSE C6 state is not supported.
*
*/
BOOLEAN
STATIC
F14IsC6Supported (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciRegister;
BOOLEAN IsEnabled;
PCI_ADDR PciAddress;
IsEnabled = TRUE;
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if ((((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CoreC6Cap == 0) &&
(((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Cap == 0)) {
IsEnabled = FALSE;
}
F14EarlySampleC6Support.F14IsC6SupportedHook (&IsEnabled, StdHeader);
return IsEnabled;
}开发者ID:michaelforney， 项目名称:coreboot， 代码行数:36， 代码来源:F14C6State.c
示例17: F10IsHtAssistSupported
/**
* Check to see if the input CPU supports HT Assist.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HT Assist is supported.
* @retval FALSE HT Assist cannot be enabled.
*
*/
BOOLEAN
STATIC
F10IsHtAssistSupported (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 PciRegister;
BOOLEAN IsSupported;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
IsSupported = FALSE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &PciRegister)->L3Capable == 1) {
IsSupported = TRUE;
}
break;
}
}
return IsSupported;
}开发者ID:AdriDlu， 项目名称:coreboot， 代码行数:39， 代码来源:F10RevDHtAssist.c
示例18: Update800MHzHtcPstateTo900MHz
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