本文整理汇总了C++中LibAmdPciWrite函数 的典型用法代码示例。如果您正苦于以下问题:C++ LibAmdPciWrite函数的具体用法?C++ LibAmdPciWrite怎么用?C++ LibAmdPciWrite使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了LibAmdPciWrite函数 的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: select_socket
static void select_socket(UINT8 socket_id)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (SMBUS0_BASE_ADDRESS & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
switch (socket_id) {
case 0:
/* Switch onto the First CPU Socket SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x80, 0x03);
break;
case 1:
/* Switch onto the Second CPU Socket SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x40, 0x03);
break;
default:
/* Switch off two CPU Sockets SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
break;
}
}
开发者ID:MikeeHawk, 项目名称:coreboot, 代码行数:33, 代码来源:BiosCallOuts.c
示例2: Erratum687Workaround
/**
* Workaround for Erratum #687 for TN processors.
*
* AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
* program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts.
*
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
Erratum687Workaround (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PRODUCT_INFO_REGISTER ProductInfo;
NB_CFG_4_REGISTER NbCfg4;
GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
UINT32 DctSelCnt;
DCT_CFG_SEL_REGISTER DctCfgSel;
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
}
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:44, 代码来源:F15TnPciTables.c
示例3: SetupFch
STATIC
VOID
SetupFch (
IN UINT16
IN IoBase
)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
/* set SMBus clock to 400 KHz */
__outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
}
开发者ID:hustcalm, 项目名称:coreboot-hacking, 代码行数:26, 代码来源:dimmSpd.c
示例4: F15SetBrandIdRegistersAtEarly
/**
* Set the Processor Name String register based on F5x194/198
*
* This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
UINT32 ExceptionId;
UINT32 MsrIndex;
UINT64 MsrData;
UINT64 *MsrNameStringPtrPtr;
PCI_ADDR PciAddress;
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
if (IsException (&ExceptionId, StdHeader)) {
ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));
MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
} else {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
// check if D18F5x198_x0 is 00000000h.
PciData = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
if (PciData != 0) {
for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = MsrIndex * 2;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = (MsrIndex * 2) + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
}
return;
} else {
// It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
}
}
// Put values into name MSRs, Always write the full 48 bytes
for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
MsrNameStringPtrPtr++;
}
}
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:69, 代码来源:cpuF15BrandId.c
示例5: F14OptimizeForLowPowerInit
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
* according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
BOOLEAN OptimizeForLowPower;
BOOLEAN IsRevC;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
(CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
OptimizeForLowPower = TRUE;
} else {
OptimizeForLowPower = FALSE;
}
// Get F4x15C [4:2] NumBoostStates
// Get IsRevC
NumBoostStates = 0;
IsRevC = FALSE;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
IsRevC = TRUE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
// F6x94[2:0] CpuPstateThr
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (OptimizeForLowPower) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
} else {
if (NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
}
// F6x94[3] CpuPstateThrEn = 1
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// F4x134[31:27] IntRateCC6DecrRate
PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
开发者ID:AdriDlu, 项目名称:coreboot, 代码行数:70, 代码来源:cpuF14LowPowerInit.c
示例6: F16KbInitializeHtc
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Kabini core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 HtcTempLimit;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
UINT32 D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
if (HtcTempLimit < HtcReg.HtcTmpLmt) {
HtcReg.HtcTmpLmt = HtcTempLimit;
}
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:69, 代码来源:F16KbHtc.c
示例7: F14InitializeIoCstate
/**
* Enable IO Cstate on a family 14h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Program D18F4x1A8[PService] to the index of lowest-performance
// P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL0_REGISTER *) &PciRegister)->PService = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Program D18F4x1AC[CstPminEn] to 1.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CstPminEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
开发者ID:michaelforney, 项目名称:coreboot, 代码行数:66, 代码来源:F14IoCstate.c
示例8: F16MlInitializeHtc
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Mullins core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16MlInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
D0F0xBC_xC0107097_STRUCT D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_xC0107097_TYPE, D0F0xBC_xC0107097_ADDRESS, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = D0F0xBC_xC0107097.Field.HtcTmpLmt;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
}
return AGESA_SUCCESS;
}
开发者ID:fishbaoz, 项目名称:edk2ml, 代码行数:65, 代码来源:F16MlHtc.c
示例9: F15CzInitializeCpb
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15CzInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
PCI_ADDR StcPciAddr;
F15_PSTATE_MSR PstateMsrData;
SW_PS_LIMIT_REGISTER Stc;
UINT32 Pbx;
UINT32 PsMax;
if ((EntryPoint & CPU_FEAT_MID_INIT) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.BoostSrc == 0) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
StcPciAddr.AddressValue = SW_PS_LIMIT_PCI_ADDR;
LibAmdPciRead (AccessWidth32, StcPciAddr, &Stc, StdHeader);
Stc.SwPstateLimitEn = 1;
Stc.SwPstateLimit = CpbControl.NumBoostStates;
LibAmdPciWrite (AccessWidth32, StcPciAddr, &Stc, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, StcPciAddr, AccessWidth32, &Stc);
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &CpbControl);
break;
}
}
}
} else if ((EntryPoint & CPU_FEAT_MID_LATE_INIT) != 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0xDC);
LibAmdPciRead (AccessWidth32, PciAddress, &PsMax, StdHeader);
PsMax = ((PsMax & 0x700) << 20);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0x68);
LibAmdPciWrite (AccessWidth32, PciAddress, &PsMax, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &PsMax);
}
return AGESA_SUCCESS;
}
开发者ID:fishbaoz, 项目名称:CarrizoPI, 代码行数:64, 代码来源:cpuF15CzCpb.c
示例10: SetF15KvCacheFlushOnHaltRegister
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF15KvCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
F15_KV_CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set D18F3xDC[CacheFlushOnHaltCtl] != 0
// Set D18F3xDC[CacheFlushOnHaltTmr]
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;
ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x32;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
// Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
CstatePolicyCtrl1.CacheFlushTmr = 0x32;
CstatePolicyCtrl1.CacheFlushSucMonThreshold = 5;
CstatePolicyCtrl1.CacheFlushSucMonMispredictAct = 1;
CstatePolicyCtrl1.CacheFlushSucMonTmrSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
// Set cache flush bits in D18F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
CstateCtrl1.CacheFlushEnCstAct0 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;
CstateCtrl1.ClkDivisorCstAct0 = 0;
// Set C-state Action Field 1
CstateCtrl1.CacheFlushEnCstAct1 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;
CstateCtrl1.ClkDivisorCstAct1 = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
开发者ID:fishbaoz, 项目名称:KaveriPI, 代码行数:57, 代码来源:cpuF15KvCacheFlushOnHalt.c
示例11: SetF16KbCacheFlushOnHaltRegister
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[11] NbClkGate0 = 0x1
// bits[12] SelfRefr0 = 0x1
CstateCtrl1.NbClkGate0 = 1;
CstateCtrl1.SelfRefr0 = 1;
// Set C-state Action Field 1
// bits[27] NbClkGate1 = 0x1
// bits[28] SelfRefr1 = 0x1
CstateCtrl1.NbClkGate1 = 1;
CstateCtrl1.SelfRefr1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:40, 代码来源:F16KbCacheFlushOnHalt.c
示例12: F15KvInitializeHtc
/**
* Entry point for enabling Hardware Thermal Control
*
* This function must be run after all P-State routines have been executed
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15KvInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
} else {
// Disable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0;
}
IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
return AGESA_SUCCESS;
}
开发者ID:fishbaoz, 项目名称:KaveriPI, 代码行数:47, 代码来源:cpuF15KvHtc.c
示例13: F10PmThermalInit
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 10h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F10PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 LocalPciRegister;
UINT32 Socket;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0;
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
开发者ID:Godkey, 项目名称:coreboot, 代码行数:41, 代码来源:cpuF10SoftwareThermal.c
示例14: F15TnInitializeCpb
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15TnInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
F15_PSTATE_MSR PstateMsrData;
UINT32 Pbx;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
break;
}
}
}
}
return AGESA_SUCCESS;
}
开发者ID:fishbaoz, 项目名称:KaveriPI, 代码行数:46, 代码来源:F15TnCpb.c
示例15: imc_reg_init
void imc_reg_init(void)
{
/* Init Power Management Block 2 (PM2) Registers.
* Check BKDG for AMD Family 16h for details. */
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
UINT8 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
PciData &= (UINT8)0x8F;
PciData |= 0x10;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
#endif
}
开发者ID:RafaelRMachado, 项目名称:Coreboot, 代码行数:29, 代码来源:imc.c
示例16: F12InitializeCpb
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
D18F4x15C_STRUCT CpbControl;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader);
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
CpbControl.Field.BoostSrc = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
SMUx0Bx8580.Value = 0;
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
开发者ID:AdriDlu, 项目名称:coreboot, 代码行数:48, 代码来源:F12Cpb.c
示例17: Fam10SetConfigAddrMap
/**
* Enable config access to a non-coherent chain for the given bus range.
*
* @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
*
* @param[in] ConfigMapIndex the map entry to set
* @param[in] SecBus The secondary bus number to use
* @param[in] SubBus The subordinate bus number to use
* @param[in] TargetNode The Node that shall be the recipient of the traffic
* @param[in] TargetLink The Link that shall be the recipient of the traffic
* @param[in] State our global state
* @param[in] Nb this northbridge
*/
VOID
Fam10SetConfigAddrMap (
IN UINT8 ConfigMapIndex,
IN UINT8 SecBus,
IN UINT8 SubBus,
IN UINT8 TargetNode,
IN UINT8 TargetLink,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT8 CurNode;
PCI_ADDR Reg;
UINT32 Temp;
Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
ASSERT (SecBus <= SubBus);
ASSERT (TargetNode <= State->NodesDiscovered);
ASSERT (TargetLink < Nb->MaxLinks);
Temp = SecBus;
Reg.Address.Register += HTHOST_ISOC_REG;
LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
((UINT32)TargetNode << 4) + (UINT32)3;
for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
MakePciBusFromNode (CurNode),
MakePciDeviceFromNode (CurNode),
CPU_ADDR_FUNC_01,
REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:48, 代码来源:htNbNonCoherentFam10.c
示例18: SetHtIoFrequencyRegisterBits
/**
* Set HT Frequency register for IO Devices
*
* Provide a common routine for accessing the HT Link Frequency registers at offset 8
* and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of
* AmdPCIWriteBits().
*
* @note This routine is called for IO Devices only!! All comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Reg the PCI config address the control register
* @param[in] Hibit the high bit number
* @param[in] Lobit the low bit number
* @param[in] Value the value to write to that bit range. Bit 0 => loBit.
* @param[in] State Our state, config handle for lib
*/
VOID
STATIC
SetHtIoFrequencyRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 Hibit,
IN UINT8 Lobit,
IN UINT32 *Value,
IN STATE_DATA *State
)
{
UINT32 Mask;
UINT32 Temp;
ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
ASSERT ((Hibit < 12) || (Lobit > 14));
// A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
if ((Hibit - Lobit) != 31) {
Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
} else {
Mask = (UINT32)0xFFFFFFFF;
}
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
Temp &= ~(Mask << Lobit);
Temp |= (*Value & Mask) << Lobit;
Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
开发者ID:B-Rich, 项目名称:coreboot, 代码行数:45, 代码来源:htFeatOptimization.c
示例19: ModifyCurrSocketPciMulti
/**
* Writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
VOID
ModifyCurrSocketPciMulti (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 LocalPciRegister;
AGESA_STATUS AgesaStatus;
PCI_ADDR Reg;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
Reg.Address.Function = PciAddress->Address.Function;
Reg.Address.Register = PciAddress->Address.Register;
LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
LocalPciRegister &= Mask;
LocalPciRegister |= Data;
LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
}
}
}
开发者ID:andy737, 项目名称:firebrickRemote, 代码行数:37, 代码来源:cpuPowerMgmtMultiSocket.c
示例20: SetHtControlRegisterBits
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