C++ LibAmdMsrWrite函数代码示例

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本文整理汇总了C++中LibAmdMsrWrite函数的典型用法代码示例。如果您正苦于以下问题：C++ LibAmdMsrWrite函数的具体用法？C++ LibAmdMsrWrite怎么用？C++ LibAmdMsrWrite使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。

在下文中一共展示了LibAmdMsrWrite函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。

示例1: F14OnLoadMicrocodePatchAtEarly

/**
 * Update microcode patch in current processor for Family14h ON.
 *
 * This function acts as a wrapper for calling the LoadMicrocodePatch
 * routine at AmdInitEarly.
 *
 *  @param[in]   FamilyServices      The current Family Specific Services.
 *  @param[in]   EarlyParams         Service parameters.
 *  @param[in]   StdHeader           Config handle for library and services.
 *
 */
VOID
F14OnLoadMicrocodePatchAtEarly (
  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT64 MsrValue;

  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
  // To load a microcode patch while using the cache as general storage,
  // the following steps are followed:
  // 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
  // 2. Load the microcode patch.
  // 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
  MsrValue = MsrValue | BIT7;
  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);

  LoadMicrocodePatch (StdHeader);

  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
  MsrValue = MsrValue & ~((UINT64)BIT7);
  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}

开发者ID:Godkey，项目名称:coreboot，代码行数:36，代码来源:F14OnInitEarlyTable.c

示例2: F15OrLoadMicrocodePatchAtEarly

/**
 * Update microcode patch in current processor for Family15h OR.
 *
 * This function acts as a wrapper for calling the LoadMicrocodePatch
 * routine at AmdInitEarly.
 *
 * This particualr version implements a workaround to a potential problem caused
 * when upgrading the microcode on Orochi B1 processors.
 *
 *  @param[in]   FamilyServices      The current Family Specific Services.
 *  @param[in]   EarlyParams         Service parameters.
 *  @param[in]   StdHeader           Config handle for library and services.
 *
 */
VOID
F15OrLoadMicrocodePatchAtEarly (
  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT64         MsrValue;
  UINT64         BuCfg2MsrValue;
  UINT64         CuCfgMsrValue;
  BOOLEAN        IsPatchLoaded;

  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);

  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {

    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesStart (StdHeader, &BuCfg2MsrValue);

    // Erratum #655
    // Set MSR C001_1023[1] = 1b, prior to writing to MSR C001_1020
    LibAmdMsrRead (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);
    MsrValue = CuCfgMsrValue | BIT1;
    LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader);

    IsPatchLoaded =  F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader);

    // Erratum #655
    // Restore MSR C001_1023[1] = previous setting
    LibAmdMsrWrite (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);

    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesEnd (StdHeader, &BuCfg2MsrValue);
    F15OrEarlySampleLoadMcuPatch.F15OrESAfterPatchLoaded (StdHeader, IsPatchLoaded);
  }
}

开发者ID:AdriDlu，项目名称:coreboot，代码行数:48，代码来源:F15OrInitEarlyTable.c

示例3: MemNInitializeMctC32

BOOLEAN
MemNInitializeMctC32 (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_DATA_STRUCT *MemPtr;
  S_UINT64 SMsr;

  MemPtr = NBPtr->MemPtr;

  if (NBPtr->Node == BSP_DIE) {
    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    if (SMsr.lo & ((UINT32)1 << 15)) {
      NBPtr->ClToNbFlag = 1;
    }
    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);

    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  }
  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}

开发者ID:AdriDlu，项目名称:coreboot，代码行数:25，代码来源:mnmctc32.c

示例4: MemRecNFinalizeMctDR

VOID
MemRecNFinalizeMctDR (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_DATA_STRUCT *MemPtr;
  S_UINT64 SMsr;

  MemPtr = NBPtr->MemPtr;


  // Recommended settings for F2x11C
  MemRecNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
  MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
  MemRecNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
  MemRecNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);

  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  if (!NBPtr->ClToNbFlag) {
    SMsr.lo &= ~((UINT32) 1 << 15);                // ClLinesToNbDis
  }
  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);

  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  SMsr.hi &= ~((UINT32) 1 << (48 - 32));               // WbEnhWsbDis
  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}

开发者ID:Jason-Lam，项目名称:coreboot，代码行数:27，代码来源:mrnmctdr.c

示例5: MemNFinalizeMctDr

BOOLEAN
MemNFinalizeMctDr (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_DATA_STRUCT *MemPtr;
  S_UINT64 SMsr;

  MemPtr = NBPtr->MemPtr;

  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
  // Recommended settings for F2x11C
  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);

  if (NBPtr->Node == BSP_DIE) {
    if (!NBPtr->ClToNbFlag) {
      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    }

    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  }

  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}

开发者ID:AdriDlu，项目名称:coreboot，代码行数:34，代码来源:mnmctdr.c

示例6: F16MlWriteNormalizer

/**
 * Family specific code for writing normalizer.
 *
 * @param[in]  FiveBitExponent         The current CPU's family services.
 * @param[in]  FiveBitMantissa         Timepoint designator.
 * @param[in]  StdHeader               Config handle for library and services.
 *
 */
VOID
STATIC
F16MlWriteNormalizer (
  IN       UINT8               FiveBitExponent,
  IN       UINT8               FiveBitMantissa,
  IN       AMD_CONFIG_PARAMS   *StdHeader
  )
{
  D0F0xBC_x3F98C_STRUCT       D0F0xBC_x3F98C;
  C001_1073_MSR               LocalMsrRegister;

  LibAmdMsrRead (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);

  //Write normalizer as 5-bit exponent and 5 bit mantissa to MSRC001_1073[Exp/Man] and D0F0xBC_x3F98C[Exp/Man]
  LocalMsrRegister.Exponent = FiveBitExponent;
  LocalMsrRegister.Mantissa = FiveBitMantissa;
  LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);

  GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_x3F98C_TYPE, D0F0xBC_x3F98C_ADDRESS, &D0F0xBC_x3F98C, 0, StdHeader);
  D0F0xBC_x3F98C.Field.Exponent = FiveBitExponent;
  D0F0xBC_x3F98C.Field.Mantissa = FiveBitMantissa;
  GnbRegisterWriteML (GnbGetHandle (StdHeader), D0F0xBC_x3F98C_TYPE, D0F0xBC_x3F98C_ADDRESS, &D0F0xBC_x3F98C, 0, StdHeader);

  // Toggle the Ready bit to ensure proper operation.
  LocalMsrRegister.Ready = 0;
  LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);

  LocalMsrRegister.Ready = 1;
  LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);

  IDS_SKIP_HOOK (IDS_MSR_ACCESS_OVERRIDE, NULL, StdHeader) {
    LocalMsrRegister.Lock = 1;
    LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
  }

开发者ID:fishbaoz，项目名称:MullinsPI，代码行数:42，代码来源:F16MlScs.c

示例7: F15SetBrandIdRegistersAtEarly

/**
 * Set the Processor Name String register based on F5x194/198
 *
 * This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
 *
 *  @param[in]   FamilyServices      The current Family Specific Services.
 *  @param[in]   EarlyParams         Service parameters.
 *  @param[in]   StdHeader           Config handle for library and services.
 *
 */
VOID
F15SetBrandIdRegistersAtEarly (
  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT32 PciData;
  UINT32 ExceptionId;
  UINT32 MsrIndex;
  UINT64 MsrData;
  UINT64 *MsrNameStringPtrPtr;
  PCI_ADDR PciAddress;

  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
    if (IsException (&ExceptionId, StdHeader)) {
      ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));

      MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
    } else {
      OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
      PciAddress.Address.Function = FUNC_5;
      PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
      // check if D18F5x198_x0 is 00000000h.
      PciData = 0;
      LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
      PciAddress.Address.Register = NAME_STRING_DATA_PORT;
      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
      if (PciData != 0) {
        for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
          PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
          PciData = MsrIndex * 2;
          LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
          PciAddress.Address.Register = NAME_STRING_DATA_PORT;
          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
          ((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;

          PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
          PciData = (MsrIndex * 2) + 1;
          LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
          PciAddress.Address.Register = NAME_STRING_DATA_PORT;
          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
          ((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;

          LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
        }
        return;
      } else {
        // It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
        MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
      }
    }
    // Put values into name MSRs,  Always write the full 48 bytes
    for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
      LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
      MsrNameStringPtrPtr++;
    }
  }
}

开发者ID:B-Rich，项目名称:coreboot，代码行数:69，代码来源:cpuF15BrandId.c

示例8: F10PmPwrPlaneInitPviCore

/**
 * Support routine for F10CpuAmdPmPwrPlaneInit.
 *
 * This function implements step 1 on each core.
 *
 * @param[in]  StdHeader          Config handle for library and services.
 *
 */
VOID
STATIC
F10PmPwrPlaneInitPviCore (
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  UINT32 MsrAddr;
  UINT32 NbVid;
  UINT32 CpuVid;
  UINT64 MsrRegister;

  for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
      NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
      CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
      if (NbVid != CpuVid) {
        if (NbVid > CpuVid) {
          NbVid = CpuVid;
        }
        ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
        ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
        LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
      }
    }
  }
}

开发者ID:Godkey，项目名称:coreboot，代码行数:35，代码来源:cpuF10PowerPlane.c

示例9: Update800MHzHtcPstateTo900MHz

/**
 *  Workaround for CPUs with a minimum P-state = 800MHz.
 *
 *  AGESA should change the frequency of 800MHz P-states to 900MHz.
 *
 * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
 * @param[in]   StdHeader    Config handle for library and services.
 *
 */
VOID
STATIC
Update800MHzHtcPstateTo900MHz (
  IN       UINT32             Data,
  IN       AMD_CONFIG_PARAMS  *StdHeader
  )
{
  PCI_ADDR      PciAddress;
  PSTATE_MSR    HtcPstate;
  PSTATE_MSR    HtcPstateMinus1;
  HTC_REGISTER  HtcRegister;

  PciAddress.AddressValue = HTC_PCI_ADDR;
  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &HtcRegister, StdHeader);

  LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);

  if (HtcPstate.CpuFid == 0 && HtcPstate.CpuDid == 1) {
    if (HtcRegister.HtcPstateLimit == 0) {
      HtcPstateMinus1 = HtcPstate;
    } else {
      LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0 - 1), (UINT64 *) &HtcPstateMinus1, StdHeader);
    }
    HtcPstate.CpuVid = HtcPstateMinus1.CpuVid;
    HtcPstate.CpuFid = 2;
    LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
  }
}

开发者ID:andy737，项目名称:firebrickRemote，代码行数:37，代码来源:F15TnSharedMsrTable.c

示例10: MemRecUSetTargetWTIO

VOID
STATIC
MemRecUSetTargetWTIO (
  IN       UINT32 Address,
  IN OUT   MEM_DATA_STRUCT *MemPtr
  )
{
  S_UINT64 SMsr;

  SMsr.lo = Address;
  SMsr.hi = 0;
  LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader);          // ;IORR0 Base
  SMsr.hi = 0xFFFF;
  SMsr.lo = 0xFC000800;
  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);          // ;64MB Mask
}

开发者ID:AdriDlu，项目名称:coreboot，代码行数:16，代码来源:mruc.c

示例11: McaInitialization

/**
 * Initialize Machine Check Architecture registers
 *
 * This function initializes the MCA MSRs.  On cold reset, these registers
 * have an invalid data that must be cleared on all cores.
 *
 * @param[in]  StdHeader         Config handle for library and services
 *
 *---------------------------------------------------------------------------------------
 */
VOID
McaInitialization (
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  UINT16      TempVar16_a;
  UINT32      MsrAddress;
  UINT64      MsrData;
  CPUID_DATA  CpuIdDataStruct;

  if (!(IsWarmReset (StdHeader))) {
    // Run CPUID to verify that the processor supports MCE and MCA
    // i.e. edx[7], and edx[14]
    // CPUID_MODEL = 1
    LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader);
    if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) {
      // Check to see if the MCG_CTL_P bit is set
      // MCG = Global Machine Check Exception Reporting Control Register
      LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
      if ((MsrData & MCG_CTL_P) != 0) {
        TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2);
        TempVar16_a += MSR_MC0_CTL;

        // Initialize the data
        MsrData = 0;
        for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) {
          LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader);
        }
      }
    }
  }
}

开发者ID:andy737，项目名称:firebrickRemote，代码行数:42，代码来源:cpuEarlyInit.c

示例12: F16MlProgramWeights

/**
 * Family specific code for programming weights.
 *
 * @param[in]  *SmuCpuInfoPtr          Pointer to Smu data.
 * @param[in]  StdHeader               Config handle for library and services.
 *
 * @retval     AGESA_SUCCESS           Normalizer and weights programmed
 * @retval     AGESA_ERROR             Unable to locate Smu data, or error in Smu data
 *
 */
AGESA_STATUS
STATIC
F16MlProgramWeights (
  IN       SMU_RAM_CPU_INFO       *SmuCpuInfoPtr,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT32              i;
  C001_1072_MSR       PowerMonitorWeights;

  // If we get valid data, but number of counts is incorrect for Mullins, panic !
  ASSERT (SmuCpuInfoPtr->CountApmWeights == WEIGHTS);
  if (SmuCpuInfoPtr->CountApmWeights != WEIGHTS) {
    PutEventLog (AGESA_ERROR,
                 (CPU_EVENT_SCS_INITIALIZATION_ERROR + AGESA_SCS_WEIGHTS_MISMATCH),
                 0, 0, 0, 0, StdHeader);
    return AGESA_ERROR;
  }

  // Process table and program the Power Monitor Weights (MSRC001_1072)
  for (i = 0; i < SmuCpuInfoPtr->CountApmWeights; i++) {
    PowerMonitorWeights.ArrayIndex = i;
    PowerMonitorWeights.WriteCmd = 1;
    PowerMonitorWeights.WriteData = SmuCpuInfoPtr->MSRApmWeights[i].Weight;
    LibAmdMsrWrite (MSR_C001_1072, (UINT64 *) (&PowerMonitorWeights), StdHeader);
  }
  return AGESA_SUCCESS;
}

开发者ID:fishbaoz，项目名称:MullinsPI，代码行数:38，代码来源:F16MlScs.c

示例13: MemNFinalizeMctDA

BOOLEAN
MemNFinalizeMctDA (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  UINT8 Dct;
  MEM_DATA_STRUCT *MemPtr;
  S_UINT64 SMsr;

  MemPtr = NBPtr->MemPtr;
  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
  // Recommended settings for F2x11C
  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
  // For power saving
  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
    NBPtr->SwitchDCT (NBPtr, Dct);
    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
      if (NBPtr->ChannelPtr->Dimmx4Present == 0) {
        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80));
      }
      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10));
      }
      MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01));
    }
  }

  if (NBPtr->Node == BSP_DIE) {
    if (!NBPtr->ClToNbFlag) {
      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    }

    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  }

  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}

开发者ID:Godkey，项目名称:coreboot，代码行数:47，代码来源:mnmctda.c

示例14: MemNFinalizeMctC32

BOOLEAN
MemNFinalizeMctC32 (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_DATA_STRUCT *MemPtr;
  S_UINT64 SMsr;
  UINT16 Speed;
  UINT32 ExtMctCfgLoRegVal;

  MemPtr = NBPtr->MemPtr;
  Speed = NBPtr->DCTPtr->Timings.Speed;
  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);

  ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
  ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;

  ExtMctCfgLoRegVal &= 0x0FFFFFFF;
  if (Speed == DDR667_FREQUENCY) {
    ExtMctCfgLoRegVal |= 0x40000000;
  } else if (Speed == DDR800_FREQUENCY) {
    ExtMctCfgLoRegVal |= 0x50000000;
  } else if (Speed == DDR1066_FREQUENCY) {
    ExtMctCfgLoRegVal |= 0x60000000;
  } else if (Speed == DDR1333_FREQUENCY) {
    ExtMctCfgLoRegVal |= 0x80000000;
  } else {
    ExtMctCfgLoRegVal |= 0x90000000;
  }
  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);

  if (NBPtr->Node == BSP_DIE) {
    if (!NBPtr->ClToNbFlag) {
      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    }

    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
  }

  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
}

开发者ID:Godkey，项目名称:coreboot，代码行数:45，代码来源:mnmctc32.c

示例15: IdsPerfAnalyseTimestamp

/**
 * Output Test Point function .
 *
 *  @param[in,out] StdHeader    The Pointer of Standard Header.
 *
 *  @retval AGESA_SUCCESS       Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
 *  @retval AGESA_ERROR         Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
 *
 **/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
  IN OUT   AMD_CONFIG_PARAMS *StdHeader
  )
{
  AGESA_STATUS status;
  LOCATE_HEAP_PTR LocateHeapStructPtr;
  UINT32 TscRateInMhz;
  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
  IDS_CALLOUT_STRUCT IdsCalloutData;
  AGESA_STATUS Status;

  PERFREGBACKUP PerfReg;
  UINT32 CR4reg;
  UINT64 SMsr;

  LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
  LocateHeapStructPtr.BufferPtr = NULL;
  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
  if (status != AGESA_SUCCESS) {
    return status;
  }
  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
  FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
  ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
  ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->Version = IDS_PERF_VERSION;

  IdsCalloutData.IdsNvPtr = NULL;
  IdsCalloutData.StdHeader = *StdHeader;
  IdsCalloutData.Reserved = 0;
  Status = AgesaGetIdsData (IDS_CALLOUT_GET_PERF_BUFFER, &IdsCalloutData);

  //Check if Platform BIOS provide a buffer to copy
  if ((Status == AGESA_SUCCESS) && (IdsCalloutData.Reserved != 0)) {
    LibAmdMemCopy ((VOID *)IdsCalloutData.Reserved, LocateHeapStructPtr.BufferPtr, sizeof (TP_Perf_STRUCT), StdHeader);
  } else {
    //No platform performance buffer provide, use the default HDTOUT output
    if (AmdIdsHdtOutSupport () == FALSE) {
    //Init break point
      IdsPerfSaveReg (&PerfReg, StdHeader);

      LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
      SMsr |= 1;
      LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);

      LibAmdWriteCpuReg (DR2_REG, 0x99cc);
      LibAmdWriteCpuReg (DR7_REG, 0x02000420);

      LibAmdReadCpuReg (CR4_REG, &CR4reg);
      LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));

      IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader);
      IdsPerfRestoreReg (&PerfReg, StdHeader);
    }
  }
  return status;
}

开发者ID:fishbaoz，项目名称:edk2ml，代码行数:66，代码来源:IdsPerf.c

示例16: F10InitializeHwC1eOnCore

/**
 *  Enable Hardware C1e on a family 10h core.
 *
 * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
 * @param[in]    StdHeader          Config Handle for library, services.
 *
 */
VOID
STATIC
F10InitializeHwC1eOnCore (
  IN       VOID *IntPendMsr,
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  UINT64  MsrRegister;

  // Enable C1e
  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);

  // Set OS Visible Workaround Status BIT1 to indicate that C1e
  // is enabled.
  LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
  MsrRegister |= BIT1;
  LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
}

开发者ID:Godkey，项目名称:coreboot，代码行数:25，代码来源:F10RevCHwC1e.c

示例17: F14InitializeIoCstateOnCore

/**
 *  Enable C-State on a family 14h core.
 *
 * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
 * @param[in]    StdHeader          Config Handle for library, services.
 *
 */
VOID
STATIC
F14InitializeIoCstateOnCore (
  IN       VOID *CstateBaseMsr,
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  // Initialize MSRC001_0073[CstateAddr] on each core
  LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}

开发者ID:michaelforney，项目名称:coreboot，代码行数:17，代码来源:F14IoCstate.c

示例18: PSPProgBar3Msr

void PSPProgBar3Msr(void *Buffer)
{
	u32 Bar3Addr;
	u64 Tmp64;
	/* Get Bar3 Addr */
	Bar3Addr = PspLibPciReadPspConfig(0x20);
	Tmp64 = Bar3Addr;
	printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
	LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
	LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
}

开发者ID:siro20，项目名称:coreboot，代码行数:11，代码来源:model_15_init.c

示例19: PmNbCofVidInitP0P1Core

/**
 * Cold reset support routine for F10PmNbCofVidInit.
 *
 * This function implements steps 3, 4, & 5 on each core.
 *
 * @param[in]  NewNbVid           NewNbVid determined by core 0 in step 2.
 * @param[in]  StdHeader          Config handle for library and services.
 *
 */
VOID
STATIC
PmNbCofVidInitP0P1Core (
  IN       VOID *NewNbVid,
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  UINT32 MsrAddress;
  UINT64 MsrRegister;
  CPU_SPECIFIC_SERVICES *FamilySpecificServices = NULL;

  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
  LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
  ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
  LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}

开发者ID:Godkey，项目名称:coreboot，代码行数:29，代码来源:F10PmNbCofVidInit.c

示例20: MemRecUResetTargetWTIO

VOID
STATIC
MemRecUResetTargetWTIO (
  IN OUT   MEM_DATA_STRUCT *MemPtr
  )
{
  S_UINT64 Smsr;
  Smsr.hi = 0;
  Smsr.lo = 0;
  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
}

开发者ID:AdriDlu，项目名称:coreboot，代码行数:11，代码来源:mruc.c

注：本文中的LibAmdMsrWrite函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。

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C++ LibAmdMsrWrite函数代码示例

示例1: F14OnLoadMicrocodePatchAtEarly

示例2: F15OrLoadMicrocodePatchAtEarly

示例3: MemNInitializeMctC32

示例4: MemRecNFinalizeMctDR

示例5: MemNFinalizeMctDr

示例6: F16MlWriteNormalizer

示例7: F15SetBrandIdRegistersAtEarly

示例8: F10PmPwrPlaneInitPviCore

示例9: Update800MHzHtcPstateTo900MHz

示例10: MemRecUSetTargetWTIO

示例11: McaInitialization

示例12: F16MlProgramWeights

示例13: MemNFinalizeMctDA

示例14: MemNFinalizeMctC32

示例15: IdsPerfAnalyseTimestamp

示例16: F10InitializeHwC1eOnCore

示例17: F14InitializeIoCstateOnCore

示例18: PSPProgBar3Msr

示例19: PmNbCofVidInitP0P1Core

示例20: MemRecUResetTargetWTIO

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