def implement_fsm(states):
	stnames = ["S" + str(i) for i in range(len(states))]
	fsm = FSM(*stnames)
	lans = _LowerAbstractNextState(fsm, states, stnames)
	for i, state in enumerate(states):
		actions = lans.visit(state)
		fsm.act(getattr(fsm, stnames[i]), *actions)
	return fsm

    def __init__(self):

        self.busy = Signal()
        self.sink = Sink(CMD_REC)
        self.source = Source([('d',8), ('last',1)])

        sm = FSM(reset_state="IDLE")
        self.submodules += sm

        self.comb += [
            self.source.stb.eq(0),
            self.source.payload.last.eq(0)
            ]


        ssum = Signal(8)

        token_next = Record(CMD_REC)
        token = Record(CMD_REC)
        self.comb += token_next.eq(token)
        self.sync += token.eq(token_next)

        sm.act("IDLE",
                If(self.sink.stb,
                    self.sink.ack.eq(1),
                    token_next.eq(self.sink.payload),
                    NextState('c0')))

        _outs = [
            0x55,
            Cat(token.a[8:14], 0, token.wr),
            token.a[0:8],
            token.d,
            ssum
            ]

        s = _outs[0]
        for i in _outs[1:-1]:
            s = s + i
        self.sync += ssum.eq(s)


        for c, v in enumerate(_outs):
            _last = 1 if c == len(_outs) - 1 else 0
            _next = "IDLE" if _last else "c%d" % (c + 1)
            sm.act("c%d" % c,
                    self.source.stb.eq(1),
                    self.source.payload.d.eq(v),
                    self.source.payload.last.eq(_last),
                    If(self.source.ack,
                        NextState(_next)
                        ))

    def __init__(self, sys_clk_freq):
        self.qpll_reset = Signal()
        self.qpll_lock = Signal()
        self.tx_reset = Signal()
        self.done = Signal()

        # Handle async signals
        qpll_reset = Signal()
        tx_reset = Signal()
        self.sync += [
            self.qpll_reset.eq(qpll_reset),
            self.tx_reset.eq(tx_reset)
        ]
        self.qpll_reset.attr.add("no_retiming")
        self.tx_reset.attr.add("no_retiming")
        qpll_lock = Signal()
        self.specials += MultiReg(self.qpll_lock, qpll_lock)

        # After configuration, transceiver resets have to stay low for
        # at least 500ns.
        # See https://www.xilinx.com/support/answers/43482.html
        timer_max = ceil(500e-9*sys_clk_freq)
        timer = Signal(max=timer_max+1)
        tick = Signal()
        self.sync += [
            tick.eq(0),
            If(timer == timer_max,
                tick.eq(1),
                timer.eq(0)
            ).Else(
                timer.eq(timer + 1)
            )
        ]

        fsm = FSM()
        self.submodules += fsm

        fsm.act("WAIT",
            If(tick, NextState("QPLL_RESET"))
        )
        fsm.act("QPLL_RESET",
            tx_reset.eq(1),
            qpll_reset.eq(1),
            If(tick, NextState("WAIT_QPLL_LOCK"))
        )
        fsm.act("WAIT_QPLL_LOCK",
            tx_reset.eq(1),
            If(qpll_lock & tick, NextState("DONE"))
        )
        fsm.act("DONE",
            self.done.eq(1)
        )

    def __init__(self, has_completion=True):
        self.cmd = Endpoint(CMD_REC)
        self.sink = self.cmd

        if has_completion:
            self.completion = Endpoint(CMD_REC)
            self.source = self.completion

        self.master = Interface()

        self.busy = Signal()

        self.comb += [ 
                self.cmd.ack.eq(0)
                ]

        samp_comp = Signal()

        if has_completion:
            self.sync += If(self.cmd.ack, 
                    self.completion.payload.a.eq(self.cmd.payload.a),
                    self.completion.payload.wr.eq(self.cmd.payload.wr),
                    If(self.cmd.payload.wr,
                        self.completion.payload.d.eq(self.master.dat_w))
                    )

            self.sync += If(samp_comp & ~self.completion.payload.wr,
                    self.completion.payload.d.eq(self.master.dat_r))


        fsm = FSM()
        fsm.act("IDLE",
                If(self.cmd.stb,
                    self.cmd.ack.eq(1),
                    self.master.we.eq(self.cmd.payload.wr),
                    self.master.adr.eq(self.cmd.payload.a),
                    self.master.dat_w.eq(self.cmd.payload.d),
                    NextState("READ")))
        fsm.act("READ",
                samp_comp.eq(1),
                NextState("WAIT"))

        if has_completion:
            fsm.act("WAIT",
                    self.completion.stb.eq(1),
                    If(self.completion.ack, NextState("IDLE")))
        else:
            fsm.act("WAIT", NextState("IDLE"))

        self.submodules += fsm

    def __init__(self, stream_slicer):
        self.source = stream.Endpoint(record_layout)
        self.end_marker_found = Signal()
        self.flush = Signal()

        hdrlen = (layout_len(record_layout) - 512)//8
        record_raw = Record(record_layout)
        self.comb += [
            record_raw.raw_bits().eq(stream_slicer.source),
            self.source.channel.eq(record_raw.channel),
            self.source.timestamp.eq(record_raw.timestamp),
            self.source.address.eq(record_raw.address),
            Case(record_raw.length,
                {hdrlen+i: self.source.data.eq(record_raw.data[:i*8])
                 for i in range(1, 512//8+1)}),
        ]

        fsm = FSM(reset_state="FLOWING")
        self.submodules += fsm

        fsm.act("FLOWING",
            If(stream_slicer.source_stb,
                If(record_raw.length == 0,
                    NextState("END_MARKER_FOUND")
                ).Else(
                    self.source.stb.eq(1)
                )
            ),
            If(self.source.ack,
                stream_slicer.source_consume.eq(record_raw.length)
            )
        )
        fsm.act("END_MARKER_FOUND",
            self.end_marker_found.eq(1),
            If(self.flush,
                stream_slicer.flush.eq(1),
                NextState("WAIT_FLUSH")
            )
        )
        fsm.act("WAIT_FLUSH",
            If(stream_slicer.flush_done,
                NextState("SEND_EOP")
            )
        )
        fsm.act("SEND_EOP",
            self.source.eop.eq(1),
            self.source.stb.eq(1),
            If(self.source.ack, NextState("FLOWING"))
        )

    def __init__(self, cycle_bits, data_bits, def_end_cycle=20):
        # I/O signals
        self.d = Signal()
        self.clk = Signal()

        # control signals
        self.pds = Signal()
        self.pdi = Signal(data_bits)

        self.clk_high = Signal()
        self.clk_low = Signal()

        self.eoc = Signal()
        self.ev_clk_high = Signal()
        self.ev_clk_low = Signal()
        self.ev_data = Signal()

        # FSM
        self.fsm = FSM()
        self.start_action = [NextState("TRANSFER_DATA")]
        self.end_action = [NextState("WAIT_DATA")]

        # registers
        self._pos_end_cycle = CSRStorage(cycle_bits, reset=def_end_cycle)
        self._pos_data = CSRStorage(cycle_bits, reset=0)

        ###

        # cycle counter and events
        cycle_counter = Signal(cycle_bits)
        self.cycle_counter_reset = Signal()
        self.comb += self.eoc.eq(cycle_counter == self._pos_end_cycle.storage)
        self.sync += If(self.eoc | self.cycle_counter_reset, cycle_counter.eq(0)).Else(
            cycle_counter.eq(cycle_counter + 1)
        )

        self.comb += [
            self.ev_clk_high.eq(cycle_counter == (self._pos_end_cycle.storage >> 1)),
            self.ev_clk_low.eq(cycle_counter == self._pos_end_cycle.storage),
            self.ev_data.eq(cycle_counter == self._pos_data.storage),
        ]

        # data
        sr = Signal(data_bits)
        self.sr_load = Signal()
        self.sr_shift = Signal()
        self.remaining_data = Signal(max=data_bits + 1)
        self.sync += If(self.sr_load, sr.eq(self.pdi), self.remaining_data.eq(data_bits)).Elif(
            self.sr_shift, sr.eq(sr[1:]), self.d.eq(sr[0]), self.remaining_data.eq(self.remaining_data - 1)
        )

        # clock
        clk_p = Signal()
        self.sync += [If(self.clk_high, clk_p.eq(1)).Elif(self.clk_low, clk_p.eq(0)), self.clk.eq(clk_p)]

	def __init__(self):
		self.s = Signal()
		myfsm = FSM()
		self.submodules += myfsm
		myfsm.act("FOO", self.s.eq(1), NextState("BAR"))
		myfsm.act("BAR", self.s.eq(0), NextState("FOO"))
		self.be = myfsm.before_entering("FOO")
		self.ae = myfsm.after_entering("FOO")
		self.bl = myfsm.before_leaving("FOO")
		self.al = myfsm.after_leaving("FOO")

	def __init__(self, pads):
		self.source = source = Source(eth_description(8))

		###

		sop = source.sop
		set_sop = Signal()
		clr_sop = Signal()
		self.sync += \
			If(clr_sop,
				sop.eq(0)
			).Elif(set_sop,
				sop.eq(1)
			)

		lo = Signal(4)
		hi = Signal(4)
		load_nibble = Signal(2)
		self.sync  += \
			If(load_nibble[0],
				lo.eq(pads.rx_data)
			).Elif(load_nibble[1],
				hi.eq(pads.rx_data)
			)
		self.comb += [
			source.d.eq(Cat(lo, hi))
		]

		fsm = FSM(reset_state="IDLE")
		self.submodules += fsm
		fsm.act("IDLE",
			set_sop.eq(1),
			If(pads.dv,
				load_nibble.eq(0b01),
				NextState("LOAD_HI")
			)
		)
		fsm.act("LOAD_LO",
			source.stb.eq(1),
			If(pads.dv,
				clr_sop.eq(1),
				load_nibble.eq(0b01),
				NextState("LOAD_HI")
			).Else(
				source.eop.eq(1),
				NextState("IDLE")
			)
		)
		fsm.act("LOAD_HI",
			load_nibble.eq(0b10),
			NextState("LOAD_LO")
		)

    def __init__(self):
        self.counter = Signal(8)

        myfsm = FSM()
        self.submodules += myfsm

        self.sync += self.counter.eq(self.counter + 1)
        self.sync += If(self.counter > 235, myfsm.act("COAST",
            If(self.counter == 240, NextState("IDLE"))
        ))
        myfsm.act("IDLE",
            If(self.counter == 10, NextState("START"))
        )
        myfsm.act("START",
            If(self.counter == 100, NextState("RUNNING"))
        )
        myfsm.act("RUNNING",
            If(self.counter == 200, NextState("COAST"))
        )

	def __init__(self, d_w):
		self.sink = Sink(eth_description(d_w))
		self.source = Source(eth_description(d_w))

		###

		preamble = Signal(64, reset=eth_preamble)
		cnt_max = (64//d_w)-1
		cnt = Signal(max=cnt_max+1)
		clr_cnt = Signal()
		inc_cnt = Signal()

		self.sync += \
			If(clr_cnt,
				cnt.eq(0)
			).Elif(inc_cnt,
				cnt.eq(cnt+1)
			)

		fsm = FSM(reset_state="IDLE")
		self.submodules += fsm
		fsm.act("IDLE",
			self.sink.ack.eq(1),
			clr_cnt.eq(1),
			If(self.sink.stb & self.sink.sop,
				self.sink.ack.eq(0),
				NextState("INSERT"),
			)
		)
		fsm.act("INSERT",
			self.source.stb.eq(1),
			self.source.sop.eq(cnt==0),
			chooser(preamble, cnt, self.source.d),
			If(cnt == cnt_max,
				If(self.source.ack, NextState("COPY"))
			).Else(
				inc_cnt.eq(self.source.ack)
			)
		)
		fsm.act("COPY",
			Record.connect(self.sink, self.source),
			self.source.sop.eq(0),

			If(self.sink.stb & self.sink.eop & self.source.ack,
				NextState("IDLE"),
			)
		)

	def __init__(self, crc_class, layout):
		self.sink = sink = Sink(layout, True)
		self.source = source = Source(layout, True)
		self.busy = Signal()

		###

		dw = flen(sink.d)
		self.submodules.crc = crc_class(dw)

		fsm = FSM(reset_state="RESET_CRC")
		self.submodules += fsm

		fsm.act("RESET_CRC",
			sink.ack.eq(0),
			self.crc.reset.eq(1),
			NextState("IDLE")
		)
		fsm.act("IDLE",
			sink.ack.eq(sink.stb),
			If(sink.stb & sink.sop,
				Record.connect(sink, source),
				self.crc.ce.eq(sink.ack),
				self.crc.d.eq(sink.d),
				NextState("COPY")
			)
		)
		fsm.act("COPY",
			Record.connect(sink, source),
			self.crc.ce.eq(sink.stb & sink.ack),
			self.crc.d.eq(sink.d),
			source.error.eq(sink.eop & self.crc.error),
			If(sink.stb & sink.ack & sink.eop,
				NextState("RESET_CRC")
			)
		)
		self.comb += self.busy.eq(~fsm.ongoing("IDLE"))

	def __init__(self, rx0, tx0, rx1, tx1, rd_port, wr_port, c_pci_data_width=32, wordsize=32, ptrsize=64, npagesincache=4, pagesize=4096):

		self.cmd_rx = rx0
		self.cmd_tx = tx0
		self.data_rx = rx1
		self.data_tx = tx1

		self.rd_port = rd_port
		self.wr_port = wr_port

		self.virt_addr = Signal(ptrsize)
		self.page_addr = Signal(log2_int(npagesincache))
		self.send_req = Signal()
		self.fetch_req = Signal()
		self.req_complete = Signal()

		##

		# fix start signals
		cmd_rx_start_prev = Signal()
		data_rx_start_prev = Signal()

		self.sync += cmd_rx_start_prev.eq(self.cmd_rx.start), data_rx_start_prev.eq(self.data_rx.start)

		cmd_rx_transaction_requested = Signal()
		data_rx_transaction_requested = Signal()

		cmd_rx_transaction_ack = Signal()
		data_rx_transaction_ack = Signal()

		self.sync += If(cmd_rx_transaction_ack, cmd_rx_transaction_requested.eq(0)).Elif(~cmd_rx_transaction_requested & (self.cmd_rx.start == 1) & (cmd_rx_start_prev == 0), cmd_rx_transaction_requested.eq(1))
		self.sync += If(data_rx_transaction_ack, data_rx_transaction_requested.eq(0)).Elif(~data_rx_transaction_requested & (self.data_rx.start == 1) & (data_rx_start_prev == 0), data_rx_transaction_requested.eq(1))


		# constant definitions
		memorywidth = max(c_pci_data_width, wordsize)
		memorysize = npagesincache*pagesize*8//memorywidth

		pcie_word_adr_nbits = log2_int(memorywidth//32)
		num_tx_off = log2_int(c_pci_data_width//32)

		num_tx_per_word = max(1, wordsize//c_pci_data_width)

		words_per_line = c_pci_data_width//wordsize if c_pci_data_width > wordsize else wordsize//c_pci_data_width

		page_adr_nbits = log2_int(npagesincache)
		line_adr_nbits = log2_int(pagesize*8//memorywidth)
		word_adr_nbits = log2_int(words_per_line)
		byte_adr_nbits = log2_int(wordsize//8)

		word_adr_off = byte_adr_nbits
		line_adr_off = log2_int(memorywidth//8)
		page_tag_off = line_adr_nbits + line_adr_off

		page_tag_nbits = ptrsize - page_tag_off

		# variables

		virt_addr_internal = Signal(ptrsize)
		page_addr_internal = Signal(ptrsize)

		rxcount = Signal(32)
		txcount = Signal(32)
		wordcount = Signal(32)
		rlen = Signal(32)

		# state machine that controls page cache
		fsm = FSM()
		self.submodules += fsm

		fsm.act("IDLE", #0
			#reset internal registers
			NextValue(rxcount, 0),
			NextValue(txcount, 0),
			NextValue(wordcount, 0),
			NextValue(rlen, 0),
			self.req_complete.eq(1),
			If(self.send_req,
				NextValue(virt_addr_internal, self.virt_addr),
				NextValue(page_addr_internal, self.page_addr),
				NextState("TX_DIRTY_PAGE_INIT")
			).Elif(self.fetch_req,
				NextValue(virt_addr_internal, self.virt_addr),
				NextValue(page_addr_internal, self.page_addr),
				NextState("TX_PAGE_FETCH_CMD")
			)
		)

		fsm.act("REQ_COMPLETE",
			self.req_complete.eq(1),
			NextState("IDLE")
		)

		# page send

		fsm.act("TX_DIRTY_PAGE_INIT", #4
			self.data_tx.start.eq(1),
			self.data_tx.len.eq(pagesize//4),
			self.data_tx.last.eq(1),
			NextValue(txcount, c_pci_data_width//32),
#.........这里部分代码省略.........

	def __init__(self, lasmim, nslots):
		bus_aw = lasmim.aw
		bus_dw = lasmim.dw
		alignment_bits = bits_for(bus_dw//8) - 1

		fifo_word_width = 24*bus_dw//32
		self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
		self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
		self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
		self.ev = self._slot_array.ev

		###

		# address generator + maximum memory word count to prevent DMA buffer overrun
		reset_words = Signal()
		count_word = Signal()
		last_word = Signal()
		current_address = Signal(bus_aw)
		mwords_remaining = Signal(bus_aw)
		self.comb += [
			self._slot_array.address_reached.eq(current_address),
			last_word.eq(mwords_remaining == 1)
		]
		self.sync += [
			If(reset_words,
				current_address.eq(self._slot_array.address),
				mwords_remaining.eq(self._r_frame_size.storage)
			).Elif(count_word,
				current_address.eq(current_address + 1),
				mwords_remaining.eq(mwords_remaining - 1)
			)
		]

		# 24bpp -> 32bpp
		memory_word = Signal(bus_dw)
		pixbits = []
		for i in range(bus_dw//32):
			for j in range(3):
				b = (i*3+j)*8
				pixbits.append(self.frame.payload.pixels[b+6:b+8])
				pixbits.append(self.frame.payload.pixels[b:b+8])
			pixbits.append(0)
			pixbits.append(0)
		self.comb += memory_word.eq(Cat(*pixbits))

		# bus accessor
		self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
		self.comb += [
			self._bus_accessor.address_data.payload.a.eq(current_address),
			self._bus_accessor.address_data.payload.d.eq(memory_word)
		]

		# control FSM
		fsm = FSM()
		self.submodules += fsm

		fsm.act("WAIT_SOF",
			reset_words.eq(1),
			self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.payload.sof),
			If(self._slot_array.address_valid & self.frame.payload.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
		)
		fsm.act("TRANSFER_PIXELS",
			self.frame.ack.eq(self._bus_accessor.address_data.ack),
			If(self.frame.stb,
				self._bus_accessor.address_data.stb.eq(1),
				If(self._bus_accessor.address_data.ack,
					count_word.eq(1),
					If(last_word, NextState("EOF"))
				)
			)
		)
		fsm.act("EOF",
			If(~self._bus_accessor.busy,
				self._slot_array.address_done.eq(1),
				NextState("WAIT_SOF")
			)
		)

	def __init__(self, pads, default=_default_edid):
		self.specials.mem = Memory(8, 128, init=default)

		###

		scl_raw = Signal()
		sda_i = Signal()
		sda_drv = Signal()
		_sda_drv_reg = Signal()
		_sda_i_async = Signal()
		self.sync += _sda_drv_reg.eq(sda_drv)
		self.specials += [
			MultiReg(pads.scl, scl_raw),
			Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
			MultiReg(_sda_i_async, sda_i)
		]

		scl_i = Signal()
		samp_count = Signal(6)
		samp_carry = Signal()
		self.sync += [
			Cat(samp_count, samp_carry).eq(samp_count + 1),
			If(samp_carry, scl_i.eq(scl_raw))
		]

		scl_r = Signal()
		sda_r = Signal()
		scl_rising = Signal()
		sda_rising = Signal()
		sda_falling = Signal()
		self.sync += [
			scl_r.eq(scl_i),
			sda_r.eq(sda_i)
		]
		self.comb += [
			scl_rising.eq(scl_i & ~scl_r),
			sda_rising.eq(sda_i & ~sda_r),
			sda_falling.eq(~sda_i & sda_r)
		]

		start = Signal()
		self.comb += start.eq(scl_i & sda_falling)

		din = Signal(8)
		counter = Signal(max=9)
		self.sync += [
			If(start, counter.eq(0)),
			If(scl_rising,
				If(counter == 8,
					counter.eq(0)
				).Else(
					counter.eq(counter + 1),
					din.eq(Cat(sda_i, din[:7]))
				)
			)
		]

		is_read = Signal()
		update_is_read = Signal()
		self.sync += If(update_is_read, is_read.eq(din[0]))

		offset_counter = Signal(max=128)
		oc_load = Signal()
		oc_inc = Signal()
		self.sync += [
			If(oc_load,
				offset_counter.eq(din)
			).Elif(oc_inc,
				offset_counter.eq(offset_counter + 1)
			)
		]
		rdport = self.mem.get_port()
		self.comb += rdport.adr.eq(offset_counter)
		data_bit = Signal()

		zero_drv = Signal()
		data_drv = Signal()
		self.comb += If(zero_drv, sda_drv.eq(1)).Elif(data_drv, sda_drv.eq(~data_bit))

		data_drv_en = Signal()
		data_drv_stop = Signal()
		self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
		self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))

		states = ["WAIT_START",
			"RCV_ADDRESS", "ACK_ADDRESS0", "ACK_ADDRESS1", "ACK_ADDRESS2",
			"RCV_OFFSET", "ACK_OFFSET0", "ACK_OFFSET1", "ACK_OFFSET2",
			"READ", "ACK_READ"]
		fsm = FSM(*states)
		self.submodules += fsm
	
		fsm.act(fsm.RCV_ADDRESS,
			If(counter == 8,
				If(din[1:] == 0x50,
					update_is_read.eq(1),
					fsm.next_state(fsm.ACK_ADDRESS0)
				).Else(
					fsm.next_state(fsm.WAIT_START)
				)
			)
#.........这里部分代码省略.........

from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.genlib.fsm import FSM

s = Signal()
myfsm = FSM("FOO", "BAR")
myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO))
print(verilog.convert(myfsm.get_fragment(), {s}))

	def __init__(self, dw_i, dw_o):
		self.wishbone_i = Interface(dw_i)
		self.wishbone_o = Interface(dw_o)
		self.ratio = dw_i//dw_o

		###
		
		rst = Signal()

		# generate internal write and read ack
		write_ack = Signal()
		read_ack = Signal()
		ack = Signal()
		self.comb += [
			ack.eq(self.wishbone_o.cyc & self.wishbone_o.stb & self.wishbone_o.ack),
			write_ack.eq(ack & self.wishbone_o.we),
			read_ack.eq(ack & ~self.wishbone_o.we)
		]
		
		# accesses counter logic
		cnt = Signal(max=self.ratio)
		self.sync += If(rst, cnt.eq(0)).Elif(ack, cnt.eq(cnt + 1))
		
		# read data path
		dat_r = Signal(dw_i)
		self.sync += If(ack, dat_r.eq(Cat(self.wishbone_o.dat_r, dat_r[:dw_i-dw_o])))
		
		# write data path
		dat_w = Signal(dw_i)
		self.comb += dat_w.eq(self.wishbone_i.dat_w)
		
		# errors generation
		err = Signal()
		self.sync += If(ack, err.eq(self.wishbone_o.err))
		
		# direct connection of wishbone_i --> wishbone_o signals
		for name, size, direction in self.wishbone_i.layout:
			if direction == DIR_M_TO_S and name not in ["adr", "dat_w"]:
				self.comb += getattr(self.wishbone_o, name).eq(getattr(self.wishbone_i, name))
		
		# adaptation of adr & dat signals
		self.comb += [
			self.wishbone_o.adr[0:flen(cnt)].eq(cnt),
			self.wishbone_o.adr[flen(cnt):].eq(self.wishbone_i.adr)
		]
		
		self.comb += chooser(dat_w, cnt, self.wishbone_o.dat_w, reverse=True)
		
		# fsm
		fsm = FSM(reset_state="IDLE")
		self.submodules += fsm
		
		fsm.act("IDLE",
			If(write_ack, NextState("WRITE_ADAPT")),
			If(read_ack, NextState("READ_ADAPT"))
		)
		
		fsm.act("WRITE_ADAPT",
			If(write_ack & (cnt == self.ratio-1),
				NextState("IDLE"),
				rst.eq(1),
				self.wishbone_i.err.eq(err | self.wishbone_o.err),
				self.wishbone_i.ack.eq(1),
			)
		)
		
		master_i_dat_r = Signal(dw_i)
		self.comb += master_i_dat_r.eq(Cat(self.wishbone_o.dat_r, dat_r[:dw_i-dw_o]))

		fsm.act("READ_ADAPT",
			If(read_ack & (cnt == self.ratio-1),
				NextState("IDLE"),
				rst.eq(1),
				self.wishbone_i.err.eq(err | self.wishbone_o.err),
				self.wishbone_i.ack.eq(1),
				self.wishbone_i.dat_r.eq(master_i_dat_r)
			)
		)

    def __init__(self, a, ba, tRP, tREFI, tRFC):
        self.req = Signal()
        self.ack = Signal()  # 1st command 1 cycle after assertion of ack
        self.cmd = CommandRequest(a, ba)

        ###

        # Refresh sequence generator:
        # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
        seq_start = Signal()
        seq_done = Signal()
        self.sync += [
            self.cmd.a.eq(2**10),
            self.cmd.ba.eq(0),
            self.cmd.cas_n.eq(1),
            self.cmd.ras_n.eq(1),
            self.cmd.we_n.eq(1),
            seq_done.eq(0)
        ]
        self.sync += timeline(seq_start, [
            (1, [
                self.cmd.ras_n.eq(0),
                self.cmd.we_n.eq(0)
            ]),
            (1+tRP, [
                self.cmd.cas_n.eq(0),
                self.cmd.ras_n.eq(0)
            ]),
            (1+tRP+tRFC, [
                seq_done.eq(1)
            ])
        ])

        # Periodic refresh counter
        counter = Signal(max=tREFI)
        start = Signal()
        self.sync += [
            start.eq(0),
            If(counter == 0,
                start.eq(1),
                counter.eq(tREFI - 1)
            ).Else(
                counter.eq(counter - 1)
            )
        ]

        # Control FSM
        fsm = FSM()
        self.submodules += fsm
        fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
        fsm.act("WAIT_GRANT",
            self.req.eq(1),
            If(self.ack,
                seq_start.eq(1),
                NextState("WAIT_SEQ")
            )
        )
        fsm.act("WAIT_SEQ",
            self.req.eq(1),
            If(seq_done, NextState("IDLE"))
        )

	def __init__(self, ulpi_reg):
		
		ReadAddress = Signal(6)
		
		write_fsm = FSM()
		self.submodules += write_fsm
		
		def delay_clocks(v, d):
			for i in range(d):
				n = Signal()
				self.sync += n.eq(v)
				v = n
			return v
		
		ulpi_reg_wack = delay_clocks(ulpi_reg.wack, 2)
		ulpi_reg_rack = delay_clocks(ulpi_reg.rack, 2)
		
		write_fsm.delayed_enter("RESET", "WRITE_HS_SNOOP", 16)

		write_fsm.act("WRITE_HS_SNOOP",
			ulpi_reg.waddr.eq(0x4),
			ulpi_reg.wdata.eq(0x48),
			ulpi_reg.wreq.eq(1),
			If(ulpi_reg_wack, NextState("WRITE_IDLE")))
		
		write_fsm.act("WRITE_IDLE",
			ulpi_reg.wreq.eq(0))
		
		read_fsm = FSM()
		self.submodules += read_fsm

		read_fsm.delayed_enter("RESET", "READ_REG", 16)
		
		read_fsm.act("READ_REG",
			ulpi_reg.raddr.eq(ReadAddress),
			ulpi_reg.rreq.eq(1),
			If(ulpi_reg_rack, NextState("READ_ACK")))
		
		self.sync += If(ulpi_reg_rack & ulpi_reg.rreq, ReadAddress.eq(ReadAddress + 1))
		
		read_fsm.act("READ_ACK",
			ulpi_reg.rreq.eq(0),
			If(~ulpi_reg_rack, NextState("READ_WAIT")))
		
		read_fsm.delayed_enter("READ_WAIT", "READ_REG", 16)

    def __init__(self, sink_description, source_description, header):
        self.sink = sink = Sink(sink_description)
        self.source = source = Source(source_description)
        self.header = Signal(header.length*8)

        # # #

        dw = flen(self.sink.data)

        header_reg = Signal(header.length*8)
        header_words = (header.length*8)//dw
        load = Signal()
        shift = Signal()
        counter = Counter(max=max(header_words, 2))
        self.submodules += counter

        self.comb += header.encode(sink, self.header)
        if header_words == 1:
            self.sync += [
                If(load,
                    header_reg.eq(self.header)
                )
            ]
        else:
            self.sync += [
                If(load,
                    header_reg.eq(self.header)
                ).Elif(shift,
                    header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
                )
            ]

        fsm = FSM(reset_state="IDLE")
        self.submodules += fsm

        if header_words == 1:
            idle_next_state = "COPY"
        else:
            idle_next_state = "SEND_HEADER"

        fsm.act("IDLE",
            sink.ack.eq(1),
            counter.reset.eq(1),
            If(sink.stb & sink.sop,
                sink.ack.eq(0),
                source.stb.eq(1),
                source.sop.eq(1),
                source.eop.eq(0),
                source.data.eq(self.header[:dw]),
                If(source.stb & source.ack,
                    load.eq(1),
                    NextState(idle_next_state)
                )
            )
        )
        if header_words != 1:
            fsm.act("SEND_HEADER",
                source.stb.eq(1),
                source.sop.eq(0),
                source.eop.eq(0),
                source.data.eq(header_reg[dw:2*dw]),
                If(source.stb & source.ack,
                    shift.eq(1),
                    counter.ce.eq(1),
                    If(counter.value == header_words-2,
                        NextState("COPY")
                    )
                )
            )
        fsm.act("COPY",
            source.stb.eq(sink.stb),
            source.sop.eq(0),
            source.eop.eq(sink.eop),
            source.data.eq(sink.data),
            source.error.eq(sink.error),
            If(source.stb & source.ack,
                sink.ack.eq(1),
                If(source.eop,
                    NextState("IDLE")
                )
            )
        )

    def __init__(self, lasmim, nslots):
        bus_aw = lasmim.aw
        bus_dw = lasmim.dw
        alignment_bits = bits_for(bus_dw//8) - 1

        # debug
        print("LASMI Bus Address Width : {}".format(bus_aw))
        print("LASMI Bus Data Width    : {}".format(bus_dw))
        
        fifo_word_width = bus_dw
        self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
        self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
        self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
        self.ev = self._slot_array.ev

        ###

        # address generator + maximum memory word count to prevent DMA buffer overrun
        reset_words = Signal()
        count_word = Signal()
        last_word = Signal()
        current_address = Signal(bus_aw)
        mwords_remaining = Signal(bus_aw)
        self.comb += [
            self._slot_array.address_reached.eq(current_address),
            last_word.eq(mwords_remaining == 1)
        ]
        self.sync += [
            If(reset_words,
                current_address.eq(self._slot_array.address),
                mwords_remaining.eq(self._frame_size.storage) #Initially there was no division by 4
            ).Elif(count_word,
                current_address.eq(current_address + 1),
                mwords_remaining.eq(mwords_remaining - 1)
            )
        ]

        memory_word = Signal(bus_dw)
        pixbits = []
        for i in range(bus_dw//16): #was initially 16
            pixbits.append(self.frame.pixels)
        self.comb += memory_word.eq(Cat(*pixbits))

        # bus accessor
        self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
        self.comb += [
            self._bus_accessor.address_data.a.eq(current_address),
            self._bus_accessor.address_data.d.eq(memory_word)
        ]

        # control FSM
        fsm = FSM()
        self.submodules += fsm

        fsm.act("WAIT_SOF",
            reset_words.eq(1),
            self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.sof),
            If(self._slot_array.address_valid & self.frame.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
        )
        fsm.act("TRANSFER_PIXELS",
            self.frame.ack.eq(self._bus_accessor.address_data.ack),
            If(self.frame.stb,
                self._bus_accessor.address_data.stb.eq(1),
                If(self._bus_accessor.address_data.ack,
                    count_word.eq(1),
                    If(last_word, NextState("EOF"))
                )
            )
        )
        fsm.act("EOF",
            If(~self._bus_accessor.busy,
                self._slot_array.address_done.eq(1),
                NextState("WAIT_SOF")
            )
        )