def export_one(config, filename='top.v'):

    m = UnCore(config)

    verilog.convert(m,
                    name="top",
                    ios={m.start, m.done, m.cycle_count}
                    ).write(filename)

def export(config, filename='top.v'):

    m = UnCore(config)
    m.clock_domains.cd_sys = ClockDomain(reset_less=True)

    verilog.convert(m,
                    name="top",
                    ios={m.start, m.done, m.cycle_count, m.total_num_messages, m.cd_sys.clk}
                    ).write(filename)

def test_instance_module():
    sub = ChildModule()
    convert(sub, sub.io, name="ChildModule").write("ChildModule.v")

    im = ParentModule()
    convert(im, im.io, name="ParentModule").write("ParentModule.v")

    subprocess.check_call(["iverilog", "-W", "all",
                           "ParentModule.v", "ChildModule.v"])

def export(config, filename='top.v'):

    m = UnCore(config)
    m.clock_domains.cd_sys = ClockDomain(reset_less=True)

    ios = {m.start, m.done, m.cycle_count, m.total_num_messages, m.cd_sys.clk, m.kernel_error}
    if config.use_ddr:
        ios |= m.cores[0].portsharer.get_ios()

    verilog.convert(m,
                    name="top",
                    ios=ios
                    ).write(filename)

    with open("address_mapping.txt", 'w') as adrmap:
        word_offset = m.cores[0].bramio.word_offset
        addr_spacing = m.cores[0].bramio.addr_spacing
        start_addr = m.cores[0].config.start_addr
        if config.init_nodedata:
            for pe_id, data in enumerate(config.init_nodedata):
                fname = "init_nodedata{}.data".format(pe_id)
                with open(fname, 'wb') as f:
                    adrmap.write("{}\t{}\n".format(hex(start_addr), fname))
                    for x in data:
                        for _ in range(512//32):
                            f.write(struct.pack('=I', x & (2**32 - 1)))
                            x >>= 32
                start_addr += addr_spacing
        else:
            start_addr += config.addresslayout.num_pe * addr_spacing
        for pe_id, adj_idx in enumerate(config.adj_idx):
            fname = "adj_idx{}.data".format(pe_id)
            with open(fname, 'wb') as f:
                adrmap.write("{}\t{}\n".format(hex(start_addr), fname))
                for index, length in adj_idx:
                    data = convert_record_to_int([("index", config.addresslayout.edgeidsize), ("length", config.addresslayout.edgeidsize)], index=index, length=length)
                    print(hex(index), hex(length), hex(data))
                    for _ in range(512//32):
                        print(hex(data & (2**32 - 1)))
                        f.write(struct.pack('=I', data & (2**32 - 1)))
                        data = data >> 32
            start_addr += addr_spacing
        if config.use_ddr:
            with open("adj_val.data", 'wb') as f:
                adrmap.write("0x000000000\tadj_val.data\n")
                for x in config.adj_val:
                    f.write(struct.pack('=I', x))
        else:
            fname = "adj_val{}.data".format(pe_id)
            with open(fname, 'wb') as f:
                adrmap.write("{}\t{}\n".format(hex(start_addr), fname))
                for x in data:
                    f.write(struct.pack('=I', x))
            start_addr += addr_spacing

def main():
    pico = PicoPlatform(1, bus_width=32, stream_width=128)

    m = Top(pico)

    so = dict(migen.build.xilinx.common.xilinx_special_overrides)
    verilog.convert(m,
                    name="echo",
                    ios=pico.get_ios(),
                    special_overrides=so,
                    create_clock_domains=False
                    ).write("top.v")

def export(filename='echo.v'):

    platform = PicoPlatform(bus_width=32, stream_width=128)

    m = Top(platform)

    so = dict(migen.build.xilinx.common.xilinx_special_overrides)
    verilog.convert(m,
                    name="echo",
                    ios=platform.get_ios(),
                    special_overrides=so,
                    create_clock_domains=False
                    ).write(filename)

def export(config, filename='top.v'):
    config.platform = PicoPlatform(0 if config.memtype == "BRAM" else config.addresslayout.num_pe_per_fpga, create_hmc_ios=True, bus_width=32, stream_width=128)

    m = Top(config)

    so = dict(migen.build.xilinx.common.xilinx_special_overrides)
    verilog.convert(m,
                    name="top",
                    ios=config.platform.get_ios(),
                    special_overrides=so,
                    create_clock_domains=False
                    ).write(filename)
    if config.memtype != "BRAM":
        export_data(config.adj_val, "adj_val.data", backup=config.alt_adj_val_data_name)

def export(config, filename='top'):

    m = [Core(config, i*config.addresslayout.num_pe_per_fpga, min((i+1)*config.addresslayout.num_pe_per_fpga, config.addresslayout.num_pe)) for i in range(config.addresslayout.num_fpga)]

    for i in range(config.addresslayout.num_fpga):
        iname = filename + "_" + str(i)
        os.makedirs(iname, exist_ok=True)
        with cd(iname):
            ios={m[i].start, m[i].done, m[i].cycle_count}
            ios |= m[i].network.ios
            verilog.convert(m[i],
                            name="top",
                            ios=ios
                            ).write(iname + ".v")

def create_bench(ports):
    radix = clog2(ports)
    width = radix * 2
    print("Generating butterfly with radix == {}".format(radix))
    bf = sdlib.sd_butterfly(radix=radix, width=width)
    convert(bf, bf.io, name="butterfly{}".format(ports), asic_syntax=True).write("butterfly{}.v".format(ports))
    senders = sender(width=width, targets=ports)
    convert(senders, senders.io, name="sender{}".format(ports), asic_syntax=True).write("sender{}.v".format(ports))
    rcvr = receiver(width=width, sources=ports)
    convert(rcvr, rcvr.io, name="receiver{}".format(ports), asic_syntax=True).write("receiver{}.v".format(ports))
    se = harness(ports=ports, width=width)
    convert(se, se.io, name="harness{}".format(ports), asic_syntax=True).write("harness{}.v".format(ports))
    tb = harness_tb(ports=ports)
    convert(tb, name="harness_tb{}".format(ports)).write("harness_tb{}.v".format(ports))

def export_one(config, filename='top'):
    logger = logging.getLogger('config')
    config.platform = PicoPlatform(0 if config.memtype == "BRAM" else config.addresslayout.num_pe_per_fpga, create_hmc_ios=True, bus_width=32, stream_width=128)

    m = Top(config)
    logger.info("Exporting design to file {}".format(filename + '.v'))

    so = dict(migen.build.xilinx.common.xilinx_special_overrides)
    verilog.convert(m,
                    name=filename,
                    ios=config.platform.get_ios(),
                    special_overrides=so,
                    create_clock_domains=False
                    ).write(filename + '.v')
    if not config.memtype == "BRAM":
        export_data(config.adj_val, "adj_val.data")

def main():
	m = RiffAverage(c_pci_data_width=128)
	m.cd_sys.clk.name_override="clk"
	m.cd_sys.rst.name_override="rst"
	for name in "ack", "last", "len", "off", "data", "data_valid", "data_ren":
		getattr(m.chnl_rx, name).name_override="chnl_rx_{}".format(name)
		getattr(m.chnl_tx, name).name_override="chnl_tx_{}".format(name)
	m.chnl_rx.start.name_override="chnl_rx"
	m.chnl_tx.start.name_override="chnl_tx"

	print(verilog.convert(m, name="top", ios={
		m.chnl_rx_clk,
		m.chnl_rx.start,
		m.chnl_rx.ack,
		m.chnl_rx.last,
		m.chnl_rx.len,
		m.chnl_rx.off,
		m.chnl_rx.data,
		m.chnl_rx.data_valid,
		m.chnl_rx.data_ren,
		m.chnl_tx_clk,
		m.chnl_tx.start,
		m.chnl_tx.ack,
		m.chnl_tx.last,
		m.chnl_tx.len,
		m.chnl_tx.off,
		m.chnl_tx.data,
		m.chnl_tx.data_valid,
		m.chnl_tx.data_ren,
		m.cd_sys.clk,
		m.cd_sys.rst}))

	def get_verilog(self, fragment, **kwargs):
		if not isinstance(fragment, Fragment):
			fragment = fragment.get_fragment()
		# We may create a temporary clock/reset generator that would request pins.
		# Save the constraint manager state so that such pin requests disappear
		# at the end of this function.
		backup = self.constraint_manager.save()
		try:
			# if none exists, create a default clock domain and drive it
			if not fragment.clock_domains:
				if self.default_crg_factory is None:
					raise NotImplementedError("No clock/reset generator defined by either platform or user")
				crg = self.default_crg_factory(self)
				frag = fragment + crg.get_fragment()
			else:
				frag = fragment
			# generate Verilog
			src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
				return_ns=True, create_clock_domains=False, **kwargs)
			# resolve signal names in constraints
			sc = self.constraint_manager.get_sig_constraints()
			named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
			# resolve signal names in platform commands
			pc = self.constraint_manager.get_platform_commands()
			named_pc = []
			for template, args in pc:
				name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
				named_pc.append(template.format(**name_dict))
		finally:
			self.constraint_manager.restore(backup)
		return src, named_sc, named_pc

	def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
		if not isinstance(fragment, Fragment):
			fragment = fragment.get_fragment()
		if top_level is None:
			top_level = TopLevel()
		if sim_runner is None:
			sim_runner = icarus.Runner()		
		self.fragment = fragment + Fragment(clock_domains=top_level.clock_domains)
		self.top_level = top_level
		self.ipc = Initiator(sockaddr)
		self.sim_runner = sim_runner
		
		c_top = self.top_level.get(sockaddr)
		
		c_fragment, self.namespace = verilog.convert(self.fragment,
			ios=self.top_level.ios,
			name=self.top_level.dut_type,
			return_ns=True,
			**vopts)
		
		self.cycle_counter = -1
		self.interrupt = False

		self.sim_runner = sim_runner
		self.sim_runner.start(c_top, c_fragment)
		self.ipc.accept()
		reply = self.ipc.recv()
		assert(isinstance(reply, MessageTick))
		_call_sim(self.fragment, self)

def main():
	# Compute filter coefficients with SciPy.
	coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
	fir = FIR(coef)
	
	# Simulate for different frequencies and concatenate
	# the results.
	in_signals = []
	out_signals = []
	for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
		tb = TB(fir, frequency)
		fragment = autofragment.from_local()
		sim = Simulator(fragment, Runner())
		sim.run(100)
		in_signals += tb.inputs
		out_signals += tb.outputs
	
	# Plot data from the input and output waveforms.
	plt.plot(in_signals)
	plt.plot(out_signals)
	plt.show()
	
	# Print the Verilog source for the filter.
	print(verilog.convert(fir.get_fragment(),
		ios={fir.i, fir.o}))

def main():
	c_pci_data_width = 128 # PCIe lane width
	ptrsize = 64 # pointer size of the host system, 32 bit or 64 bit
	wordsize = 32 # width of data port to design (any power of 2)
	
	num_chnls = 4 # Virtmem takes 2 channels, add more for direct use, plus last one for loopback "are you there?" test
	combined_interface_tx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls)
	combined_interface_rx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls)

	m = DesignTemplate(combined_interface_rx=combined_interface_rx, combined_interface_tx=combined_interface_tx, c_pci_data_width=c_pci_data_width, wordsize=wordsize, ptrsize=ptrsize)

	# add a loopback to test responsiveness
	test_rx, test_tx = m.get_channel(num_chnls - 1)
	m.comb += test_rx.connect(test_tx)

	m.cd_sys.clk.name_override="clk"
	m.cd_sys.rst.name_override="rst"
	for name in "ack", "last", "len", "off", "data", "data_valid", "data_ren":
		getattr(combined_interface_rx, name).name_override="chnl_rx_{}".format(name)
		getattr(combined_interface_tx, name).name_override="chnl_tx_{}".format(name)
	combined_interface_rx.start.name_override="chnl_rx"
	combined_interface_tx.start.name_override="chnl_tx"
	m.rx_clk.name_override="chnl_rx_clk"
	m.tx_clk.name_override="chnl_tx_clk"
	print(verilog.convert(m, name="top", ios={getattr(combined_interface_rx, name) for name in ["start", "ack", "last", "len", "off", "data", "data_valid", "data_ren"]} | {getattr(combined_interface_tx, name) for name in ["start", "ack", "last", "len", "off", "data", "data_valid", "data_ren"]} | {m.rx_clk, m.tx_clk, m.cd_sys.clk, m.cd_sys.rst} ))

def get():
	MHz = 1000000
	clk_freq = 80*MHz
	sram_size = 4096 # in kilobytes
	
	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
	reset0 = m1reset.M1Reset()
	
	cpu0 = lm32.LM32()
	norflash0 = norflash.NorFlash(25, 12)
	sram0 = sram.SRAM(sram_size//4)
	wishbone2csr0 = wishbone2csr.WB2CSR()
	wishbonecon0 = wishbone.InterconnectShared(
		[cpu0.ibus, cpu0.dbus],
		[(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
		register=True,
		offset=1)
	uart0 = uart.UART(0, clk_freq, baud=115200)
	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
	
	frag = autofragment.from_local()
	src_verilog, vns = verilog.convert(frag,
		{clkfx_sys.clkin, reset0.trigger_reset},
		name="soc",
		clk_signal=clkfx_sys.clkout,
		rst_signal=reset0.sys_rst,
		return_ns=True)
	src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
	return (src_verilog, src_ucf)

	def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
		if not isinstance(fragment, _Fragment):
			fragment = fragment.get_fragment()
		if top_level is None:
			top_level = TopLevel()
		if sim_runner is None:
			sim_runner = icarus.Runner()
		self.top_level = top_level
		self.ipc = Initiator(sockaddr)
		self.sim_runner = sim_runner
		
		c_top = self.top_level.get(sockaddr)
		
		fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
		c_fragment, self.namespace = verilog.convert(fragment,
			ios=self.top_level.ios,
			name=self.top_level.dut_type,
			return_ns=True,
			**vopts)
		
		self.cycle_counter = -1

		self.sim_runner = sim_runner
		self.sim_runner.start(c_top, c_fragment)
		self.ipc.accept()
		reply = self.ipc.recv()
		assert(isinstance(reply, MessageTick))

		self.sim_functions = fragment.sim
		self.active_sim_functions = set(f for f in fragment.sim if not hasattr(f, "passive") or not f.passive)

	def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts):
		self.fragment = fragment
		if top_level is None:
			self.top_level = TopLevel()
		else:
			self.top_level = top_level
		self.ipc = Initiator(sockaddr)
		
		c_top = self.top_level.get(sockaddr)
		
		clk_signal = Signal(name_override=self.top_level.clk_name)
		rst_signal = Signal(name_override=self.top_level.rst_name)
		c_fragment, self.namespace = verilog.convert(fragment,
			{clk_signal, rst_signal},
			name=self.top_level.dut_type,
			clk_signal=clk_signal,
			rst_signal=rst_signal,
			return_ns=True,
			**vopts)
		
		self.cycle_counter = -1
		self.interrupt = False

		self.sim_runner = sim_runner
		self.sim_runner.start(c_top, c_fragment)
		self.ipc.accept()
		reply = self.ipc.recv()
		assert(isinstance(reply, MessageTick))
		self.fragment.call_sim(self)

def export(config, filename='top'):
    logger = logging.getLogger('config')
    config.platform = [PicoPlatform(0 if config.memtype == "BRAM" else config.addresslayout.num_pe_per_fpga, create_hmc_ios=True, bus_width=32, stream_width=128) for _ in range(config.addresslayout.num_fpga)]

    m = [Top(config, i) for i in range(config.addresslayout.num_fpga)]

    logger.info("Exporting design to files {0}[0-{1}]/{0}.v".format(filename, config.addresslayout.num_fpga - 1))

    for i in range(config.addresslayout.num_fpga):
        iname = filename + "_" + str(i)
        os.makedirs(iname, exist_ok=True)
        with cd(iname):
            verilog.convert(m[i],
                            name=filename,
                            ios=config.platform[i].get_ios()
                            ).write(filename + ".v")
    if config.memtype != "BRAM":
        export_data(config.adj_val, "adj_val.data", data_size=config.addresslayout.adj_val_entry_size_in_bytes*8, backup=config.alt_adj_val_data_name)

def _test_accu():
    dut = PhasedAccu(8, parallelism=8)

    if False:
        print(convert(dut))
    else:
        o = []
        run_simulation(dut, _test_gen_accu(dut, o), vcd_name="accu.vcd")
        o = np.array(o)
        print(o)