def __init__(self, nchan=3, depth=8):
        self.valid_i = Signal()
        self.chan_synced = Signal()

        self._r_channels_synced = CSRStatus()

        lst_control = []
        all_control = Signal()
        for i in range(nchan):
            name = "data_in" + str(i)
            data_in = Record(channel_layout, name=name)
            setattr(self, name, data_in)
            name = "data_out" + str(i)
            data_out = Record(channel_layout, name=name)
            setattr(self, name, data_out)

            ###

            syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
            self.submodules += syncbuffer
            self.comb += [syncbuffer.din.eq(data_in.raw_bits()), data_out.raw_bits().eq(syncbuffer.dout)]
            is_control = Signal()
            self.comb += [is_control.eq(~data_out.de), syncbuffer.re.eq(~is_control | all_control)]
            lst_control.append(is_control)

        some_control = Signal()
        self.comb += [all_control.eq(optree("&", lst_control)), some_control.eq(optree("|", lst_control))]
        self.sync.pix += If(~self.valid_i, self.chan_synced.eq(0)).Else(
            If(some_control, If(all_control, self.chan_synced.eq(1)).Else(self.chan_synced.eq(0)))
        )
        self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)

    def __init__(self, master, slaves, register=False):
        ns = len(slaves)
        slave_sel = Signal(ns)
        slave_sel_r = Signal(ns)

        # decode slave addresses
        self.comb += [slave_sel[i].eq(fun(master.adr))
            for i, (fun, bus) in enumerate(slaves)]
        if register:
            self.sync += slave_sel_r.eq(slave_sel)
        else:
            self.comb += slave_sel_r.eq(slave_sel)

        # connect master->slaves signals except cyc
        for slave in slaves:
            for name, size, direction in _layout:
                if direction == DIR_M_TO_S and name != "cyc":
                    self.comb += getattr(slave[1], name).eq(getattr(master, name))

        # combine cyc with slave selection signals
        self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
            for i, slave in enumerate(slaves)]

        # generate master ack (resp. err) by ORing all slave acks (resp. errs)
        self.comb += [
            master.ack.eq(optree("|", [slave[1].ack for slave in slaves])),
            master.err.eq(optree("|", [slave[1].err for slave in slaves]))
        ]

        # mux (1-hot) slave data return
        masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
        self.comb += master.dat_r.eq(optree("|", masked))

	def complete_selector(self, slicer, bankn, slots):
		rr = self.rr

		# List outstanding requests for our bank
		outstandings = []
		for slot in slots:
			outstanding = Signal()
			self.comb += outstanding.eq(
				(slicer.bank(slot.adr) == bankn) & \
				(slot.state == SLOT_PENDING))
			outstandings.append(outstanding)
		
		# Row tracking
		openrow_r = Signal(slicer.geom_settings.row_a)
		openrow_n = Signal(slicer.geom_settings.row_a)
		openrow = Signal(slicer.geom_settings.row_a)
		self.comb += [
			openrow_n.eq(slicer.row(self.adr)),
			If(self.stb,
				openrow.eq(openrow_n)
			).Else(
				openrow.eq(openrow_r)
			)
		]
		self.sync += If(self.stb & self.ack, openrow_r.eq(openrow_n))
		hits = []
		for slot, os in zip(slots, outstandings):
			hit = Signal()
			self.comb += hit.eq((slicer.row(slot.adr) == openrow) & os)
			hits.append(hit)
		
		# Determine best request
		rr = RoundRobin(self.nslots, SP_CE)
		has_hit = Signal()
		self.comb += has_hit.eq(optree("|", hits))
		
		best_hit = [rr.request[i].eq(hit)
			for i, hit in enumerate(hits)]
		best_fallback = [rr.request[i].eq(os)
			for i, os in enumerate(outstandings)]
		select_stmt = If(has_hit,
				*best_hit
			).Else(
				*best_fallback
			)
		
		if slots[0].time:
			# Implement anti-starvation timer
			matures = []
			for slot, os in zip(slots, outstandings):
				mature = Signal()
				comb.append(mature.eq(slot.mature & os))
				matures.append(mature)
			has_mature = Signal()
			self.comb += has_mature.eq(optree("|", matures))
			best_mature = [rr.request[i].eq(mature)
				for i, mature in enumerate(matures)]
			select_stmt = If(has_mature, *best_mature).Else(select_stmt)
		self.comb += select_stmt

    def __init__(self, period_bits=24):
        self.data = Signal(10)
        self._update = CSR()
        self._value = CSRStatus(period_bits)

        ###
        # (pipeline stage 1)
	# We ignore the 10th (inversion) bit, as it is independent of the
	# transition minimization.
        data_r = Signal(9)
        self.sync.pix += data_r.eq(self.data[:9])

        # (pipeline stage 2)
	# Count the number of transitions in the TMDS word.
        transitions = Signal(8)
        self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
        transition_count = Signal(max=9)
        self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))

	# Control data characters are designed to have a large number (7) of
	# transitions to help the receiver synchronize its clock with the
	# transmitter clock.
        is_control = Signal()
        self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))

        # (pipeline stage 3)
	# The TMDS characters selected to represent pixel data contain five or
	# fewer transitions.
        is_error = Signal()
        self.sync.pix += is_error.eq((transition_count > 4) & ~is_control)

        # counter
        period_counter = Signal(period_bits)
        period_done = Signal()
        self.sync.pix += Cat(period_counter, period_done).eq(period_counter + 1)

        wer_counter = Signal(period_bits)
        wer_counter_r = Signal(period_bits)
        wer_counter_r_updated = Signal()
        self.sync.pix += [
            wer_counter_r_updated.eq(period_done),
            If(period_done,
                wer_counter_r.eq(wer_counter),
                wer_counter.eq(0)
            ).Elif(is_error,
                wer_counter.eq(wer_counter + 1)
            )
        ]

        # sync to system clock domain
        wer_counter_sys = Signal(period_bits)
        self.submodules.ps_counter = PulseSynchronizer("pix", "sys")
        self.comb += self.ps_counter.i.eq(wer_counter_r_updated)
        self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))

        # register interface
        self.sync += If(self._update.re, self._value.status.eq(wer_counter_sys))

	def do_finalize(self):
		self.tag_call = Signal(self.tagbits)
		for port in self.ports:
			self.comb += [
				port.call.eq(self.call),
				port.tag_call.eq(self.tag_call),
				port.dat_r.eq(self.dat_r)
			]
		self.comb += [
			self.dat_w.eq(optree("|", [port.dat_w for port in self.ports])),
			self.dat_wm.eq(optree("|", [port.dat_wm for port in self.ports]))
		]

	def get_fragment(self):
		if not self.finalized:
			raise FinalizeError
		
		slots_fragment = sum([s.get_fragment() for s in self.slots], Fragment())
		
		comb = []
		sync = []
		
		# allocate
		for s in self.slots:
			comb += [
				s.allocate_we.eq(self.we),
				s.allocate_adr.eq(self.adr)
			]
		choose_slot = None
		needs_tags = len(self.slots) > 1
		for n, s in reversed(list(enumerate(self.slots))):
			choose_slot = If(s.state == SLOT_EMPTY,
				s.allocate.eq(self.stb),
				self.tag_issue.eq(n) if needs_tags else None
			).Else(choose_slot)
		comb.append(choose_slot)
		comb.append(self.ack.eq(optree("|", 
			[s.state == SLOT_EMPTY for s in self.slots])))
		
		# call
		comb += [s.call.eq(self.get_call_expression(n))
			for n, s in enumerate(self.slots)]
		
		return slots_fragment + Fragment(comb, sync)

	def __init__(self, dfg):
		dfg.elaborate()

		# expose unconnected endpoints
		uc_eps_by_node = dict((node, get_endpoints(node)) for node in dfg)
		for u, v, d in dfg.edges_iter(data=True):
			uc_eps_u = uc_eps_by_node[u]
			source = d["source"]
			try:
				del uc_eps_u[source]
			except KeyError:
				pass
			uc_eps_v = uc_eps_by_node[v]
			sink = d["sink"]
			try:
				del uc_eps_v[sink]
			except KeyError:
				pass
		for node, uc_eps in uc_eps_by_node.items():
			for k, v in uc_eps.items():
				assert(not hasattr(self, k))
				setattr(self, k, v)

		# generate busy signal
		self.busy = Signal()
		self.comb += self.busy.eq(optree("|", [node.busy for node in dfg]))

		# claim ownership of sub-actors and establish connections
		for node in dfg:
			self.submodules += node
		for u, v, d in dfg.edges_iter(data=True):
			ep_src = getattr(u, d["source"])
			ep_dst = getattr(v, d["sink"])
			self.comb += ep_src.connect_flat(ep_dst)

	def get_fragment(self):
		source = self.endpoints["source"]
		sinks = [self.endpoints["sink{0}".format(n)]
			for n in range(len(self.endpoints)-1)]
		comb = [source.stb.eq(optree("&", [sink.stb for sink in sinks]))]
		comb += [sink.ack.eq(source.ack & source.stb) for sink in sinks]
		return Fragment(comb)

	def __init__(self):
		a = [Foo() for x in range(3)]
		
		output = Signal()
		allsigs = []
		for obj in a:
			allsigs.extend(obj.la)
			allsigs.extend(obj.lb)
		self.comb += output.eq(optree("|", allsigs))

def simple_interconnect_stmts(desc, master, slaves):
	s2m = desc.get_names(S_TO_M)
	m2s = desc.get_names(M_TO_S)
	sl = [getattr(slave, name).eq(getattr(master, name))
		for name in m2s for slave in slaves]
	sl += [getattr(master, name).eq(
			optree("|", [getattr(slave, name) for slave in slaves])
		)
		for name in s2m]
	return sl

	def __init__(self, base_port, nshares):
		self.shared_ports = [SharedPort(base_port) for i in range(nshares)]

		###

		# request issuance
		self.submodules.rr = roundrobin.RoundRobin(nshares, roundrobin.SP_CE)
		self.comb += [
			self.rr.request.eq(Cat(*[sp.stb for sp in self.shared_ports])),
			self.rr.ce.eq(base_port.ack)
		]
		self.comb += [
			base_port.adr.eq(Array(sp.adr for sp in self.shared_ports)[self.rr.grant]),
			base_port.we.eq(Array(sp.we for sp in self.shared_ports)[self.rr.grant]),
			base_port.stb.eq(Array(sp.stb for sp in self.shared_ports)[self.rr.grant]),
		]
		if hasattr(base_port, "tag_issue"):
			self.comb += [sp.tag_issue.eq(base_port.tag_issue) for sp in self.shared_ports]
		self.comb += [sp.ack.eq(base_port.ack & (self.rr.grant == n)) for n, sp in enumerate(self.shared_ports)]

		# request completion
		self.comb += [sp.call.eq(base_port.call & Array(sp.slots)[base_port.tag_call-base_port.base])
			for sp in self.shared_ports]
		self.comb += [sp.tag_call.eq(base_port.tag_call) for sp in self.shared_ports]
		self.comb += [sp.dat_r.eq(base_port.dat_r) for sp in self.shared_ports]
		self.comb += [
			base_port.dat_w.eq(optree("|", [sp.dat_w for sp in self.shared_ports])),
			base_port.dat_wm.eq(optree("|", [sp.dat_wm for sp in self.shared_ports])),
		]
		
		# request ownership tracking
		if hasattr(base_port, "tag_issue"):
			for sp in self.shared_ports:
				self.sync += If(sp.stb & sp.ack, Array(sp.slots)[sp.tag_issue].eq(1))
				for n, slot in enumerate(sp.slots):
					self.sync += If(base_port.call & (base_port.tag_call == (base_port.base + n)), slot.eq(0))
		else:
			for sp in self.shared_ports:
				self.sync += [
					If(sp.stb & sp.ack, sp.slots[0].eq(1)),
					If(base_port.call & (base_port.tag_call == base_port.base), sp.slots[0].eq(0))
				]

	def __init__(self, charge, sense, width=24):
		if not isinstance(sense, collections.Iterable):
			sense = [sense]

		channels = len(sense)

		self._start_busy = CSR()
		self._overflow = CSRStatus(channels)
		self._polarity = CSRStorage()

		count = Signal(width)
		busy = Signal(channels)

		res = []
		for i in range(channels):
			res.append(CSRStatus(width, name="res"+str(i)))
			setattr(self, "_res"+str(i), res[-1])

		any_busy = Signal()
		self.comb += [
			any_busy.eq(optree("|",
			    [busy[i] for i in range(channels)])),
			self._start_busy.w.eq(any_busy)
		]

		carry = Signal()

		self.sync += [
			If(self._start_busy.re,
				count.eq(0),
				busy.eq((1 << channels)-1),
				self._overflow.status.eq(0),
				charge.eq(~self._polarity.storage)
			).Elif(any_busy,
				Cat(count, carry).eq(count + 1),
				If(carry,
					self._overflow.status.eq(busy),
					busy.eq(0)
				)
			).Else(
				charge.eq(self._polarity.storage)
			)
		]

		for i in range(channels):
			sense_synced = Signal()
			self.specials += MultiReg(sense[i], sense_synced)
			self.sync += If(busy[i],
				If(sense_synced != self._polarity.storage,
					res[i].status.eq(count),
					busy[i].eq(0)
				)
			)

	def __init__(self):
		a = [Bar() for x in range(3)]
		b = [Foo() for x in range(3)]
		c = b
		b = [Bar() for x in range(2)]

		output = Signal()
		allsigs = []
		for lst in [a, b, c]:
			for obj in lst:
				allsigs.extend(obj.sigs)
		self.comb += output.eq(optree("|", allsigs))

	def get_fragment(self):
		comb = [self.busy.eq(optree("|", [node.busy for node in self.dfg]))]
		fragment = Fragment(comb)
		for node in self.dfg:
			fragment += node.get_fragment()
		for u, v, d in self.dfg.edges_iter(data=True):
			ep_src = u.endpoints[d["source"]]
			ep_dst = v.endpoints[d["sink"]]
			fragment += get_conn_fragment(ep_src, ep_dst)
		if hasattr(self, "debugger"):
			fragment += self.debugger.get_fragment()
		return fragment

	def build_binary_control(self, stb_i, ack_o, stb_o, ack_i, latency):
		valid = Signal(latency)
		if latency > 1:
			self.sync += If(self.pipe_ce, valid.eq(Cat(stb_i, valid[:latency-1])))
		else:
			self.sync += If(self.pipe_ce, valid.eq(stb_i))
		last_valid = valid[latency-1]
		self.comb += [
			self.pipe_ce.eq(ack_i | ~last_valid),
			ack_o.eq(self.pipe_ce),
			stb_o.eq(last_valid),
			self.busy.eq(optree("|", [valid[i] for i in range(latency)]))
		]

    def __init__(self, n_out, n_state=31, taps=[27, 30]):
        self.o = Signal(n_out)

        ###

        state = Signal(n_state)
        curval = [state[i] for i in range(n_state)]
        curval += [0] * (n_out - n_state)
        for i in range(n_out):
            nv = ~optree("^", [curval[tap] for tap in taps])
            curval.insert(0, nv)
            curval.pop()

        self.sync += [state.eq(Cat(*curval[:n_state])), self.o.eq(Cat(*curval))]

	def get_fragment(self):
		muls = []
		sync = []
		src = self.i
		for c in self.coef:
			sreg = Signal((self.wsize, True))
			sync.append(sreg.eq(src))
			src = sreg
			c_fp = int(c*2**(self.wsize - 1))
			muls.append(c_fp*sreg)
		sum_full = Signal((2*self.wsize-1, True))
		sync.append(sum_full.eq(optree("+", muls)))
		comb = [self.o.eq(sum_full[self.wsize-1:])]
		return Fragment(comb, sync)

    def __init__(self, layout, subrecords):
        self.source = Source(layout)
        sinks = []
        for n, r in enumerate(subrecords):
            s = Sink(layout_partial(layout, *r))
            setattr(self, "sink" + str(n), s)
            sinks.append(s)
        self.busy = Signal()

        ###

        self.comb += [self.busy.eq(0), self.source.stb.eq(optree("&", [sink.stb for sink in sinks]))]
        self.comb += [sink.ack.eq(self.source.ack & self.source.stb) for sink in sinks]
        self.comb += [self.source.payload.eq(sink.payload) for sink in sinks]

	def get_fragment(self):
		comb = []
		sync = []
		
		ns = len(self.slaves)
		slave_sel = Signal(ns)
		slave_sel_r = Signal(ns)
		
		# decode slave addresses
		comb += [slave_sel[i].eq(fun(self.master.adr))
			for i, (fun, bus) in enumerate(self.slaves)]
		if self.register:
			sync.append(slave_sel_r.eq(slave_sel))
		else:
			comb.append(slave_sel_r.eq(slave_sel))
		
		# connect master->slaves signals except cyc
		m2s_names = _desc.get_names(M_TO_S, "cyc")
		comb += [getattr(slave[1], name).eq(getattr(self.master, name))
			for name in m2s_names for slave in self.slaves]
		
		# combine cyc with slave selection signals
		comb += [slave[1].cyc.eq(self.master.cyc & slave_sel[i])
			for i, slave in enumerate(self.slaves)]
		
		# generate master ack (resp. err) by ORing all slave acks (resp. errs)
		comb += [
			self.master.ack.eq(optree("|", [slave[1].ack for slave in self.slaves])),
			self.master.err.eq(optree("|", [slave[1].err for slave in self.slaves]))
		]
		
		# mux (1-hot) slave data return
		masked = [Replicate(slave_sel_r[i], len(self.master.dat_r)) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
		comb.append(self.master.dat_r.eq(optree("|", masked)))
		
		return Fragment(comb, sync)

	def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
		valid = Signal(self.latency)
		if self.latency > 1:
			sync = [If(self.pipe_ce, valid.eq(Cat(stb_i, valid[:self.latency-1])))]
		else:
			sync = [If(self.pipe_ce, valid.eq(stb_i))]
		last_valid = valid[self.latency-1]
		
		comb = [
			self.pipe_ce.eq(ack_i | ~last_valid),
			ack_o.eq(self.pipe_ce),
			stb_o.eq(last_valid),
			self.busy.eq(optree("|", [valid[i] for i in range(self.latency)]))
		]
		
		return Fragment(comb, sync)