def assign1():
     """assign quantizer core signals to buffer interface"""
     buffer_data.next = quant_output_stream_temp.data
     buffer_waddr.next = concat(not quanto_datastream.buffer_sel, write_cnt)
     buffer_we.next = quant_output_stream_temp.valid
     buffer_raddr.next = concat(quanto_datastream.buffer_sel,
                                quanto_datastream.addr)

 def rtl():
     b30_20.next = (
         instruction[31:20]
         if sel == Consts.IMM_U
         else concat(sign, sign, sign, sign, sign, sign, sign, sign, sign, sign, sign)
     )
     b19_12.next = (
         instruction[20:12]
         if (sel == Consts.IMM_U or sel == Consts.IMM_UJ)
         else concat(sign, sign, sign, sign, sign, sign, sign, sign)
     )
     b11.next = (
         False
         if (sel == Consts.IMM_U or sel == Consts.IMM_Z)
         else (instruction[20] if sel == Consts.IMM_UJ else (instruction[7] if sel == Consts.IMM_SB else sign))
     )
     b10_5.next = modbv(0)[6:] if (sel == Consts.IMM_U or sel == Consts.IMM_Z) else instruction[31:25]
     b4_1.next = (
         modbv(0)[4:]
         if sel == Consts.IMM_U
         else (
             instruction[12:8]
             if (sel == Consts.IMM_S or sel == Consts.IMM_SB)
             else (instruction[20:16] if sel == Consts.IMM_Z else instruction[25:21])
         )
     )
     b0.next = (
         instruction[7]
         if sel == Consts.IMM_S
         else (instruction[20] if sel == Consts.IMM_I else (instruction[15] if sel == Consts.IMM_Z else False))
     )

 def beh_state_machine():
     fifobus.write.next = False
     
     if state == states.start:
         # @todo: wait some amount of time
         if sclkneg:
             bitcnt.next = 0
             state.next = states.capture
             csn.next = False
             sregout.next[14:11] = channel
         
     elif state == states.capture:
         if sclkpos:
             bitcnt.next = bitcnt + 1 
             sregin.next = concat(sregin[15:0], din)
         elif sclkneg:
             sregout.next = concat(sregout[15:0], '0')
         
         if bitcnt == 16:
             state.next = states.start
             sample.next = sregin[12:]   # this can be removed
             if not fifobus.full:
                 fifobus.write_data.next = sregin
                 fifobus.write.next = True
             else:
                 print("FIFO full dropping sample")

    def continuous_assignment():

        digb_period.next = (not __ade) and (____ade or ade)

        decision1.next = (no_of_ones_video_in > 4) or \
                         (no_of_ones_video_in == 4 and not _video_in[0])
        decision2.next = (count == 0) | (no_of_zeros_q_m == no_of_ones_q_m)
        decision3.next = (not count[4]) & (no_of_ones_q_m > no_of_zeros_q_m) | \
                         (count[4]) & (no_of_ones_q_m < no_of_zeros_q_m)

        if is_blue:
            ade_vld.next = ade | __ade | ____ade
            if digb_period:
                audio_in_vld.next = concat(bool(1), bool(1), __c1, __c0)
            else:
                audio_in_vld.next = concat(__audio_in[3], __audio_in[2], __c1, __c0)

        else:
            ade_vld.next = __ade
            audio_in_vld.next = __audio_in

        q_m.next[0] = _video_in[0]
        temp = _video_in[0]
        if decision1:
            for i in range(1, 8):
                temp = temp ^ (not _video_in[i])
                q_m.next[i] = 1 if temp else 0
            q_m.next[8] = 0
        else:
            for i in range(1, 8):
                temp = temp ^ _video_in[i]
                q_m.next[i] = 1 if temp else 0
            q_m.next[8] = 1

 def comb_logic():
     a_upper.next = a[A_MAX : A_MAX - MULTMAX].signed()
     a_lower.next = concat(False, a[A_MAX - MULTMAX :])
     b_upper.next = b[A_MAX : A_MAX - MULTMAX].signed()
     b_lower.next = concat(False, b[A_MAX - MULTMAX :])
     n_pipe.next = bufout
     p.next = pipe_buf

    def output_logic():
        if __vde:
            if decision2:
                data_out.next[9] = not _q_m[8]
                data_out.next[8] = _q_m[8]
                if _q_m[8]:
                    data_out.next[8:0] = _q_m[8:0]
                    count.next = count + no_of_ones_q_m - no_of_zeros_q_m
                else:
                    data_out.next[8:0] = ~_q_m[8:0]
                    count.next = count + no_of_zeros_q_m - no_of_ones_q_m
            elif decision3:
                data_out.next[9] = True
                data_out.next[8] = _q_m[8]
                data_out.next[8:0] = ~_q_m[8:0]
                count.next = count - concat(_q_m[8], bool(0)) + no_of_zeros_q_m - no_of_ones_q_m
            else:
                data_out.next[9] = False
                data_out.next[8] = _q_m[8]
                data_out.next[8:0] = _q_m[8:0]
                count.next = count - concat(not _q_m[8], bool(0)) + no_of_ones_q_m - no_of_zeros_q_m
        else:
            if vde:
                data_out.next = video_guard_band
            elif ade_vld:
                data_out.next = terc4_encoding[audio_in_vld]
            elif (ade or ____ade) and (not is_blue):
                data_out.next = data_island_guard_band
            else:
                concat_c = concat(__c1, __c0)
                data_out.next = control_token[concat_c]

            count.next = 0

 def assignments_0():
     sign_a.next = io.input1[31] if (io.cmd[0] or io.cmd[2]) else modbv(0)[1:]
     sign_b.next = io.input2[31] if io.cmd[0] else modbv(0)[1:]
     partial_sum.next = concat(modbv(0)[15:], result_mid_1) + concat(result_hh_1[32:], result_ll_1[32:16])
     io.output.next = -result_mult if sign_result3 else result_mult
     io.ready.next = active3
     io.active.next = active0 | active1 | active2 | active3

 def state_machine():
     if state == s_idle:
         if req_valid:
             result.next = 0
             a.next = abs_in_1
             b.next = concat(abs_in_2, modbv(0)[XPR_LEN:]) >> 1
             if op == MD_OP_REM:
                 negate_output.next = sign_in_1
             else:
                 negate_output.next = sign_in_1 ^ sign_in_2
             out_sel.next = req_out_sel
             op.next = req_op
             counter.next = XPR_LEN - 1
     elif state == s_compute:
         counter.next = counter + 1
         b.next = b >> 1
         if op == MD_OP_MUL:
             if a[counter]:
                 result.next = result + b
         else:
             b.next = b + 1
             if a_geq:
                 a.next = a - b
                 result.next = modbv(1 << counter)[DOUBLE_XPR_LEN:] | result
     elif state == s_setup_output:
         result.next = concat(modbv(0)[XPR_LEN:], final_result)

    def write_process1():
        
        if state_m == bp_states_m.WRITE1:
            
            index_r                           = random[26:20]
                        
            #btb_line[index_r][64:63].next     = Signal(True)  #Set Valid Bit
            #btb_line[index_r][61:32].next     = tag_pc[32:2]  #Store tag
            
 
            if BPio.valid_jump:
                btb_line[index_r].next        = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.ST)[2:])
                # btb_line[index_r][63:62].next = Signal(True)              #Set Unconditional Bit
                # btb_line[index_r][2:0].next   = Consts.ST                 #As a jump it'll always be ST
                # BPio.current_state.next       = Consts.ST                 #Send our current state to Cpath
                # btb_line[index_r][32:2].next  = BPio.pc_id_brjmp[32:2]    #Store jump address in BTB

            elif BPio.valid_branch:
                btb_line[index_r].next        = concat(True,False,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.WN)[2:])
                #btb_line[index_r][63:62].next = Signal(False)           #Clear unconditional bit
                #btb_line[index_r][2:0].next   = Consts.WN               #It will be initialized in WN
                #BPio.current_state.next       = Consts.WN               #Send our current state to Cpath
                #btb_line[index_r][32:2].next  = BPio.pc_id_brjmp[32:2]  #Store Branch address in BTB
        
            else:   #Corresponding to JALR
                #btb_line[index_r][63:62]      = Signal(True)            #Set Unconditional bit
                #btb_line[index_r][2:0]        = Consts.ST               #As an indirect jump it'll always be taken
                #BPio.current_state.next       = Consts.ST               #Send our current state to Cpath
                #btb_line[index_r][32:2]       = BPio.pc_id_jalr[32:2]   #Store jump address in BTB  
                btb_line[index_r].next        = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_jalr[32:2])[30:],modbv(Consts.ST)[2:])

            

            final_write1.next      = True

 def tx(self, decim=1):
     re = [intbv(i)[10:] for i in self.tx_i][::decim]
     re = [intbv(concat(not i[len(i)-1], i[len(i)-1:])).signed() for i in re]
     im = [intbv(q)[10:] for q in self.tx_q][::decim]
     im = [intbv(concat(not q[len(q)-1], q[len(q)-1:])).signed() for q in im]
     y = np.array([i + 1j * q for i, q in zip(re, im)])
     return y

    def gain_correct():
        if in_valid:
            mul_valid.next = in_valid
            mul_last.next = in_last

            #print 'i', ia.signed()/2.**9, '*', ix.signed() / float(ix.max), '=', ia.signed()/2**9 * (ix.signed() / float(ix.max))

            mul_i.next = in_i.signed() * concat(bool(0), gain_i).signed()
            mul_q.next = in_q.signed() * concat(bool(0), gain_q).signed()
        else:
            mul_valid.next = False
            mul_last.next = False
            mul_i.next = 0
            mul_q.next = 0

        if mul_valid:
            out_valid.next = mul_valid
            out_last.next = mul_last
            #print 'm', mul_q[len(mul_q)-2] ^ mul_q[len(mul_q)-3]
            out_i.next = mul_i[len(mul_i)-2:len(mul_i)-len(out_i)-2].signed()
            out_q.next = mul_q[len(mul_q)-2:len(mul_q)-len(out_q)-2].signed()
        else:
            out_valid.next = False
            out_last.next = False
            out_i.next = 0
            out_q.next = 0

 def accessor():
     if state == state_t.READY:
         coeff_ram_blk.next = True
         if enable and in_valid:
             delay_line_i_ram_addr.next = concat(bank1, bank0, n)
             delay_line_i_ram_din.next = in_i
             delay_line_i_ram_blk.next = False
             delay_line_i_ram_wen.next = False
             delay_line_q_ram_addr.next = concat(bank1, bank0, n)
             delay_line_q_ram_din.next = in_q
             delay_line_q_ram_blk.next = False
             delay_line_q_ram_wen.next = False
         else:
             delay_line_i_ram_blk.next = True
             delay_line_q_ram_blk.next = True
             
     elif state == state_t.WAIT1 or state == state_t.WAIT2 or state == state_t.RUN:
         delay_line_i_ram_addr.next = concat(bank1, bank0, modbv(n - k, min=0, max=2**7-1))
         delay_line_i_ram_blk.next = False
         delay_line_i_ram_wen.next = True
         delay_line_q_ram_addr.next = concat(bank1, bank0,
                 modbv(n - k, min=0, max=2**7-1))
         delay_line_q_ram_blk.next = False
         delay_line_q_ram_wen.next = True
         coeff_ram_addr.next = concat(bank1, bank0, k)
         coeff_ram_blk.next = False
         coeff_ram_wen.next = True
     else:
         delay_line_i_ram_blk.next = True
         delay_line_q_ram_blk.next = True
         coeff_ram_blk.next = True

    def beh_shifts():
        # extra registers on the serial inputs and outputs
        irei.next = sdi
        oreo.next = lastoreg[nby-1]
        sdo.next = oreo

        # build the large shift register out of the logical
        # list of signals (array)
        for ii in range(nin):
            tmp1 = ireg[ii]
            if ii == 0:
                ireg[ii].next = concat(tmp1[nbx-1:0], irei)
            else:
                tmp0 = ireg[ii-1]
                ireg[ii].next = concat(tmp1[nbx-1:0], tmp0[nbx-1])

        if scnt == imax:
            valid.next = True
            scnt.next = 0
            for oo in range(nout):
                oreg[oo].next = pout[oo]
        else:
            valid.next = False
            scnt.next = scnt + 1
            for oo in range(nout):
                tmp1 = oreg[oo]
                if oo == 0:
                    oreg[oo].next = concat(tmp1[nby-1:0],  tmp1[nby-1])
                else:
                    tmp0 = oreg[oo-1]
                    oreg[oo].next = concat(tmp1[nby-1:0], tmp0[nby-1])

        def continuous_assignment():

            digb_period.next = (not __ade) and (____ade or self.ade)

            decision1.next = (no_of_ones_video_in > 4) or \
                             (no_of_ones_video_in == 4 and not _video_in[0])
            decision2.next = (count == 0) | (no_of_zeros_q_m == no_of_ones_q_m)
            decision3.next = (not count[4]) & (no_of_ones_q_m > no_of_zeros_q_m) | \
                             (count[4]) & (no_of_ones_q_m < no_of_zeros_q_m)

            if self.channel == "BLUE":

                ade_vld.next = self.ade | __ade | ____ade
                if digb_period:
                    audio_in_vld.next = concat(bool(1), bool(1), __c1, __c0)
                else:
                    audio_in_vld.next = concat(__audio_in[3], __audio_in[2], __c1, __c0)

            else:

                ade_vld.next = __ade
                audio_in_vld.next = __audio_in

            q_m.next[0] = _video_in[0]
            temp = _video_in[0]
            for i in range(1, self.color_depth):
                temp = (temp ^ (not _video_in[i] if decision1 else _video_in[i]))
                q_m.next[i] = 1 if temp else 0
            q_m.next[self.color_depth] = 0 if decision1 else 1

 def audio_shift_reg():
     if ce_bit:
         if seq[1]:
             sr.next = concat(parity1, inreg1)
         elif seq[33]:
             sr.next = concat(parity2, inreg2)
         elif out_ch1 or out_ch2:
             sr.next = concat(False, sr[28:1])

    def store_data(data, mem_type):

        if mem_type == MEM_TYPE_SB:
            return concat(data[8:0], data[8:0], data[8:0], data[8:0])
        elif mem_type == MEM_TYPE_SH:
            return concat(data[16:0], data[16:0])
        else:
            return data

 def frombytes(self, bytes):
     self.clear()
     self.access.next = bytes[0][0]
     self.write.next = bytes[0][1]
     self.datamode.next = bytes[0][4:2]
     self.ctrlmode.next = bytes[0][8:4]
     self.dstaddr.next = concat(*reversed(bytes[1:5]))
     self.data.next = concat(*reversed(bytes[5:9]))
     self.srcaddr.next = concat(*reversed(bytes[9:13]))

        def stimulus():
            N = Signal(intbv(0)[32:])

            yield bus.reset()
            # Send a clear
            yield whitebox_clear(bus)

            # Check the fifo flags
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_SPACE
            assert not (bus.rdata & WES_DATA)

            yield bus.transmit(WE_THRESHOLD_ADDR,
                concat(intbv(1)[16:], intbv(3)[16:]))
            yield bus.receive(WE_THRESHOLD_ADDR)
            assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])

            yield bus.transmit(WE_INTERP_ADDR, INTERP)
            yield bus.receive(WE_INTERP_ADDR)
            assert bus.rdata == INTERP

            ## Insert samples until overrun
            yield bus.receive(WE_RUNS_ADDR)
            while not (bus.rdata & 0x0000ffff):
                x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15), min=-2**15, max=2**15)[16:]
                yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
                N.next = N + 1
                yield bus.receive(WE_RUNS_ADDR)

            # Check that we're full
            yield bus.receive(WE_STATUS_ADDR)
            assert not (bus.rdata & WES_SPACE)
            assert bus.rdata & WES_DATA

            ## Now start transmitting
            yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_TXEN

            ## Wait until underrun
            yield bus.receive(WE_RUNS_ADDR)
            while not (bus.rdata & 0xffff0000):
                yield bus.delay(1000)
                yield bus.receive(WE_RUNS_ADDR)

            ## Make sure we're both over and underrun
            assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff

            # Check the fifo flags
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_SPACE
            assert not (bus.rdata & WES_DATA)

            raise StopSimulation

 def binary_offset():
     if in_valid:
         out_valid.next = True
         out_last.next = in_last
         out_i.next = intbv(concat(not in_i[len(in_i) - 1], in_i[len(in_i) - 1:]), min=0, max=2**len(in_i))
         out_q.next = intbv(concat(not in_q[len(in_q) - 1], in_q[len(in_q) - 1:]), min=0, max=2**len(in_q))
     else:
         out_valid.next = False
         out_last.next = False
         out_i.next = 0
         out_q.next = 0

def random_read(n):
    """ Generate and return a random intbv suitable for a read operation

    n -- length of the expected value in number of bytes

    """
    data = intbv(randrange(0xFF))[8:] # key
    data[7] = 0 # read
    data = concat(data, intbv(n)[8:]) # length
    for j in range(n):
        data = concat(data, intbv(0)[8:]) # placeholder bytes for value
    return data