def WriteAddress(self, addr, data):
        wbuf = [0xDE, 0xCA, 0x01, 0x00, 0x00, 0x01, 0xFB, 0xAD, 0x00]
        rbuf = [0 for ii in range(9)]

        wbuf[3] = (addr >> 8) & 0xFF
        wbuf[4] = addr & 0xFF
        wbuf[5] = 1
        wbuf[8] = data

        self.Write(wbuf, self.EP2)
        while not self.IsEmpty(self.EP2):
            yield delay(2 * self.IFCLK_TICK)
        while not self.IsData(self.EP6, 9):
            yield delay(2 * self.IFCLK_TICK)

        for i in range(9):
            rbuf[i] = self.Read(self.EP6)

        # The last byte is the previous value of the register, it will not match
        for i in range(8):
            if wbuf[i] != rbuf[i]:
                print("wbuf ", wbuf)
                print("rbuf ", rbuf)
            assert wbuf[i] == rbuf[i], "Write Address Failed wbuf[%d](%02x) != rbuf[%d](%02x)" % (
                i,
                wbuf[i],
                i,
                rbuf[i],
            )

    def stimulus():
        for s in script:
            print s
            yield delay(10)
            if (we):
                we.next = False
                wclk.next = False
            elif (re):
                print Q, s
                assert Q == s[1]
                print 'all good in the hood'
                re.next = False
                rclk.next = False

            yield delay(10)

            if s[0] == 'w':
                we.next = True
                wclk.next = True
                data.next = s[1]
            elif s[0] == 'r':
                re.next = True
                rclk.next = True
            elif s[0] == 'x':
                pass

    def stimulus():
        for i in range(5):
            if random.random() > 0.25:
                clk.next = 1
            if random.random() > 0.75:
                rst.next = 1

            pc_adder_in.next, data1_in.next, data2_in.next, address32_in.next = [intbv(random.randint(-255, 255)) for i in range(4)]

            rs_in.next, rd_in.next, rt_in.next, func_in.next = [intbv(random.randint(0, 15)) for i in range(4)]

            RegDst_in.next, ALUop_in.next, ALUSrc_in.next = [random.randint(0, 1) for i in range(3)]
            Branch_in.next, MemRead_in.next, MemWrite_in.next = [random.randint(0, 1) for i in range(3)]
            RegWrite_in.next, MemtoReg_in.next = [random.randint(0, 1) for i in range(2)]

            yield delay(1)
            print "-" * 79
            print "%i %i %i | %i %i %i | %i | %i  %i  %i  %i  %i  %i  %i  %i " % (data1_in, data2_in, address32_in,
                                                                                  rs_in, rt_in, rd_in, func_in,
                                                                                  RegDst_in, ALUop_in, ALUSrc_in,
                                                                                  Branch_in, MemRead_in, MemWrite_in,
                                                                                  RegWrite_in, MemtoReg_in)
            print "clk: %i  rst: %i " % (clk, rst)

            print "%i %i %i | %i %i %i | %i | %i  %i  %i  %i  %i  %i  %i  %i " % (data1_out, data2_out, address32_out,
                                                                                  rs_out, rt_out, rd_out, func_out, RegDst_out, ALUop_out, ALUSrc_out,
                                                                                  Branch_out, MemRead_out, MemWrite_out,
                                                                                  RegWrite_out, MemtoReg_out)

            clk.next = 0
            rst.next = 0
            yield delay(1)

 def test(out, a):
     yield delay(10)
     self.assertEqual(Signal(None), a)
     self.assertEqual(Signal(None), out)
     a.next = True
     yield delay(10)
     self.assertEqual(Signal(False), out)

        def tbstim():
            yield delay(1000)
            
            # send a write that should enable all five LEDs
            pkt = CommandPacket(False, address=0x20, vals=[0xFF])
            for bb in pkt.rawbytes:
                uartmdl.write(bb)
            waitticks = int((1/115200.) / 1e-9) * 10 * 28
            yield delay(waitticks) 
            timeout = 100
            yield delay(waitticks) 
            # get the response packet
            for ii in range(PACKET_LENGTH):
                rb = uartmdl.read()
                while rb is None and timeout > 0:
                    yield clock.posedge
                    rb = uartmdl.read()
                    timeout -= 1
                if rb is None:
                    raise TimeoutError

            # the last byte should be the byte written
            assert rb == 0xFF

            yield delay(1000)
            raise StopSimulation

    def inst():
        yield delay(300 * nsec)

        while 1:
            yield delay(interval - 1)
            yield bus.CLK_I.posedge

            bus.CYC_I.next = 1
            bus.STB_I.next = 1
            bus.WE_I.next = 0

            while 1:
                yield bus.CLK_I.posedge
                if bus.ACK_O or bus.ERR_O:
                    break

            if bus.ACK_O:
                print "ACK", hex(bus.ADR_I), hex(bus.DAT_O & ((1<<(len(bus.DAT_O)-1))-1))

            if bus.ERR_O:
                print "ERR", hex(bus.ADR_I)

            bus.CYC_I.next = 0
            bus.STB_I.next = 0

            bus.ADR_I.next = 0
            if bus.ADR_I != n - 1:
                bus.ADR_I.next = bus.ADR_I + 1

 def stimulus():
     print('out\tin')
     for k in range(16):
         in_.next = k       
         yield delay(10)                 
         print(out, in_, sep='\t')                      
         yield delay(10)              

 def test(out, c0, c1, d0, d1, d2, d3):
     yield delay(10)
     for i in range(2):
         d0.next = i
         for j in range(2):
             d1.next = j
             for k in range(2):
                 d2.next = k
                 for l in range(2):
                     d3.next = l
             
                     c0.next = 0
                     c1.next = 0
                     yield delay(10)
                     print "here?", c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d0, out)
                     
                     c1.next = 1
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d1, out)
                     
                     c0.next = 1
                     c1.next = 0
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d2, out)
                     
                     c0.next = 1
                     c1.next = 1
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d3, out)

 def monitor():
     yield self.rx_ready.posedge, delay(500000)
     yield delay(1)
     print(now())
     self.assertEquals(self.rx_msg, 0x0FFFFFFFFFFF)
     self.assertTrue(self.rx_ready)
     self.stop_simulation()

 def tbstim():
   yield delay(10)
   print("{0:<8d} ".format(now()))
   yield delay(1000)
   print("{0:<8d} ".format(now()))
   for _ in range(10):
     yield delay(1000)

 def driveClk():
     clk.next = 0
     while True:
         yield delay(lowTime)
         clk.next = 1
         yield delay(highTime)
         clk.next = 0

 def clock_driver():
     for i in range(NUM_NIBBLES):
         pclk.next = 0
         yield delay(period / 2)
         pclk.next = 1
         yield delay(period / 2)
     pclk.next = 0    # 80

        def test():

            self.rx_ready.next = False
            self.tx_ready.next = False
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = True
            yield delay(10)
            self.assertFalse(self.nop)
            self.assertTrue(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = False
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = True
            yield delay(10)
            self.assertFalse(self.nop)
            self.assertTrue(self.rx_next)

            self.rx_ready.next = False
            self.tx_ready.next = True
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.stop_simulation()

        def tbstim():
            try:
                yield delay(100)
                yield reset.pulse(110)
                yield clock.posedge
                
                for k, reg in regdef.items():
                    if reg.access == 'ro':
                        yield regbus.readtrans(reg.addr)
                        rval = regbus.get_read_data()
                        assert rval == reg.default, \
                            "ro: {:02x} != {:02x}".format(rval, reg.default)
                    else:
                        wval = randint(0, (2**reg.width)-1)
                        yield regbus.writetrans(reg.addr, wval)
                        for _ in range(4):
                            yield clock.posedge
                        yield regbus.readtrans(reg.addr)
                        rval = regbus.get_read_data()
                        assert rval == wval, \
                            "rw: {:02x} != {:02x} @ {:04X}".format(
                                rval, wval, reg.addr)
                yield delay(100)
            except AssertionError as err:
                print("@E: %s".format(err))
                traceback.print_exc()
                asserr.next = True
                for _ in range(10):
                    yield clock.posedge
                raise err

            raise StopSimulation

def rs232_rx(rx, data, duration=T_9600, timeout=MAX_TIMEOUT):
    
    """ Simple rs232 receiver procedure.

    rx -- serial input data
    data -- data received
    duration -- receive bit duration
    
    """

    # wait on start bit until timeout
    yield rx.negedge, delay(timeout)
    if rx == 1:
        raise StopSimulation, "RX time out error"

    # sample in the middle of the bit duration
    yield delay(duration // 2)
    print "RX: start bit"

    for i in range(8):
        yield delay(duration)
        print "RX: %s" % rx
        data[i] = rx

    yield delay(duration)
    print "RX: stop bit"
    print "-- Received %s --" % hex(data)

    def tbstim():
        print("start simulation")
        fbus.write.next = False
        fbus.write_data.next = 0
        fbus.read.next = False
        fbus.clear.next = False

        print("reset")
        reset.next = reset.active
        yield delay(10)
        reset.next = not reset.active
        yield delay(10)

        print("some clock cycles")
        for ii in range(10):
            yield clock_write.posedge

        print("some writes")
        for ii in range(fifosize):
            fbus.write.next = True
            fbus.write_data.next = ii
            yield clock_write.posedge
        fbus.write.next = False
        yield clock_write.posedge

        for ii in range(fifosize):
            fbus.read.next = True
            yield clock_read.posedge
            print("%d %d %d %d" % (
                fbus.write, fbus.write_data, fbus.read, fbus.read_data,))
        fbus.read.next = False

        print("end simulation")
        raise StopSimulation

    def stimulus():

        #write
        for addr, val in zip(addresses, values):
            
            address.next = intbv( addr)[32:]
            data_in.next = intbv( val, min=-(2**31), max=2**31-1)
            
            write_control.next = 1
            clk.next = 0

            print "Write: addr %i = %d" % ( addr, val)
            yield delay(5)
            write_control.next = 0
            clk.next = 1
            yield delay(5)
        
        #read
        for addr in addresses:
            address.next = intbv( addr)[32:]
            read_control.next = 1
            clk.next = 0
            yield delay(5)
            print "Read: addr %i = %d" % (addr, data_out)
            clk.next = 1
            read_control.next = 0
            yield delay(5)

        def tbstim():
            yield delay(1111)
            yield clock.posedge

            # send a bunch of write packets
            print("send packets")
            save_data = []
            yield emesh.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
            save_data.append(0xDECAFBAD)
            for ii in range(10):
                addr = randint(0, 1024)
                data = randint(0, (2**32)-1)
                save_data.append(data)
                yield emesh.write(addr, data, ii)

            # the other device is a simple loopback, should receive
            # the same packets sent.
            while emesh.txwr_fifo.count > 0:
                print("  waiting ... {}".format(emesh))
                yield delay(8000)

            print("get packets looped back, ")
            while len(save_data) > 0:
                yield delay(8000)
                pkt = emesh.get_packet('wr')
                if pkt is not None:
                    assert pkt.data == save_data[0], \
                        "{} ... {:08X} != {:08X}".format(
                        pkt, int(pkt.data), save_data[0])
                    save_data.pop(0)

            for ii in range(27):
                yield clock.posedge

            raise StopSimulation

 def testlogic():
     reset.next = 0
     yield delay(15)
     reset.next = 1
     yield delay(20)
     print("Converted! %d" % now())
     raise StopSimulation

 def test(out, a, b):
     yield delay(10)
     for i in range(2):
         a.next = i
         yield delay(10)
         #print a, b, out
         self.assertEqual(Signal(None), out)