def stimulus():
        for op_value in [0, int('100011', 2), int('101011', 2), int('000100', 2)]:
            opcode.next = op_value
            yield delay(10)

            print 'opcode: ', bin(opcode, 6)
            print RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(ALUop, 2)

    def logic():
        if not aluop[0] and not aluop[1]:
            control_out.next = intbv('0010')

        elif aluop[0]:
            control_out.next = intbv('0110')

        elif aluop[1]:
           
            if bin(funct_field[3:], 4) == '0000':
                control_out.next = intbv('0010')
            
            elif bin(funct_field[3:], 4) == '0010':
                control_out.next = intbv('0110')
                
            elif bin(funct_field[3:], 4) == '0100':
                control_out.next = intbv('0000')
        
            elif bin(funct_field[3:], 4) == '0101':
                control_out.next = intbv('0001')
        
            elif bin(funct_field[3:], 4) == '1010':
                control_out.next = intbv('0111')

            else:
                control_out.next = intbv(0)

 def testRandomLong(self):
     for j in range(SIZE):
         k = randrange(sys.maxint)
         i = k + sys.maxint
         self.assertEqual(bin(i), binref(i))
         i = -k - sys.maxint
         self.assertEqual(bin(i), binref(i))

 def testRandomLong(self):
     for j in range(SIZE):
         k = randrange(sys.maxsize)
         i = k + sys.maxsize
         assert bin(i) == binref(i)
         i = -k - sys.maxsize
         assert bin(i) == binref(i)

 def stimulus():
     for i in range(8):
         value = random.randint(-(2**15), 2**15-1)
         data_in.next = intbv( value, min=-(2**15), max=2**15-1)
         
         print "In: %s (%i) | Out: %s (%i)" % (bin(data_in, 16), data_in, bin(data_out, 32), data_out)
         yield delay(5)

 def testRandomLongWith(self):
     for j in range(SIZE):
         w = randrange(1, 1000)
         k = randrange(sys.maxint)
         i = k + sys.maxint
         self.assertEqual(bin(i, w), binref(i, w))
         i = -k - sys.maxint
         self.assertEqual(bin(i, w), binref(i, w))

 def testRandomLongWith(self):
     for j in range(SIZE):
         w = randrange(1, 1000)
         k = randrange(sys.maxsize)
         i = k + sys.maxsize
         assert bin(i, w) == binref(i, w)
         i = -k - sys.maxsize
         assert bin(i, w) == binref(i, w)

        def stimulus():
            iA, iB, pA, pB = 0, 0, 1, 1
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                pipeA[iA].next = a
                pipeB[iB].next = b
                iA = (iA + 1) % ticks
                iB = (iB + 1) % ticks

                if (p != pipeA[pA] * pipeB[pB]):
                    f_a = float(a)
                    f_b = float(b)
                    f_p = float(p)
                    f_pipeA = float(pipeA[pA])
                    f_pipeB = float(pipeB[pB])
                    print("{:5.4f}x{:5.4f} = {:5.4f}".format(
                        f_a/float(MAX), f_b/float(MAX),
                        (f_pipeA * f_pipeB)/float(MAXOUT)) +
                        " but got {:5.4f}, error: {:5.4f}".format(
                            f_p/float(MAXOUT),
                            (f_pipeA * f_pipeB - f_p)/float(MAXOUT)))
                assert p == pipeA[iA] * pipeB[iB], \
                    "Difference: p - a * b = {}".format(
                        bin(p - pipeA[iA] * pipeB[pB], 2 * BITS))

                pA = (pA + 1) % ticks
                pB = (pB + 1) % ticks

    def stimulus():
        for control_val, func in [(int(b, 2), func) for (b, func) in control_func]:
            control_i.next = Signal(intbv(control_val))

            op1_i.next, op2_i.next = [intbv(random.randint(0, 255))[32:] for i in range(2)]

            yield delay(10)
            print "Control: %s | %i %s %i | %i | z=%i" % (bin(control_i, 4), op1_i, func, op2_i, out_i, zero_i)

 def test(B, G, width):
     B.next = intbv(0)
     yield delay(10)
     for i in range(1, 2**width):
         G_Z.next = G
         B.next = intbv(i)
         yield delay(10)
         diffcode = bin(G ^ G_Z)
         self.assertEqual(diffcode.count('1'), 1)

        def stimulus():
            for step in range(STEPS):
                print "STEP %02d:" % step,

                a.next = step
                b.next = step << 8

                if step % 2 == 0:
                    sel.next = not sel

                yield DELAY
                print "%d q %s a %s b %s" % (sel, bin(q, 16), bin(a, 16), bin(b, 16))
                if sel % 2 == 0:
                    assert q == a
                else:
                    assert q == b

            raise StopSimulation

    def stimulus():
        for i in range(4):
            aluop_i.next = intbv(i)

            for j in range(2**6):

                funct_field_i.next = intbv(j)

                yield delay(10)
                print "aluop: %s | funct field: %s | alu_control_lines: %s" % (bin(aluop_i, 2), bin(funct_field_i, 6 ), bin(alu_control_lines, 4)) 

        def debug_internals():
            sep = "\n" + "=" * 31 + " cycle %i (%ins)" + "=" * 31
            print sep % (int(now() / 2.0 + 0.5), now())
            #IF
            print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
            print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %x" % (PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip)
            print 'Instruction_if %s (%x)' % (bin(Instruction_if, 32), Instruction_if)

            if True:  # now () > 2:

                #ID
                print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
                print "Ip_id %i | Instruction_id %s (%x) | Nop %i" % (PcAdderOut_id, bin(Instruction_id, 32), Instruction_id, NopSignal)
                print 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
                    (bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id)

                print 'Data1 %i | Data2 %i' % (Data1_id, Data2_id)
                print '-->CONTROL'
                print 'RegDst %i  ALUop %s  ALUSrc %i | Branch %i Jump %i  MemR %i  MemW %i |  RegW %i Mem2Reg %i ' % \
                    (RegDst_id, ALUop_id, ALUSrc_id, Branch_id, Jump_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id)

                print 'Stall --> %i' % Stall

            if True:  # if now () > 4:

                #EX
                print "\n" + "." * 35 + " EX " + "." * 35 + "\n"

                print "Ip_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
                print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)

                print 'Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex)

                print 'ForwardA %i | ForwardB %i' % (ForwardA, ForwardB)
                print 'ForwMux1Out %i | ForwMux2Out %i' % (ForwMux1Out, ForwMux2Out)

                print '-->CONTROL'
                print 'RegDst %i  ALUop %s  ALUSrc %i | Branch %i  Jump %i, MemR %i  MemW %i |  RegW %i Mem2Reg %i ' % \
                    (RegDst_ex, ALUop_ex, ALUSrc_ex, Branch_ex, Jump_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex)

                print '--> ALU'
                print 'MuxAluDataSrc %i  | AluCtrl %s | AluResult_ex %i | Zero_ex %i' % (MuxAluDataSrc_ex, AluControl, AluResult_ex, Zero_ex)
                print 'WrRegDest_ex %i' % WrRegDest_ex

def get_arg(instruction, argument):
    """
    Utiity function to return commonly used slices/arguments
    of instructions in hexadecimal or binary formats
    
    :param Signal instruction: Input instruction 
    :param str argument_name: the name of the argument to be extracted
    """
    if argument == 'family_code':
        return instruction[7:2]
    elif argument == 'opcode':
        return instruction[7:]
    elif argument == 'funct3':
        return instruction[15:12]
    elif argument == 'funct7':
        return instruction[32:25]
    elif argument == 'rs1':
        return instruction[20:15]
    elif argument == 'rs2':
        return instruction[25:20]
    elif argument == 'imm12lo':
        return intbv(int(bin(instruction[31]) + bin(instruction[7]) + bin(instruction[31:27], width=4),2))
    elif argument == 'imm12hi':
        return intbv(int(bin(instruction[27:25],width=2) + bin(instruction[12:8],width=4) ,2))
    elif argument == 'instruction_id':
        return instruction[15:12]
    elif argument == 'rd':
        return instruction[12:7]
    elif argument == 'imm12':
        return instruction[32:20]
    elif argument == 'imm12_sb':
        return intbv(int(bin(instruction[32:25],width=7) + bin(instruction[12:7],width=5) ,2))
    elif argument == 'imm20':
        return intbv(int( bin(instruction[31]) + bin(instruction[20:12],width=8) + bin(instruction[20]) + bin(instruction[31:21], width=10) ,2))
    elif argument == 'imm20_pc':
        return instruction[31:12]
    elif argument == 'shamtw':
        return instruction[25:20]
    elif argument == 'shamt':
        return instruction[25:20]
    else:
        return None 

 def test(B, G):
     w = len(B)
     G_Z = Signal(intbv(0)[w:])
     B.next = intbv(0)
     yield delay(10)
     for i in range(1, 2**w):
         G_Z.next = G
         B.next = intbv(i)
         yield delay(10)
         diffcode = bin(G ^ G_Z)
         self.assertEqual(diffcode.count('1'), 1)

        def debug_internals():
            print "-" * 78
            print "time %s | clk %i | clk_pc %i | ip %i " % (now(), clk, clk_pc, ip)

            print 'pc_add_o %i | branch_add_o %i | BranchZ %i | next_ip %i' % (pc_adder_out, branch_adder_out, branchZ, next_ip)
            print 'instruction', bin(instruction, 32)

            print 'opcode %s | rs %i | rt %i | rd %i | shamt %i | func %i | address %i' % \
                (bin(opcode, 6), rs, rt, rd, shamt, func, address)

            print 'wr_reg_in %i | dat1 %i | dat2 %i | muxALUo %i ' % \
                  (wr_reg_in, data1, data2, mux_alu_out)

            print 'RegDst %i | ALUSrc %i | Mem2Reg %i | RegW %i | MemR %i | MemW %i | Branch %i | ALUop %s' % (RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(ALUop, 2))

            print 'func: %s | aluop: %s | alu_c_out: %s' % (bin(func, 5),
                                                            bin(ALUop, 2),
                                                            bin(alu_control_out, 4))

            print 'ALU_out: %i | Zero: %i' % (alu_out, zero)

            print 'ram_out %i | mux_ram_out %i ' % (ram_out, mux_ram_out)

 def _vcd_printval(self, value):
     if isinstance(value, myhdl.SignalType):
         thevalue = value.val
         if value._nrbits == 1:
             return str(int(thevalue))
     else:
         thevalue = value
     if isinstance(thevalue, myhdl.intbv):
         if thevalue._nrbits == 1:
             return str(int(thevalue))
         else:
             return "b%s " % myhdl.bin(thevalue)
     elif isinstance(thevalue, bool):
         return str(int(thevalue))
     elif isinstance(thevalue, (int, long)):
         return "b%s " % myhdl.bin(thevalue)
     elif isinstance(thevalue, float):
         return "r%.16g " % thevalue
     elif isinstance(thevalue, str):
         return "s%s " % thevalue
     else:
         # use repr as fallback
         return "s%s " % repr(thevalue)

            def transmit(char):

                yield baud_ticks(self.UART_RX_BAUD_DIV)
                self.rx.next = self.LVL_START
                yield baud_ticks(self.UART_RX_BAUD_DIV)

                indexes = range(8)[::-1]
                for i in indexes:
                    lvl = bin(char, width=8)[i] == '1'
                    self.rx.next = lvl
                    yield baud_ticks(self.UART_RX_BAUD_DIV)

                self.rx.next = self.LVL_STOP
                yield baud_ticks(self.UART_RX_BAUD_DIV)

def test_check_crc():
    x = myhdl.intbv(0, _nrbits=22 * 8)
    x[:] = 0xAAAAAAAAAAAAAAAAAAABCDEFAAAAAAAAAAAAAAAAAAAA  # 13548
    crc_poly = myhdl.intbv(0, _nrbits=9)
    crc_poly[8] = 1
    crc_poly[4] = 1
    crc_poly[3] = 1
    crc_poly[2] = 1
    crc_poly[0] = 1
    print(myhdl.bin(x, x._nrbits))
    print(myhdl.bin(crc_poly, crc_poly._nrbits))

    c, err = check_crc(x, crc_poly)

    print(myhdl.bin(c, c._nrbits))
    print(myhdl.bin(err, err._nrbits))

    d, derr = check_crc(x, crc_poly, err)

    print(myhdl.bin(d, d._nrbits))
    print(myhdl.bin(derr, derr._nrbits))

def test_create():
    """
    This test creates a bunch of different fixed-point objects.
    This test doesn't test correctness only test that creating and many
    of the public functions execute without error.
    """
    print("\n** Create W16.0 fxintbv")
    x = fixbv(0, min=-1, max=1, res=2**-15)
    print(x, hex(x), repr(x))

    print "\n** Create W9.3 fxintbv == 2.5"
    x = fixbv(2.5, min=-8, max=8, res=1./32)
    print(x, hex(x), repr(x))

    print("\n** Create W0.?? fxintbv == 0.0333")
    x = fixbv(0.0333, min=-1, max=1, res=0.0001)
    print(x, hex(x), repr(x))
    
    s = 0.5
    x = 0x4000
    for i in range(16):
        fxp = fixbv(s, min=-1, max=1, res=2**-15)
        s = s / 2
        print(str(fxp), myhdl.bin(fxp, 16), "%04x" % (fxp), type(fxp), repr(fxp))
        #print(hex(fxp & x)  @todo assert hex(fxp & x) == x, "Incorrect fixed-point calculation")
        x = x >> 1

    print("Get fixbv")
    a = fixbv(0, min=-2, max=2, res=2**-4)
    print("Assign to 1")
    a._val = 1
    print(a, repr(a))

    print("[1] Showing range: ")
    print("printing a:", a)
    print("slice operation (Note slice will return intbv)")
    print("  ", str(a), "  slice a[4:] ", hex(a[4:]), " a[16:] ", hex(a[16:]))

    a = fixbv(1.2, min=-2, max=2, res=2**-3)
    print("[2] Showing range: ")
    print("printing a: ", a)


    a = fixbv(0.02, min=-1, max=1, res=2**-8)
    print("[1] Representation a: ", repr(a))

    b = fixbv(0.2, min=-1, max=1, res=2**-8)
    print("[2] Representation b: ", repr(b))

    c = fixbv(0, format=a.W+b.W)
    print("[3] Representation c: ", c.W)

    print("[1] Add: c = a + b")
    c[:] = a + b
    print "c: ", c, type(c), repr(c)

    print("[2] Add: c = 1.25 + 2.0")
    a = fixbv(1.25, min=-4, max=4, res=2**-12)
    b = fixbv(2.0,  min=-4, max=4, res=2**-12)
    c = fixbv(0, format=a.W+b.W)
    print("  a: ", a.W, bin(a,len(a)), " b: ", b.W, bin(b,len(b)))
    c[:] = a + b
    print("c: ", c, c.W, bin(c,len(c)))