def sdram_sdr_controller(clock, reset, ibus, extram, refresh=True):
    """ SDRAM controller
    This module is an SDRAM controller to interface and control
    SDRAM modules.  This module contains a state-machine that 
    controls the different SDRAM modes including refresh etc.

    This module provides the translation from a flat memory-mapped
    bus (e.g. Wishbone, Avalon, AXI, etc.) to the SDRAM interface.
    Also intended to support memory-mapped and streaming (FIFO
    mode).  In streaming / FIFO mode the external memory acts as
    one large FIFO.  The SDRAM controller type is determine by
    the internal interface (ibus) passed.

    This SDRAM controller is a port of the Xess SDRAM controller
    for the Xula boards.
    https://github.com/xesscorp/XuLA/blob/master/FPGA/XuLA_lib/SdramCntl.vhd
    """

    States = enum('INITWAIT', 'INITPCHG', 'INITSETMODE', 'INITRFSH', 
                  'RW', 'ACTIVATE', 'REFRESHROW', 'SELFREFRESH')

    Commands = enum('nop', 'active', 'read', 'write', 
                    'pchg', 'mode', 'rfsh',
                    encoding='binary')

    cmdlut = (intbv('011100')[5:], 
              intbv('001100')[5:],
              intbv('010100')[5:],
              intbv('010000')[5:],
              intbv('001000')[5:],
              intbv('000000')[5:],
              intbv('000100')[5:])

    sdram = extram
    sdram.cmd = Signal(intbv(0)[5:])

    timer = Signal(intbv(0, min=0, max=sdram.cyc_init))
    ras_timer = Signal(intbv(0, min=0, max=sdram.cyc_ras))
    wr_timer = Signal(intbv(0, min=0, max=sdram.cyc_wr))
    
    state = Signal(States.INITWAIT)

    @always_seq(clock.posedge, reset=reset)
    def rtl_sdram_controller():
        
        # this is one big state-machine but ...
        if state == States.INITWAIT:
            if sdram.lock:
                timer.next = sdram.cyc_init
                state.next = States.initpchg
            else:
                sdram.sd_cke.next = False
            sdram.status.next = 1

        elif state == States.INITPCHG:
            sdram.cmd.next = Commands.PCHG
            sdram.addr[CMDBITS] = Commands.ALL_BANKS
            timer.next = sdram.cycles

    return rtl_sdram_controller

def get_fmax(fn, info):
    log = open(fn, 'r')
    fmax = []
    States = enum('search', 'fmax')
    state = States.search
    glncnt,lncnt = 0,0

    for ln in log:
        if state == States.search:
            if glncnt > 100 and ln.find('Fmax Summary') != -1:
                lncnt = 1
                state = States.fmax

        elif state == States.fmax:
            if lncnt == 5:
                fstr = ln.split(';')
                if len(fstr) < 2:
                    state = States.search
                    continue
                fstr = fstr[1].split()
                fstr = fstr[0].strip()
                fmax.append(fstr)

            if lncnt >= 6:
                state = States.search

        lncnt += 1
        glncnt += 1

    if len(fmax) > 0:
        info['fmax'] = min(map(float, fmax))
    else:
        info['fmax'] = -1
    
    return info

	def gen_wbs_stm(self, *operations):
	"""
		State machine generator for slave
		This function generate the state signal and generator for the state machine
		Basic operations: Single read/write, Block read/write
		Arguments:
		* operations: a list of optional supported operations for the state machine. 
		Example:
		mygen = wishbone_slave_generator(theslave)
		mygen.gen_wbs_stm("")
	"""
		# states definition
		self.wbsstate_t = enum("wbs_idle", "wbs_incycle", "wbs_read_wait", "wbs_write_wait")
		self.wbsstate_cur = Signal(self.wbsstate_t.wbs_idle)
		
		# flag answer signals
		self.flagbusy = Signal(intbv(0)[1:])
		self.flagerr = Signal(intbv(0)[1:])
		# throttle flag
		self.flagwait = Signal(intbv(0)[1:])
		
		# state machine: transitions
		@always(self.wbssig.CLK_I.posedge, self.wbssig.RST_I.negedge)
		def wbsstate_proc():
			if self.wbssig.RST_I = 1:
				self.wbsstate_cur.next = self.wbsstate_t.wbs_idle
			else:

def whitebox_reset(resetn,
                  dac_clock,
                  clear_enable,
                  clearn):

    state_t = enum('CLEAR', 'CLEARING', 'RUN')
    state = Signal(state_t.CLEAR)

    sync_clear_en = Signal(bool(0))
    clear_en = Signal(bool(0))
    clear_count = Signal(intbv(0)[10:])

    @always_seq(dac_clock.posedge, reset=resetn)
    def controller():
        sync_clear_en.next = clear_enable
        clear_en.next = sync_clear_en
        if state == state_t.CLEAR:
            clearn.next = 0
            clear_count.next = 16
            state.next = state_t.CLEARING
        elif state == state_t.CLEARING:
            clear_count.next = clear_count - 1
            if clear_count == 0:
                state.next = state_t.RUN
            else:
                state.next = state_t.CLEARING
        if state == state_t.RUN:
            clearn.next = 1
            if clear_en:
                state.next = state_t.CLEAR
    
    return controller

 def testUniqueLiterals(self):
     try:
         t_State = enum("SEARCH", "CONFIRM", "SEARCH")
     except ValueError:
         pass
     else:
         self.fail()

    def __init__(self, intf):
        """ SDRAM Model
        This will model the behavior and cycle accurate interface to
        an SDRAM device.

        Usage:
            extmembus = SDRAMInterface()          # interface and transactors
            sdram_model = SDRAMModel(extmembus)   # model
            sdram_proc = sdram_model.process()    # send to simulator

        This model implements the functionality described in the Micron
        datasheet for a 256Mb device:
        http://www.micron.com/parts/dram/sdram/mt48lc16m16a2b4-6a-it?pc=%7B5144650B-31FA-410A-993E-BADF981C54DD%7D

        Not convertible.
        """
        assert isinstance(intf, SDRAMInterface)

        # external interface to the controller, the SDRAM interface
        # also contains the SDRAM timing parameters.
        self.intf = intf

        # emulate banks in an SDRAM
        self.banks = [{} for _ in range(intf.num_banks)]

        # typically DRAM is defined using states (@todo add reference)
        self.States = enum("IDLE", "ACTIVE")
        self.Commands = intf.Commands

def uarttx(glbl, fbustx, tx, baudce):
    """UART transmitter  function
    
    Arguments(Ports):
        glbl : rhea.Global interface, clock and reset
        fbustx : FIFOBus interface to the TX fifo
        tx : The actual transmition line

    Parameters:
        baudce : The transmittion baud rate

    myhdl convertible
    """
    clock, reset = glbl.clock, glbl.reset

    states = enum("wait", "start", "byte", "stop", "end")
    state = Signal(states.wait)
    txbyte = Signal(intbv(0)[8:])
    bitcnt = Signal(intbv(0, min=0, max=9))

    @always_seq(clock.posedge, reset=reset)
    def beh_tx():
        # default values
        fbustx.read.next = False

        # state handlers
        if state == states.wait:
            if not fbustx.empty and baudce:
                txbyte.next = fbustx.read_data
                fbustx.read.next = True
                state.next = states.start

        elif state == states.start:
            if baudce:
                bitcnt.next = 0
                tx.next = False
                state.next = states.byte

        elif state == states.byte:
            if baudce:
                bitcnt.next = bitcnt + 1
                tx.next = txbyte[bitcnt]
            elif bitcnt == 8:
                state.next = states.stop
                bitcnt.next = 0

        elif state == states.stop:
            if baudce:
                tx.next = True
                state.next = states.end

        elif state == states.end:
            if baudce:
                state.next = states.wait

        else:
            assert False, "Invalid state %s" % (state)

    return myhdl.instances()

    def process(self, glbl, lcd):
        """
        """
        self.update_cnt = 0

        # ...
        self.states = enum('init')
        
        # use a dictionary to capture all the 
        regfile = {}

        # emulate the behavior of the LT24 LCD interface, the min pulses
        # (strobes) is 15ns and require 15ns between, the max write rate 
        # is 33 Mpix/sec.  Most (all) commands accept 4 bytes (4 writes)
        # for a command.
        @instance
        def beh():

            while True:
                command_in_progress = False
                # numbytes actually the number of transfers
                numbytes, cmdbytes = 0, []
                self.reset_cursor()

                # wait for a new command
                # @todo: add timing checks
                yield lcd.csn.negedge
                wrn, rdn = bool(lcd.wrn), bool(lcd.rdn)

                # handle a transaction (csn low pulse)
                while not lcd.csn or command_in_progress:
                    if lcd.csn and command_in_progress:
                        regfile[cmd] = copy(cmdbytes)
                        command_in_progress = False
                        print("{:<10d}:LT24: cmd 0x{:02X}, numdata {}, data {}".format(
                            now(), cmd, numbytes, list(map(hex, cmdbytes[:])), ))
                    # check for rising edge of wrn or rdn
                    if not wrn and lcd.wrn:
                        if not lcd.dcn:
                            # a command received
                            command_in_progress = True
                            cmd = int(lcd.data[8:])
                            if cmd not in regfile:
                                regfile[cmd] = []
                        else:
                            if command_in_progress:
                                if cmd == 0x2C:
                                    self.update_next_pixel(int(lcd.data))
                                else:
                                    cmdbytes += [int(lcd.data[8:])]
                                numbytes += 1
                            else:
                                assert False, "Unexpected data!"

                    wrn, rdn = bool(lcd.wrn), bool(lcd.rdn)
                    yield delay(2)

        return beh

    def process(self, glbl, vga):
        """
        """
        # keep track of the number of updates
        self.update_cnt = 0

        # VGA driver essentially a state-machine with the following
        # states.  Typically implemented as a bunch of counters.
        self.States = enum('INIT', 'DISPLAY', 
                           'HFP', 'HSYNC', 'HBP', 
                           'VFP', 'VSYNC', 'VBP',
                           'END')

        # state table, small function to handle each state
        self.StateFuncs = {
            self.States.INIT: None,
            self.States.DISPLAY: self._state_display,
            self.States.HFP: self._state_hor_front_porch,
            self.States.HSYNC: self._state_hor_sync,
            self.States.HBP: self._state_hor_back_porch,
            self.States.VFP: self._state_ver_front_porch,
            self.States.VSYNC: self._state_ver_sync,
            self.States.VBP: self._state_ver_back_porch,
            self.States.END: None
        }
        
        self.state = self.States.INIT
        counters = Counters()

        # montior signals for debugging
        #_state = Signal(intbv(0, min=0, max=len(self.States)))
        _state = Signal(str(""))
        hcnt = Signal(intbv(0)[16:])
        vcnt = Signal(intbv(0)[16:])
        # end monitors

        @instance
        def g_capture_vga():            
            while True:
                #print(self.state)
                if self.state == self.States.INIT:
                    print("%10d Screen update, %d, in progress" % (now(), self.update_cnt))
                    counters.reset()
                    self.state = self.States.DISPLAY
                elif self.state == self.States.END:
                    self.state = self.States.INIT
                else:
                    yield self.StateFuncs[self.state](glbl, vga, counters)

        # monitor, sample each variable at each clock
        @always(glbl.clock.posedge)
        def g_monitor():
            _state.next = self.state._name
            hcnt.next = counters.hcnt
            vcnt.next = counters.vcnt
                        
        return g_capture_vga, g_monitor

def uarttx(glbl, fbustx, tx, baudce):
    """
    """
    clock, reset = glbl.clock, glbl.reset

    states = enum('wait', 'start', 'byte', 'stop', 'end')
    state = Signal(states.wait)
    txbyte = Signal(intbv(0)[8:])
    bitcnt = Signal(intbv(0, min=0, max=9))

    @always_seq(clock.posedge, reset=reset)
    def rtltx():
        # default values
        fbustx.rd.next = False

        # state handlers
        if state == states.wait:
            if not fbustx.empty and baudce:
                txbyte.next = fbustx.rdata
                fbustx.rd.next = True
                state.next = states.start

        elif state == states.start:
            if baudce:
                bitcnt.next = 0
                tx.next = False
                state.next = states.byte

        elif state == states.byte:
            if baudce:
                bitcnt.next = bitcnt + 1
                tx.next = txbyte[bitcnt]
            elif bitcnt == 8:
                state.next = states.stop
                bitcnt.next = 0

        elif state == states.stop:
            if baudce:
                tx.next = True
                state.next = states.end

        elif state == states.end:
            if baudce:
                state.next = states.wait

        else:
            assert False, "Invalid state %s" % (state)

    return rtltx

	def gen_wbm_stm(self, *operations):
	"""
		State machine generator for master
		This function generate the state signal and generator for the state machine
		Basic operations: Single read/write, Block read/write
		Arguments:
		* operations: a list of optional supported operations for the state machine. 
		Example:
		mygen = wishbone_master_generator(themaster)
		mygen.gen_wbm_stm("")
	"""
		# states definition
		self.wbmstate_t = enum("wbm_idle", "wbm_incycle", "wbm_read_wait", "wbm_write_wait", "wbm_rmw_rdwait", "wbm_rmw_midwait", "wbm_rmw_wrwait")
		self.wbmstate_cur = Signal(self.wbmstate_t.wbm_idle)
		
		# list of trigger signals and related states
		self.list_trigsignals = []
		for i in zip(("trig_read", "trig_write", "trig_rmw"), self.wbmstate_t._names[2:5]):
			self.list_trigsignals.append({"name": i[0], "initstate": i[1], "trig": Signal(intbv(0)[1:])})
			
		# Vector of triggers: for use in state machine
		trig_vector = Signal(intbv(0)[3:])
		trig_list = (x["trig"] for x in self.list_trigsignals)
		@always_comb
		def trigvectgen():
			trig_vector.next = concat(*trig_list)
			
		# Vector of acknowledge signals: for use in state machine
		ack_list = [self.ACK_I]
		if self.RTY_I != None:
			ack_list.append(self.RTY_I)
		if self.ERR_I != None:
			ack_list.append(self.ERR_I)
		ack_vector = Signal(intbv(0)[len(ack_list):])
		# the error signals can be sliced with [1:]
		@always_comb
		def ackvectgen():
			ack_vector.next = concat(*ack_list)
		
		# state machine: transitions
		@always(self.wbmsig.CLK_I.posedge, self.wbmsig.RST_I.negedge)
		def wbmstate_proc():
			if self.wbmsig.RST_I = 1:
				self.wbmstate_cur.next = self.wbmstate_t.wbm_idle
			else:

def PS2Keyboard(
        code,
        finish,
        kb_dat,
        kb_clk,
        rst
    ):
    States = enum('READ', 'FINISH')

    state = Signal(States.FINISH)

    # Eight Data bits and One Parity. 
    bits = [Signal(bool(0)) for k in range(9)]
    code_reg = ConcatSignal(*bits)
    bit_counter = Signal(intbv(0, min=0, max=10))
    
    @always_seq(kb_clk.posedge, reset=rst)
    def receiving():
        if state == States.FINISH:
            if not kb_dat:
                # kb_dat=0, device starts a new transmission. 
                state.next = States.READ
                finish.next = 0
            else:
                # kb_dat=1, the stop bit. 
                code.next = code_reg
                finish.next = 1
        elif state == States.READ:
            # Shift Register. 
            bits[0].next = kb_dat
            for k in range(1, 9):
                bits[k].next = bits[k-1]
            # End Shift Register.
            if bit_counter == 8:
                # Have got all the 8bits and parity.
                state.next = States.FINISH
                bit_counter.next = 0
            else:
                bit_counter.next = bit_counter + 1
        else:
            raise ValueError('Undefined state.')

    return instances()

    def __init__(self, system, bus, divider, width = 32, strict_sdoe = True):
        self.system = system
        self.bus = bus

        self.states = enum(
            "IDLE", "START", "PRE", "FIRST", "SECOND", "POST", "PULSE")
        self.state = Signal(self.states.IDLE)

        self.divider = divider
        self.strict_sdoe = strict_sdoe

        self.data_reg = Signal(intbv(0)[width:])

        self.count = Signal(intbv(0)[8:])
        self.count_port = Port(self.count.val)
        self.cpha_reg = Signal(False)
        self.cpol_reg = Signal(False)
        self.pulse_reg = Signal(False)
        self.cs_reg = Signal(self.bus.CS.val)

        self.div_val = Signal(intbv(0, 0, self.divider + 1))

def apb3_simple_slave(bus, status_led):
    bus_presetn = bus.presetn
    bus_pclk = bus.pclk
    bus_paddr = bus.paddr
    bus_psel = bus.psel
    bus_penable = bus.penable
    bus_pwrite = bus.pwrite
    bus_pwdata = bus.pwdata
    bus_pready = bus.pready
    bus_prdata = bus.prdata
    bus_pslverr = bus.pslverr

    state_t = enum('IDLE', 'DONE',)
    state = Signal(state_t.IDLE)

    counter = Signal(intbv(0)[len(bus_prdata):])

    @always_seq(bus_pclk.posedge, reset=bus_presetn)
    def state_machine():
        status_led.next = counter[0]
        if state == state_t.IDLE:
            if bus_penable and bus_psel:
                if bus_paddr[8:] == 0x40:
                    bus_pready.next = False
                    if bus_pwrite:
                        counter.next = bus_pwdata
                        state.next = state_t.DONE
                    else:
                        bus_prdata.next = counter
                        counter.next = counter + 1
                        state.next = state_t.DONE
                else:
                    state.next = state_t.DONE
            else:
                state.next = state_t.IDLE
        elif state == state_t.DONE:
            bus_pready.next = True
            state.next = state_t.IDLE

    return state_machine

def mem_test(glbl, memmap, progress, error, done,
        start_address=0x00000000, end_address=0xFFFFFFFF):
    """
    This module performs a memory test over the memory-map bus
    """
    if end_address > memmap.addr.max:
        end_address = memmap.addr.max

    States = enum('init', 'write', 'write_ack', 'compare_read',
                  'compare', 'end')
    state = Signal(States.init)

    clock, reset = glbl.clock, glbl.reset

    rglbl, randgen = random_generator.portmap.values()
    randgen.data = Signal(memmap.wdata.val)
    rglbl.clock, rglbl.reset = clock, reset
    rand_inst = random_generator(glbl, randgen)

    @always_seq(clock.posedge, reset=reset)
    def beh():

        # defaults
        randgen.load.next = False
        randgen.enable.next = False

        if state == States.init:
            randgen.load.next = True
            randgen.enable.next = True
            error.next = False
            progress.next = 0
            memmap.addr.next = start_address

        elif state == States.write:
            progress.next = 1
            memmap.write.next = True
            memmap.wdata.next = randgen.data
            state.next = States.write.ack
            randgen.enable.next = True

        elif state == States.write_ack:
            memmap.write.next = False
            if memmap.addr == end_address-1:
                randgen.load.next = True
                state.next = States.compare_read
                memmap.addr.next = start_address
            else:
                memmap.addr.next = memmap.addr + 1
                state.next = States.write

        elif state == States.compare_read:
            progress.next = 2
            memmap.read.next = True

        elif state == States.compare:
            memmap.read.next = False
            randgen.enable.next = True
            if memmap.rdata != randgen.data:
                error.next = True

            if memmap.addr == end_address-1:
                state.next = States.end
            else:
                memmap.addr.next = memmap.addr + 1
                state.next = States.compare.read

        elif state == States.end:
            pass

        else:
            assert False, "Invalid state %s" % (state,)

    return myhdl.instances()

def lt24lcd(glbl, vmem, lcd):
    """ A video display driver for the terasic LT24 LCD display. 
    
    This driver reads pixels from the VideoMemory interface and transfers
    them to the LT24 display.  This hardware module (component) will also
    perform the initial display configuration.
    
    Ports:
        glbl (Global): global signals, clock, reset, enable, etc. 
        vmem (VideoMemory): video memory interface, the driver will read 
                            pixels from this interface. 
        lcd (LT24Interface): The external LT24 interface. 
        
    Parameters:
        None 
        
    RGB 5-6-5 (8080-system 16bit parallel bus)
    """
    assert isinstance(lcd, LT24Interface)
    resolution, refresh_rate = (240, 320), 60
    number_of_pixels = resolution[0] * resolution[1]

    # local references to signals in interfaces
    clock, reset = glbl.clock, glbl.reset

    # make sure the user timer is configured
    assert glbl.tick_user is not None

    # write out a new VMEM to the LCD display, a write cycle
    # consists of putting the video data on the bus and latching
    # with the `wrx` signal.  Init (write once) the column and
    # page addresses (cmd = 2A, 2B) then write mem (2C)
    states = enum(
        'init_wait_reset',        # wait for the controller to reset the LCD
        'init_start',             # start the display init sequence
        'init_start_cmd',         # send a command, port of the display seq
        'init_next',              # determine if another command

        'write_cmd_start',         # command subroutine
        'write_cmd',               # command subroutine

        'display_update_start',    # update the display
        'display_update_start_p',  # delay for command ack
        'display_update',          # update the display
        'display_update_next',     # wait for driver to ack pixel xfered
        'display_update_end'       # end of display update 
    )

    state = Signal(states.init_wait_reset)
    state_prev = Signal(states.init_wait_reset)
    cmd = Signal(intbv(0)[8:])
    return_state = Signal(states.init_wait_reset)

    num_hor_pxl, num_ver_pxl = resolution
    print("resolution {}x{} = {} number of pixes".format(
          num_hor_pxl, num_ver_pxl, number_of_pixels))
    hcnt = intbv(0, min=0, max=num_hor_pxl)
    vcnt = intbv(0, min=0, max=num_ver_pxl)

    # signals to start a new command transaction to the LCD
    datalen = Signal(intbv(0, min=0, max=number_of_pixels+1))
    data = Signal(intbv(0)[16:])
    datasent = Signal(bool(0))
    datalast = Signal(bool(0))
    cmd_in_progress = Signal(bool(0))

    # --------------------------------------------------------
    # LCD driver
    gdrv = lt24lcd_driver(glbl, lcd, cmd, datalen, data,
                          datasent, datalast, cmd_in_progress)

    # --------------------------------------------------------
    # build the display init sequency ROM
    rom, romlen, maxpause = build_init_rom(init_sequence)
    offset = Signal(intbv(0, min=0, max=romlen+1))
    pause = Signal(intbv(0, min=0, max=maxpause+1))

    # --------------------------------------------------------
    # state-machine

    @always_seq(clock.posedge, reset=reset)
    def rtl_state_machine():
        state_prev.next = state 
        if state == states.init_wait_reset:
            if lcd.reset_complete:
                state.next = states.init_start

        elif state == states.init_start:
            v = rom[offset]
            # @todo: change the table to only contain the number of
            # @todo: bytes to be transferred
            datalen.next = v - 3
            p = rom[offset+1]
            pause.next = p
            offset.next = offset + 2
            state.next = states.init_start_cmd

        elif state == states.init_start_cmd:
            v = rom[offset]
            cmd.next = v
#.........这里部分代码省略.........

        self.outp = Signal(bool(0))
        self.inp = Signal(bool(0))
        self.br_op = Signal(bool(0))
        self.jal = Signal(bool(0))
        self.loadh = Signal(bool(0))
        self.indls = Signal(bool(0))
        self.signals = [self.al_ena, self.ah_ena, self.log_add, self.add_sub, self.shr, self.sel_imm, self.store, \
                        self.outp, self.inp, self.br_op, self.jal, self.loadh, self.indls]

class inpSignal():
    def __init__(self):
        self.rd_data = Signal(intbv(0)[16:])


class outpSignal():
    def __init__(self):
        self.wr_data = Signal(intbv(0)[16:])
        self.wr_strobe = Signal(bool(0))
        self.rd_strobe = Signal(bool(0))
        self.io_addr = Signal(intbv(0)[16:])             



dec_op_type = enum('al_ena', 'ah_ena', 'log_add', 'add_sub',
                    'shr', 'sel_imm', 'store', 'outp', 'inp', 'br_op', 'jal',
                    'loadh', 'indls')

alu_op_type = enum('NOP', 'LD', 'AND', 'OR', 'XOR')

IM_BITS = 9
DM_BITS = 8 

from myhdl import block, always_seq, always_comb, Signal, intbv, enum, \
    ResetSignal
from gemac.crc32 import crc32

txstate = enum('IDLE', 'PREAMBLE', 'SFD', 'FIRSTBYTE', 'INFRAME', 'PADDING',
               'ERROR', 'CRC1', 'CRC2', 'CRC3', 'CRC4', 'SENDPAUSE')


@block
def txengine(txclientintf, txgmii_intf, txflowintf, txconfig, sysreset):
    """Transmit Engine.

    Accepts Ethernet frame data from the Client Transmitter interface,
    adds preamble to the start of the frame, add padding bytes and frame
    check sequence. It ensures that the inter-frame spacing between successive
    frames is at least the minimum specified. The frame is then converted
    into a format that is compatible with the GMII and sent to the GMII Block.

    Args:
        txclientintf (TxClientFIFO) - transmit streaming data interface from transmit FIFO.
        txgmii_intf (TxGMII_Interface) - transmit streaming data interface to GMII.
        flow_intf (TxFlowInterface) - transmit flow control interface.
        txconfig (Signal/intbv)(32 bit) - configregisters - Transmitter configuration word.
            See Xilinx_UG144 pdf, Table 8.5, Pg-80 for detailed description.
        reset - System reset
    """

    state = Signal(txstate.IDLE)
    curbyte = Signal(intbv(1, min=0, max=10000))
    pausereq = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)

def controller_basic(generic, memmap):
    """
    (arguments == ports)
    Arguments:
        generic: barebone interface
        memmap: any memory-map interface

    This module contains a basic memory map controller, the
    barebone bus can be used to start a bus transaction to
    any of the other implemented memory-mapped buses.

    """

    assert isinstance(generic, Barebone)
    assert isinstance(memmap, MemoryMapped)

    states = enum('idle', 'wait', 'write', 'writeack', 'read',
                  'readdone', 'done', 'end')
    state = Signal(states.idle)

    timeout_max = 33
    tocnt = Signal(intbv(0, min=0, max=timeout_max))

    # map the generic bus to the bus in use
    conv_inst = memmap.map_from_generic(generic)

    @always_seq(memmap.clock.posedge, reset=memmap.reset)
    def beh_sm():

        # ~~~[Idle]~~~
        if state == states.idle:
            if not generic.done:
                state.next = states.wait
            elif generic.write:
                state.next = states.write
            elif generic.read:
                state.next = states.read

        # ~~~[Wait]~~~
        elif state == states.wait:
            if generic.done:
                tocnt.next = 0
                if generic.write:
                    state.next = states.done
                elif generic.read:
                    state.next = states.readdone

        # ~~~[Write]~~~
        elif state == states.write:
            state.next = states.done
            tocnt.next = 0

        # ~~~[Read]~~~
        elif state == states.read:
            state.next = states.readdone

        # ~~~~[ReadDone]~~~
        elif state == states.readdone:
            if generic.done:
                state.next = states.done

        # ~~~[Done]~~~
        elif state == states.done:
            # wait for transaction signals to be release
            if not (generic.write or generic.read):
                state.next = states.idle

        # ~~~[]~~~
        else:
            assert False, "Invalid state %s" % (state,)

    return conv_inst, beh_sm

def exciter(
        resetn,
        system_clock,
        pclk,
        paddr,
        psel,
        penable,
        pwrite,
        pwdata,
        pready,
        prdata,
        pslverr,
        dac_clock,
        dac_data):

    ####### FIFO ############
    # Read
    re = Signal(bool(False))
    rclk = system_clock
    Q = Signal(intbv(0)[32:])

    # Write
    we = Signal(bool(False))
    wclk = pclk
    data = Signal(intbv(0)[32:])

    # Threshold
    full = Signal(bool(False))
    full.driven = 'wire'
    afull = Signal(bool(False))
    afull.driven = 'wire'
    empty = Signal(bool(False))
    empty.driven = 'wire'
    aempty = Signal(bool(False))
    aempty.driven = 'wire'

    fifo_args = resetn, re, rclk, Q, we, wclk, data, full, afull, \
        empty, aempty
    fifo = FIFO(*fifo_args,
        width=32,
        depth=1024)


    ######### RESAMPLER ###########

    ######### INTERLEAVER #########
    in_phase = Signal(bool(0))
    sample_i = Signal(intbv(0, 0, 2**10))
    sample_q = Signal(intbv(0, 0, 2**10))

    ########## STATE MACHINE ######
    state_t = enum('IDLE', 'WRITE_SAMPLE', 'DONE',)
    state = Signal(state_t.IDLE)

    ############ TX EN ###########
    txen = Signal(bool(0))

    @always_seq(pclk.posedge, reset=resetn)
    def state_machine():
        if state == state_t.IDLE:
            if penable and psel and pwrite:
                if paddr[8:] == 0x00:
                    state.next = state_t.WRITE_SAMPLE
                    pready.next = 0
                    we.next = 1
                    data.next = pwdata
                    if full:
                        raise OverrunError
                elif paddr[8:] == 0x01:
                    print 'hi', pwdata
                    txen.next = pwdata[0]
            elif psel and not pwrite:
                pass

        elif state == state_t.WRITE_SAMPLE:
            we.next = 0
            state.next = state_t.DONE
            
        elif state == state_t.DONE:
            pready.next = 1
            state.next = state_t.IDLE

    @always(system_clock.posedge)
    def resampler():
        if txen:  # Update the sample out of phase, locking
            if re:
                sample_i.next = Q[9:]
                sample_q.next = Q[32:23]
            re.next = not re

    @always(system_clock.posedge)
    def interleaver():
        if txen:
            dac_data.next = sample_i[10:2] if in_phase else sample_q[10:2]
            dac_clock.next = not in_phase
            in_phase.next = not in_phase

    return fifo, state_machine, resampler, interleaver