def test_simulate(self):
        import myhdl
        duration=1

        def _sim():
            pix = Add_shift_top(duration=duration)
            pix_presetn = pix.presetn
            pix_pclk = pix.pclk
            pix_paddr = pix.paddr
            pix_psel = pix.psel
            pix_penable = pix.penable
            pix_pwrite = pix.pwrite
            pix_pwdata = pix.pwdata
            pix_pready = pix.pready
            pix_prdata = pix.prdata
            pix_pslverr = pix.pslverr

            @myhdl.instance
            def __sim():
                yield pix.reset()
                yield pix.transmit(0x4000, 0x0110)
            return __sim

        s = myhdl.Simulation(myhdl.traceSignals(_sim))
        s.run(10000)

def TestBench(MCP3008Tester):

    ch1 = Signal(intbv(0)[10:])
    ch2 = Signal(intbv(0)[10:])
    ch3 = Signal(intbv(0)[10:])
    ch4 = Signal(intbv(0)[10:])
    ch5 = Signal(intbv(0)[10:])
    ch6 = Signal(intbv(0)[10:])
    ch7 = Signal(intbv(0)[10:])
    ch8 = Signal(intbv(0)[10:])
    spi_clk = Signal(LOW)
    spi_ss_n = Signal(HIGH)
    spi_miso = Signal(LOW)
    spi_mosi = Signal(LOW)
    clk = Signal(LOW)
    rst_n = Signal(HIGH)

    MCP3008Driver_inst = traceSignals(MCP3008Driver,
        ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
        spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)

    MCP3008Tester_inst = MCP3008Tester(
        ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
        spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)

    ClkGen_inst = ClkGen(clk)

    return MCP3008Driver_inst, MCP3008Tester_inst, ClkGen_inst

def main_simulate():
    resetn = Signal(bool(1))
    system_clock = Signal(bool(0))
    paddr = Signal(intbv(0, 0, 2**32))
    psel = Signal(bool(0))
    penable = Signal(bool(0))
    pwrite = Signal(bool(1))
    pwdata = Signal(intbv(0, 0, 2**32))
    pready = Signal(bool(0))
    prdata = Signal(intbv(0, 0, 2**32))
    pslverr = Signal(bool(0))
    apb3_bus_signals = [system_clock, resetn, paddr, psel, penable, pwrite,
                        pwdata, pready, prdata, pslverr]

    SYSTEM_CLOCK_FREQ = 10e6
    SYSTEM_CLOCK_PERIOD_IN_NS = int(1.0 / SYSTEM_CLOCK_FREQ * 1e9)

    def testbench():
        clock = drive_system_clock(system_clock, SYSTEM_CLOCK_PERIOD_IN_NS)
        reset = drive_reset(resetn)
        master = apb3_master_mock([(0x40050400, 0xffffffff),
                                   (0x40050400, 0xffff7fff)],
                                  *apb3_bus_signals)
        slave = fluidsp_controller(*(apb3_bus_signals))
        return clock, reset, slave, master

    traced_testbench = traceSignals(testbench)
    sim = Simulation(traced_testbench)
    sim.run(SYSTEM_CLOCK_PERIOD_IN_NS * 100)

    def test_simulate(self):
        import myhdl
        duration=1

        def _sim():
            bus = Apb3Bus(duration=duration)
            bus_presetn = bus.presetn
            bus_pclk = bus.pclk
            bus_paddr = bus.paddr
            bus_psel = bus.psel
            bus_penable = bus.penable
            bus_pwrite = bus.pwrite
            bus_pwdata = bus.pwdata
            bus_pready = bus.pready
            bus_prdata = bus.prdata
            bus_pslverr = bus.pslverr
            
            @myhdl.instance
            def __sim():
                yield bus.reset() 
                yield bus.transmit(0x4000, 0x0110)
            return __sim

        s = myhdl.Simulation(myhdl.traceSignals(_sim))
        s.run(10000)

def testBench():

    if not DEBUG:
        datapath_i = traceSignals(pipeline)  # () #toVHDL(datapath)
    else:
        datapath_i = pipeline()

    return instances()

def sim():
    insts = []
    insts.append(traceSignals(gen, *args))
    insts.append(stimuli())
    sim = Simulation(insts)
    sim.run(duration)
    print
    sys.stdout.flush()

    def __call__(self):
        if self.trace:
            #traceSignals.timescale = toMyHDL.timescale
            traceSignals.name = self.name
            gen = traceSignals(self.top, *self.args, **self.kwargs)
        else:
            gen = self.top(*self.args, **self.kwargs)

        return gen

def sim():
    from myhdl import Simulation, traceSignals
    import sys

    test_inst = traceSignals(create_test)

    sim = Simulation(test_inst)
    sim.run(20000)
    print
    sys.stdout.flush()

    def sim(self):
        insts = []

        insts.append(traceSignals(self.gen, *self.args))
        insts += self.stimuli

        sim = Simulation(insts)
        sim.run(self.duration)
        print
        sys.stdout.flush()

def testBench():


    if not DEBUG:
        datapath_i = traceSignals(dlx)  #() #toVHDL(datapath)
    else:
        datapath_i = dlx()

    

    return instances()

def test_memory():
    """
    Memory: Test load and R/W operations.
    """
    gen_test_file()
    trace = False
    if trace:
        sim = Simulation(traceSignals(_testbench))
    else:
        sim = Simulation(_testbench())
    sim.run()

def test_core(hex_file, vcd):
    """
    Core: Behavioral test for the RISCV core.
    """
    if vcd:
        vcd = traceSignals(core_testbench, hex_file,)
        sim = Simulation(vcd)
    else:
        sim = Simulation(core_testbench(hex_file))

    sim.run()

def test_cache():
    """
    Cache: Test loading from memory
    """
    gen_test_file()
    trace = False
    if trace:
        sim = Simulation(traceSignals(_testbench))
    else:
        sim = Simulation(_testbench())
    sim.run()

def sim(visu = False):
  try:
    os.remove('_bench.vcd')
  except Exception as e:
    pass # just ignore, the file is probably not here.

  fsm = traceSignals(testbench())
  sim = Simulation(fsm)
  sim.run()
  if visu:
    call(['gtkwave', '_bench.vcd'])

def main():
    args = cliparse()
    if args.trace:
        mosi, miso, sck, ss = Signals(bool(0), 4)
        led = Signal(bool(0))
        clock=Clock(0, frequency=50e6)
        tb_fsm = traceSignals(tb,led, clock, mosi, miso, sck, ss, reset=None)
        sim = Simulation(tb_fsm)
        sim.run()  
    if args.build:
        build(args)    

    def simulate(self, stimulus, whitebox, **kwargs):
        """Acturally run the cosimulation with iverilog.
        
        :param stimulus: A callable that returns the cosim object.
        :param whitebox: A whitebox peripheral object.
        :param record_tx: Record the passed in number of valid samples.
        :param auto_stop: Raise ``StopSimulation`` when the correct number of samples have been recorded.
        :param sample_rate: Samples per second.
        """
        record_tx = kwargs.get('record_tx', None)
        auto_stop = kwargs.get('auto_stop', False)
        self.sample_rate = kwargs.get('sample_rate', 10e6)
        DAC2X_DURATION = int(1e9 / (self.sample_rate * 2))
        DAC_DURATION = int(1e9 / self.sample_rate)

        @instance
        def dac2x_clock():
            while True:
                self.dac2x_clock.next = not self.dac2x_clock
                yield delay(DAC2X_DURATION // 2)

        @instance
        def dac_clock():
            yield delay(DAC2X_DURATION // 4)
            while True:
                self.dac_clock.next = not self.dac_clock
                yield delay(DAC_DURATION // 2)

        @always(self.dac_clock.posedge,
                self.dac_clock.negedge,
                self.bus.presetn.negedge)
        def tx_recorder():
            if not self.bus.presetn:
                self.tx_q = []
                self.tx_i = []
                self.tx_n = []
            elif len(self.tx_i) == len(self.tx_q) and len(self.tx_i) == record_tx:
                if auto_stop:
                    raise StopSimulation
            elif self.dac_en:
                if self.dac_clock:
                    self.tx_q.append(int(self.dac_data[:]))
                    self.tx_n.append(now())
                else:
                    self.tx_i.append(int(self.dac_data[:]))

        traced = traceSignals(whitebox)
        ss = [dac_clock, dac2x_clock, stimulus, traced]
        if 'record_tx' in kwargs:
            ss.append(tx_recorder)
        s = Simulation(ss)
        s.run()

    def simulate_quadrature(self, in_i, in_q, dspflow, **kwargs):
        """Actually run the simulation, with separate i and q inputs.

        :param in_i: The input i sequence.
        :param in_q: The input q sequence.
        :param dspflow: The MyHDL module representing the dsp flow.
        :param interp: How many samples to zero-stuff.
        :returns: The valid i and q sequences as a tuple.
        """
        interp = kwargs.get('interp', 1)
        loader = kwargs.get('loader', None)
        @instance
        def stimulus():
            self.t = 0

            if loader:
                yield loader()

            self.clearn.next = self.clearn.active
            yield self.delay(1)
            self.clearn.next = not self.clearn.active

            while self.t < len(in_i):
                yield self.produce(self.input.myhdl(in_i[self.t]),
                        self.input.myhdl(in_q[self.t]), interp)
                self.t = self.t + 1
            self.input.valid.next = False
            yield self.delay(1)
            while self.output.valid:
                self.consume()
                yield self.delay(1)
            raise StopSimulation

        # Show the input
        #f_chain_in = figure_discrete_quadrature("chain in", 223, f, self.input, in_n, in_i, in_q)

        traced = traceSignals(dspflow)

        recordings = [s.record(self.clearn, self.clock) for s in self.recording]

        s = Simulation(stimulus, recordings, traced)
        s.run()

        final_i, final_q = (np.array(self.results_i, dtype=self.output.numpy_dtype()),
                np.array(self.results_q, dtype=self.output.numpy_dtype()))
        assert len(final_i) == len(final_q)
        final_n = np.arange(final_i.shape[0])

        #f_chain_out = figure_discrete_quadrature("chain out", 224, f, self.output, final_n, final_i, final_q)
        return final_i, final_q

def sim():
    from myhdl import Simulation, traceSignals

    insts, test_gen, test_args = setup()

    test_inst = traceSignals(test_gen, *test_args)
    insts.append(test_inst)

    if 1:
        reader_inst = reader(test_args[0], test_args[1], 64, 123 * nsec)
        insts.append(reader_inst)

    sim = Simulation(*insts)
    sim.run(5 * usec)

def testBench(width):
    
    B = Signal(intbv(0))
    G = Signal(intbv(0))
    
    dut = traceSignals(bin2gray, B, G, width)

    @instance
    def stimulus():
        for i in range(2**width):
            B.next = intbv(i)
            yield delay(10)
            print "B: " + bin(B, width) + "| G: " + bin(G, width)

    return dut, stimulus

    def _getDut(self, func, **kwargs):
        ''' Returns a simulation instance of func. 
            Uses the simulator specified by self._simulator. 
            Enables traces if self._trace is True
                func - MyHDL function to be simulated
                kwargs - dict of func interface assignments: for signals and parameters
        '''
        if self._simulator=="myhdl":
            if not self._trace:
                sim_dut = func(**kwargs)
            else:
                sim_dut = traceSignals(func, **kwargs)
        else:
            sim_dut = self._getCosimulation(func, **kwargs)

        return sim_dut