def main():
    #sim = Simulation(testBench())
    #sim.run()
    pc_adder_in, data1_in, data2_in, address32_in, jumpaddr_in = [Signal(intbv(random.randint(-255, 255), min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(5)]
    pc_adder_out, data1_out, data2_out, address32_out, branch_addr32_out, jumpaddr_out = [Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(6)]

    rs_in, rd_in, rt_in, rd_out, rt_out, rs_out, shamt_in, shamt_out = [Signal(intbv(0)[5:]) for i in range(8)]
    func_in, func_out = [Signal(intbv(0)[6:]) for i in range(2)]

    RegDst_in, ALUop_in, ALUSrc_in = [Signal(intbv(0)[1:]) for i in range(3)]
    Branch_in, Jump_in, MemRead_in, MemWrite_in = [Signal(intbv(0)[1:]) for i in range(4)]
    RegWrite_in, MemtoReg_in = [Signal(intbv(0)[1:]) for i in range(2)]

    RegDst_out, ALUop_out, ALUSrc_out = [Signal(intbv(0)[1:]) for i in range(3)]
    Branch_out, Jump_out, MemRead_out, MemWrite_out = [Signal(intbv(0)[1:]) for i in range(4)]
    RegWrite_out, MemtoReg_out = [Signal(intbv(0)[1:]) for i in range(2)]

    clk = Signal(intbv(0)[1:])
    rst = Signal(intbv(0)[1:])

    toVerilog(latch_id_ex, clk, rst,
            pc_adder_in,
            data1_in, data2_in, address32_in, jumpaddr_in,
            rs_in, rt_in, rd_in, shamt_in, func_in,
            RegDst_in, ALUop_in, ALUSrc_in,  # signals to EX pipeline stage
            Branch_in, Jump_in, MemRead_in, MemWrite_in,  # signals to MEM pipeline stage
            RegWrite_in, MemtoReg_in,  # signals to WB pipeline stage
            pc_adder_out,
            data1_out, data2_out, address32_out, branch_addr32_out, jumpaddr_out,
            rs_out, rt_out, rd_out, shamt_out, func_out,
            RegDst_out, ALUop_out, ALUSrc_out,
            Branch_out, Jump_out, MemRead_out, MemWrite_out,
            RegWrite_out, MemtoReg_out)

def convert_to_verilog(args):
    clk          = Signal(False)
    rst          = Signal(False)
    imem_addr_o  = Signal(modbv(0)[32:])
    imem_dat_o   = Signal(modbv(0)[32:])
    imem_sel_o   = Signal(modbv(0)[4:])
    imem_cyc_o   = Signal(False)
    imem_we_o    = Signal(False)
    imem_stb_o   = Signal(False)
    imem_dat_i   = Signal(modbv(0)[32:])
    imem_ack_i   = Signal(False)
    imem_err_i   = Signal(False)
    dmem_addr_o  = Signal(modbv(0)[32:])
    dmem_dat_o   = Signal(modbv(0)[32:])
    dmem_sel_o   = Signal(modbv(0)[4:])
    dmem_cyc_o   = Signal(False)
    dmem_we_o    = Signal(False)
    dmem_stb_o   = Signal(False)
    dmem_dat_i   = Signal(modbv(0)[32:])
    dmem_ack_i   = Signal(False)
    dmem_err_i   = Signal(False)
    toHost       = Signal(modbv(0)[32:])

    toVerilog(CoreHDL, clk, rst, toHost, imem_addr_o, imem_dat_o, imem_sel_o, imem_cyc_o, imem_we_o,
              imem_stb_o, imem_dat_i, imem_ack_i, imem_err_i, dmem_addr_o, dmem_dat_o, dmem_sel_o,
              dmem_cyc_o, dmem_we_o, dmem_stb_o, dmem_dat_i, dmem_ack_i, dmem_err_i)

def convert():
    q = Signal(intbv(0)[1:0])
    d = Signal(intbv(0)[1:0])
    wr, rst = [Signal(bool(0)) for i in range(2)]

    toVerilog(dff, q, d, wr, rst)
    toVHDL(dff, q, d, wr, rst)

    def _getCosimulation(self, func, **kwargs):
        ''' Returns a co-simulation instance of func. 
            Uses the _simulator specified by self._simulator. 
            Enables traces if self._trace is True
                func - MyHDL function to be simulated
                kwargs - dict of func interface assignments: for signals and parameters
        '''
        vals = {}
        vals['topname'] = func.func_name
        vals['unitname'] = func.func_name.lower()
        hdlsim = self._simulator
        if not hdlsim:
            raise ValueError("No _simulator specified")
        if not self.sim_reg.has_key(hdlsim):
            raise ValueError("Simulator {} is not registered".format(hdlsim))

        hdl, analyze_cmd, elaborate_cmd, simulate_cmd = self.sim_reg[hdlsim]

        # Convert to HDL
        if hdl == "verilog":
            toVerilog(func, **kwargs)
            if self._trace:
                self._enableTracesVerilog("./tb_{topname}.v".format(**vals))
        elif hdl == "vhdl":
            toVHDL(func, **kwargs)

        # Analyze HDL
        os.system(analyze_cmd.format(**vals))
        # Elaborate
        if elaborate_cmd:
            os.system(elaborate_cmd.format(**vals))
        # Simulate
        return Cosimulation(simulate_cmd.format(**vals), **kwargs)

def main():
    #sim = Simulation(testBench())
    #sim.run()
    branch_adder_in, alu_result_in, data2_in, wr_reg_in = [Signal(intbv(random.randint(-255, 255), min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(4)]
    branch_adder_out, alu_result_out, data2_out, wr_reg_out = [Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(4)]

    zero_in, zero_out = [Signal(intbv(0)[1:]) for i in range(2)]

    Branch_in, MemRead_in, MemWrite_in = [Signal(intbv(0)[1:]) for i in range(3)]
    RegWrite_in, MemtoReg_in = [Signal(intbv(0)[1:]) for i in range(2)]

    Branch_out, MemRead_out, MemWrite_out = [Signal(intbv(0)[1:]) for i in range(3)]
    RegWrite_out, MemtoReg_out = [Signal(intbv(0)[1:]) for i in range(2)]

    clk = Signal(intbv(0)[1:])
    rst = Signal(intbv(0)[1:])


    toVerilog(latch_ex_mem, clk, rst,
                        branch_adder_in,
                        alu_result_in,
                        data2_in, wr_reg_in,
                        MemRead_in, MemWrite_in,  # signals to MEM pipeline stage
                        RegWrite_in, MemtoReg_in,  # signals to WB pipeline stage
                        branch_adder_out,
                        alu_result_out,
                        data2_out, wr_reg_out,
                        MemRead_out, MemWrite_out,
                        RegWrite_out, MemtoReg_out,
                        )

def emit_connect():
    from myhdl import toVerilog

    bus = DdrBus(2, 12, 2)
    rename_interface(bus, 'bus')

    soc_clk = Signal(False)
    soc_clk_b = Signal(False)

    soc_cs = Signal(False)
    soc_ras = Signal(False)
    soc_cas = Signal(False)
    soc_we = Signal(False)
    soc_ba = Signal(False)
    soc_a = Signal(False)

    soc_dqs = Signal(intbv(0)[bus.d_width:])
    soc_dm = Signal(intbv(0)[bus.d_width:])
    soc_dq = Signal(intbv(0)[bus.d_width * 8:])

    toVerilog(ddr_connect, bus, soc_clk, soc_clk_b, None,
              soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
              soc_dqs, soc_dm, soc_dq)

    print
    print open('ddr_connect.v', 'r').read()

def testbench_streamer(args=None):

    args = tb_default_args(args)
    if not hasattr(args, 'keep'):
        args.keep = False
    if not hasattr(args, 'bustype'):
        args.bustype = 'barebone'

    clock = Clock(0, frequency=100e6)
    reset = Reset(0, active=1, async=False)
    glbl = Global(clock, reset)

    # @todo: support all stream types ...
    upstream = AXI4StreamLitePort(data_width=32)
    downstream = AXI4StreamLitePort(data_width=32)

    def _bench_streamer():
        tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
        tbclk = clock.gen()

        dataout = []

        @instance
        def tbstim():
            yield reset.pulse(42)
            downstream.awaccept.next = True
            downstream.waccept.next = True
            data = [randint(0, (2**32)-1) for _ in range(10)]
            for dd in data:
                upstream.awvalid.next = True
                upstream.awdata.next = 0xA
                upstream.wvalid.next = True
                upstream.wdata.next = dd
                yield clock.posedge
            upstream.awvalid.next = False
            upstream.wvalid.next = False

            # @todo: wait the appropriate delay given the number of
            # @todo: streaming registers
            yield delay(100)
            print(data)
            print(dataout)
            assert False not in [di == do for di, do in zip(data, dataout)]
            raise StopSimulation

        @always(clock.posedge)
        def tbcap():
            if downstream.wvalid:
                dataout.append(int(downstream.wdata))

        return tbdut, tbclk, tbstim, tbcap

    run_testbench(_bench_streamer, args=args)

    myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
    if args.keep:
        myhdl.toVerilog.name += '_keep'
    myhdl.toVerilog.directory = 'output'
    myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)

def main():
    control = Signal(alu_code.MAND)
    op1 = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
    op2 = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
    out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
    zero = Signal(bool(False))
    positive = Signal(bool(False))
    toVerilog(ALU, control, op1, op2, out, zero, positive)

def main():
    #unittest.main()

    Rt_ex, Rs_id, Rt_id = [Signal(intbv(0)[5:]) for i in range(3)]

    MemRead_ex, Stall = [Signal(intbv(0)[1:]) for i in range(2)]

    toVerilog(hazard_detector, MemRead_ex, Rt_ex, Rs_id, Rt_id, Stall)

def main():
    #sim = Simulation(testBench())
    #sim.run()
    i_in, pc_in, i_out, pc_out = [Signal(intbv(0)[32:]) for i in range(4)]

    clk, rst, stall = [Signal(intbv(0)[1:]) for i in range(3)]

    toVerilog(latch_if_id, clk, rst, i_in, pc_in, i_out, pc_out, stall)

def convert():

    pins = 10
    t = TristateSignal(intbv(1)[pins:])
    dir = Signal(bool(0))
    wr, rst = [Signal(bool(0)) for i in range(2)]

    toVerilog(ReadWriteFlipFlop, t, dir, wr, rst)
    toVHDL(ReadWriteFlipFlop, t, dir, wr, rst)

def convert():
    Clk = myhdl.Signal(bool(0))
#     Reset = myhdl.ResetSignal(0, active=1, async=True)
    Reset = None
    D = myhdl.Signal(myhdl.intbv(0)[WIDTH_D:])
    Q = myhdl.Signal(myhdl.intbv(0)[WIDTH_Q:])

    myhdl.toVHDL(sumbits, Clk, Reset, D, Q)
    myhdl.toVerilog(sumbits, Clk, Reset, D, Q)

def main():
    #sim = Simulation(testBench_alu_control())
    #sim = Simulation(testBench())
    #sim.run()
    data_in = Signal(intbv(0, min=-(2 ** 15), max=2 ** 15 - 1))

    data_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))

    toVerilog(sign_extend, data_in, data_out)

def emit():
    from myhdl import toVerilog

    clk = Clk(50E6)

    toVerilog(test, clk)

    print
    print open('test.v', 'r').read()

def emit():
    from myhdl import toVerilog

    insts, gen, args = setup()

    toVerilog(gen, *args)

    print
    print open('gen.v', 'r').read()

def main():
    #sim = Simulation(testBench())
    #sim.run(100)
    I0, I1, I2, I3 = [Signal(intbv(random.randint(0, 255))[32:]) for i in range(4)]
    O = Signal(intbv(0)[32:])
    S = Signal(intbv(0, min=0, max=4))

    toVerilog(mux2, S, O, I2, I3)
    toVerilog(mux4, S, O, I0, I1, I2, I3)

def convert(brd, top=None, name=None, use='verilog', path='.'):
    """ Wrapper around the myhdl conversion functions
    This function will use the _fpga objects get_portmap function
    to map the board definition to the 

    Arguments
      top  : top-level myhld module
      brd  : FPGA board definition (_fpga object)
      name : name to use for the generated (converted) file
      use  : User 'verilog' or 'vhdl' for conversion
      path : path of the output files
    """
    assert isinstance(brd, _fpga)

    name = brd.top_name if name is None else name
    pp = brd.get_portmap(top=top)

    # convert with the ports and parameters        
    if use.lower() == 'verilog':
        if name is not None:
            myhdl.toVerilog.name = name
        myhdl.toVerilog(brd.top, **pp)
        brd.name = name
        brd.vfn = "%s.v"%(name)
    elif use.lower() == 'vhdl':
        if name is not None:
            myhdl.toVHDL.name = name
        myhdl.toVHDL(brd.top, **pp)
        brd.name = name
        brd.vfn = "%s.vhd"%(name)
    else:
        raise ValueError("Incorrect conversion target %s"%(use))

    # make sure the working directory exists
    #assert brd.pathexist(brd.path)
    time.sleep(2)

    # copy files etc to the working directory
    tbfn = 'tb_' + brd.vfn
    ver = myhdl.__version__
    # remove special characters from the version
    for sp in ('.', '-', 'dev'):
        ver = ver.replace(sp,'')
    pckfn = 'pck_myhdl_%s.vhd'%(ver)
    for src in (brd.vfn,tbfn,pckfn):
        dst = os.path.join(path, src)
        print('   checking %s'%(dst))
        if os.path.isfile(dst):
            print('   removing %s'%(dst))
            os.remove(dst)
        if os.path.isfile(src):
            print('   moving %s --> %s'%(src, path))
            try:
                shutil.move(src, path)
            except Exception,err:
                print("skipping %s because %s" % (src, err,))

def main():
    #sim = Simulation(testBench_alu_control())
    #sim = Simulation(testBench_alu_control())
    #sim.run()
    aluop = Signal(alu_op_code.MNOP)
    control_out = Signal(alu_code.MADD)
    funct_field = Signal(intbv(0)[6:])
    front_sel = Signal(intbv(0)[1:])
    branch = Signal(intbv(0)[1:])
    toVerilog(alu_control, aluop, branch, funct_field, front_sel, control_out)

def tb_convert(toplevel, *ports, **params):
    if not os.path.isdir('output/ver/'):
        os.makedirs('output/ver/')
    myhdl.toVerilog.directory = 'output/ver/'
    myhdl.toVerilog(toplevel, *ports, **params)

    if not os.path.isdir('output/vhd/'):
        os.makedirs('output/vhd/')
    myhdl.toVHDL.directory = 'output/vhd/'
    myhdl.toVHDL(toplevel, *ports, **params)

def test_ibh(args=None):
    args = tb_default_args(args)
    numbytes = 13

    clock = Clock(0, frequency=50e6)
    glbl = Global(clock, None)
    led = Signal(intbv(0)[8:])
    pmod = Signal(intbv(0)[8:])
    uart_tx = Signal(bool(0))
    uart_rx = Signal(bool(0))
    uart_dtr = Signal(bool(0))
    uart_rts = Signal(bool(0))
    uartmdl = UARTModel()

    def _bench_ibh():
        tbclk = clock.gen()
        tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
        tbdut = icestick_blinky_host(clock, led, pmod, 
                                     uart_tx, uart_rx,
                                     uart_dtr, uart_rts)

        @instance
        def tbstim():
            yield delay(1000)
            
            # send a write that should enable all five LEDs
            pkt = CommandPacket(False, address=0x20, vals=[0xFF])
            for bb in pkt.rawbytes:
                uartmdl.write(bb)
            waitticks = int((1/115200.) / 1e-9) * 10 * 28
            yield delay(waitticks) 
            timeout = 100
            yield delay(waitticks) 
            # get the response packet
            for ii in range(PACKET_LENGTH):
                rb = uartmdl.read()
                while rb is None and timeout > 0:
                    yield clock.posedge
                    rb = uartmdl.read()
                    timeout -= 1
                if rb is None:
                    raise TimeoutError

            # the last byte should be the byte written
            assert rb == 0xFF

            yield delay(1000)
            raise StopSimulation

        return tbclk, tbmdl, tbdut, tbstim

    run_testbench(_bench_ibh, args=args)
    myhdl.toVerilog.directory = 'output'
    myhdl.toVerilog(icestick_blinky_host, clock, led, pmod,
                    uart_tx, uart_rx, uart_dtr, uart_rts)