def bench(self):
        clk = Signal(0)
        sig1 = Signal(0)
        sig2 = Signal(0)
        td = 10

        def gen(s, n):
            for i in range(n-1):
                yield delay(td)
            s.next = 1
            yield delay(td)

        for i in range(10):
            offset = now()
            n0 = randrange(1, 50)
            n1 = randrange(1, 50)
            n2 = randrange(1, 50)
            sig1.next = 0
            sig2.next = 0
            yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
            assert sig1.val == 1
            assert sig2.val == 1
            assert now() == offset + td * max(n0, n1, n2)

        raise StopSimulation("Joined concurrent generator yield")

def assign_config(sig, val):
    keep = Signal(bool(0))
    keep.driven = 'wire'

    @always_comb
    def beh_assign():
        sig.next = val if keep else val
    return beh_assign

 def testValAttrReadOnly(self):
     """ val attribute should not be writable"""
     s1 = Signal(1)
     try:
         s1.val = 1
     except AttributeError:
         pass
     else:
         self.fail()

 def testDrivenAttrValue(self):
     """ driven attribute only accepts value 'reg' or 'wire' """
     s1 = Signal(1)
     try:
         s1.driven = "signal"
     except ValueError:
         pass
     else:
         self.fail()

def get_unsigned_intbv_rand_signal(width, init_value=0):
    '''Create an unsigned intbv random signal.
    '''
    min_val = 0
    max_val = 2**(width)
    signal = Signal(intbv(val=init_value, min=min_val, max=max_val))
    signal.val[:] = randrange(min_val, max_val)

    return signal, min_val, max_val

 def testNegedgeAttrReadOnly(self):
     """ negedge attribute should not be writable"""
     s1 = Signal(1)
     try:
         s1.negedge = 1
     except AttributeError:
         pass
     else:
         self.fail()

 def testSignalBoolBounds(self):
     if type(bool) is not type:  # bool not a type in 2.2
         return
     s = Signal(bool())
     s.next = 1
     s.next = 0
     for v in (-1, -8, 2, 5):
         with pytest.raises(ValueError):
             s.next = v

 def stimulus():
     a = Signal(0)
     yield delay(10)
     a.next = 1
     yield None, delay(10)
     self.assertEqual(a.val, 0)
     self.assertEqual(now(), 10)
     yield delay(0)
     self.assertEqual(a.val, 1)
     self.assertEqual(now(), 10)

 def stimulus():
     a = Signal(0)
     yield delay(10)
     a.next = 1
     yield None, delay(10)
     assert a.val == 0
     assert now() == 10
     yield delay(0)
     assert a.val == 1
     assert now() == 10

    def inst():
        yield delay(200 * nsec)

        addr = Signal(intbv(0x10)[len(bus.A):])

        while 1:
            yield system.CLK.posedge

            bus.CS_B.next = 0
            bus.RAS_B.next = 0
            bus.A.next = 0x4
            bus.BA.next = 0x2

            yield system.CLK.posedge

            bus.CS_B.next = 1
            bus.RAS_B.next = 1
            bus.A.next = ~0 & mask(bus.A)
            bus.BA.next = ~0 & mask(bus.BA)

            yield system.CLK.posedge

            bus.CS_B.next = 0
            bus.CAS_B.next = 0
            bus.A.next = addr
            bus.BA.next = 0

            yield system.CLK.posedge

            bus.CS_B.next = 1
            bus.CAS_B.next = 1
            bus.A.next = ~0 & mask(bus.A)
            bus.BA.next = ~0 & mask(bus.BA)

            addr.next = 0
            if addr != n - 1:
                addr.next = addr + 4

            yield system.CLK.posedge

            bus.CS_B.next = 0
            bus.CAS_B.next = 0
            bus.A.next = addr

            yield system.CLK.posedge

            bus.CS_B.next = 1
            bus.CAS_B.next = 1
            bus.A.next = ~0 & mask(bus.A)

            addr.next = 0
            if addr != n - 1:
                addr.next = addr + 4

            yield delay(interval - 1)

 def test(B, G):
     w = len(B)
     G_Z = Signal(intbv(0)[w:])
     B.next = intbv(0)
     yield delay(10)
     for i in range(1, 2**w):
         G_Z.next = G
         B.next = intbv(i)
         yield delay(10)
         diffcode = bin(G ^ G_Z)
         self.assertEqual(diffcode.count('1'), 1)

        def stimulus():
            N = Signal(intbv(0)[32:])

            yield bus.reset()
            # Send a clear
            yield whitebox_clear(bus)

            # Check the fifo flags
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_SPACE
            assert not (bus.rdata & WES_DATA)

            yield bus.transmit(WE_THRESHOLD_ADDR,
                concat(intbv(1)[16:], intbv(3)[16:]))
            yield bus.receive(WE_THRESHOLD_ADDR)
            assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])

            yield bus.transmit(WE_INTERP_ADDR, INTERP)
            yield bus.receive(WE_INTERP_ADDR)
            assert bus.rdata == INTERP

            ## Insert samples until overrun
            yield bus.receive(WE_RUNS_ADDR)
            while not (bus.rdata & 0x0000ffff):
                x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15), min=-2**15, max=2**15)[16:]
                yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
                N.next = N + 1
                yield bus.receive(WE_RUNS_ADDR)

            # Check that we're full
            yield bus.receive(WE_STATUS_ADDR)
            assert not (bus.rdata & WES_SPACE)
            assert bus.rdata & WES_DATA

            ## Now start transmitting
            yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_TXEN

            ## Wait until underrun
            yield bus.receive(WE_RUNS_ADDR)
            while not (bus.rdata & 0xffff0000):
                yield bus.delay(1000)
                yield bus.receive(WE_RUNS_ADDR)

            ## Make sure we're both over and underrun
            assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff

            # Check the fifo flags
            yield bus.receive(WE_STATUS_ADDR)
            assert bus.rdata & WES_SPACE
            assert not (bus.rdata & WES_DATA)

            raise StopSimulation

def assign_config(sig, val):
    """
    Arguments:
        sig (Signal): The signals to be assigned to a constant value
        val (int): The constant value
    """
    keep = Signal(bool(0))
    keep.driven = 'wire'

    @always_comb
    def beh_assign():
        sig.next = val if keep else val
    return beh_assign

def get_signed_intbv_rand_signal(width, val_range=None, init_value=0):
    '''Create a signed intbv random signal.
    '''
    if val_range is not None:
        min_val = val_range[0]
        max_val = val_range[1]
    else:
        min_val = -(2**(width - 1) - 1)
        max_val = 2**(width - 1)

    signal = Signal(intbv(init_value, min=min_val, max=max_val))
    signal.val[:] = randrange(min_val, max_val)

    return signal, min_val, max_val

 def testSignalBoolBounds(self):
     if type(bool) is not type: # bool not a type in 2.2
         return
     s = Signal(bool())
     s.next = 1
     s.next = 0
     for v in (-1, -8, 2, 5):
         try:
             s.next = v
             #s._update()
             #s.val
         except ValueError:
             pass
         else:
             self.fail()

 def testSliceAssign(self):
     s = Signal(intbv(min=-24, max=34))
     for i in (-24, -2, 13, 33):
         for k in (6, 9, 10):
             s.next[:] = 0
             s.next[k:] = i
             self.assertEqual(s.next, i)
     for i in (-25, -128, 34, 35, 229):
         for k in (0, 9, 10):
             try:
                 s.next[k:] = i
                 # s._update()
             except ValueError:
                 pass
             else:
                 self.fail()
     s = Signal(intbv(5)[8:])
     for v in (0, 2**8-1, 100):
         s.next[:] = v
     for v in (-1, 2**8, -10, 1000):
         try:
             s.next[:] = v
             # s._update()
         except ValueError:
             pass
         else:
             self.fail()

 def testUpdateNoEvent(self):
     """ update without value change should not return event waiters """
     s1 = Signal(1)
     s1.next = 4
     s1._update()
     s1.next = 4
     s1._eventWaiters = self.eventWaiters[:]
     s1._posedgeWaiters = self.posedgeWaiters[:]
     s1._negedgeWaiters = self.negedgeWaiters[:]
     waiters = s1._update()
     self.assertEqual(waiters, [])
     self.assertEqual(s1._eventWaiters, self.eventWaiters)
     self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
     self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)

def assign(a, b):
    """ assign a = b
    """

    if isinstance(b, SignalType):
        @always_comb
        def beh_assign():
            a.next = b
    else:
        # this is a work around for preserving constant assigns
        keep = Signal(True)
        keep.driven = "wire"

        @always_comb
        def beh_assign():
            a.next = b if keep else b

    return beh_assign

 def testUpdatePosedge(self):
     """ update on posedge should return event and posedge waiters """
     s1 = Signal(1)
     s1.next = 0
     s1._update()
     s1.next = 1
     s1._eventWaiters = self.eventWaiters[:]
     s1._posedgeWaiters = self.posedgeWaiters[:]
     s1._negedgeWaiters = self.negedgeWaiters[:]
     waiters = s1._update()
     expected = self.eventWaiters + self.posedgeWaiters
     assert set(waiters) == set(expected)
     assert s1._eventWaiters == []
     assert s1._posedgeWaiters == []
     assert s1._negedgeWaiters == self.negedgeWaiters

 def testUpdateNegedge(self):
     """ update on negedge should return event and negedge waiters """
     s1 = Signal(1)
     s1.next = 1
     s1._update()
     s1.next = 0
     s1._eventWaiters = self.eventWaiters[:]
     s1._posedgeWaiters = self.posedgeWaiters[:]
     s1._negedgeWaiters = self.negedgeWaiters[:]
     waiters = s1._update()
     expected = self.eventWaiters + self.negedgeWaiters
     self.assertEqual(set(waiters), set(expected))
     self.assertEqual(s1._eventWaiters, [])
     self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
     self.assertEqual(s1._negedgeWaiters, [])