/** 
 * @brief Initialize the watchdog timer for a specified timeout
 *
 * It is important to note that this function returns the achieved timeout 
 * for this hardware.  For hardware independence this should be checked when
 * scheduling updates.  Other hardware dependent details may need to be 
 * considered such as a window time which sets a minimum update time, 
 * and this function should return a recommended delay for clearing.  
 *
 * For the STM32 nominal clock rate is 32 khz, but for the maximum clock rate of
 * 60 khz and a prescaler of 4 yields a clock rate of 15 khz.  The delay that is
 * set in the watchdog assumes the nominal clock rate, but the delay for FreeRTOS
 * to use is 75% of the minimal delay.
 *
 * @returns Maximum recommended delay between updates based on PIOS_WATCHDOG_TIMEOUT constant
 */
uint16_t PIOS_WDG_Init()
{
	uint16_t delay = ((uint32_t) PIOS_WATCHDOG_TIMEOUT * 60) / 16;
	if (delay > 0x0fff)
		delay = 0x0fff;
#if defined(PIOS_INCLUDE_WDG)
	DBGMCU_Config(DBGMCU_IWDG_STOP, ENABLE);	// make the watchdog stop counting in debug mode
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetPrescaler(IWDG_Prescaler_16);
	IWDG_SetReload(delay);
	IWDG_ReloadCounter();
	IWDG_Enable();

	// watchdog flags now stored in backup registers
	PWR_BackupAccessCmd(ENABLE);

	wdg_configuration.bootup_flags = RTC_ReadBackupRegister(PIOS_WDG_REGISTER);

	/*
	 * Start from an empty set of registered flags so previous boots
	 * can't influence the current one
	 */
	RTC_WriteBackupRegister(PIOS_WDG_REGISTER, 0);
#endif
	return delay;
}

/**
 * @brief   iwdg config
 */
void IWDG_Configuration(void)
{
	/* Enable write access to IWDG_PR and IWDG_RLR registers */
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	/* IWDG counter clock: LSI/32 */
	IWDG_SetPrescaler(IWDG_Prescaler_32);

	/* Set counter reload value to obtain 250ms IWDG TimeOut.
	 Counter Reload Value = 250ms/IWDG counter clock period
						  = 250ms / (LSI/32)
						  = 0.25s / (LsiFreq/32)
						  = LsiFreq/(32 * 4)
						  = LsiFreq/128
	*/
//	IWDG_SetReload(LSI_FREQ / 128);

	// iwdg period is 1000mS
	IWDG_SetReload(LSI_FREQ / 32);

	/* Reload IWDG counter */
	IWDG_ReloadCounter();

	/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
	IWDG_Enable();

}

//==============================================================================
// 看門狗設定 : 用來當RESET 用
//==============================================================================
void IWDG_Config(unsigned char timeout)
{
  /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
  dispersion) */
  /* Enable write access to IWDG_PR and IWDG_RLR registers */
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
  
  /* IWDG counter clock: LSI/32 */
  //IWDG_SetPrescaler(IWDG_Prescaler_32);
  /* IWDG counter clock: LSI/256 */
  IWDG_SetPrescaler(IWDG_Prescaler_256);
  
  /* Set counter reload value to obtain 250ms IWDG TimeOut.
  Counter Reload Value = 250ms/IWDG counter clock period
  = 250ms / (LSI/32)
  = 0.25s / (LsiFreq/32)
  = LsiFreq/(32 * 4)
  = LsiFreq/128
  */
  // IWDG_SetReload(LsiFreq/128);
  
  IWDG_SetReload(timeout);
  
  /* Reload IWDG counter */
  IWDG_ReloadCounter();
  
  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();
}

void WatchDogInit(void)
{    
  /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
     dispersion) */
  /* Enable write access to IWDG_PR and IWDG_RLR registers */
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

  /* IWDG counter clock: LSI/32 */
    /*   prescaler            min/ms    max/ms
         4                        0.1             409.6
         8                        0.2             819.2
         16                      0.4             1638.4
         32                      0.8              3276.8
         64                      1.6              6553.5
         128                    3.2              13107.2
         256                    6.4              26214.4   
  */
  IWDG_SetPrescaler(IWDG_Prescaler_16);

  /* Set counter reload value to obtain 250ms IWDG TimeOut.
     Counter Reload Value = 250ms/IWDG counter clock period
                          = 250ms / (LSI/32)
                          = 0.25s / (LsiFreq/32)
                          = LsiFreq/(32 * 4)
                          = LsiFreq/128
   */
  IWDG_SetReload(0X4AAA);//(LsiFreq/128);

  /* Reload IWDG counter */
  IWDG_ReloadCounter();

  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();
}

/**
 * Initializes the boards watchdog timer. If the behavior of the board is changed, this method may need to be
 * modified if the main control loop is changed.
 *
 * @param none
 * @retval none
 */
void Watchdog_Init(void) {
	/* Get the LSI frequency from TIM5 */
	LsiFreq = GetLSIFrequency();
	printf("LSI Frequency: %" PRIu32 "\n", LsiFreq);

	/* Enable write access to IWDG_PR and IWDG_RLR registers */
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	/* IWDG counter clock: LSI/32 */
	IWDG_SetPrescaler(IWDG_Prescaler_64);

	/* Set counter reload value to obtain 1s IWDG TimeOut.
	     IWDG counter clock Frequency = LsiFreq/32
	     Counter Reload Value = 250ms/IWDG counter clock period
	                          = 0.25s / (32/LsiFreq)
	                          = LsiFreq/(32 * 4)
	                          = LsiFreq/128
	 */
	IWDG_SetReload(LsiFreq/16);

	/* Reload IWDG counter */
	IWDG_ReloadCounter();

	/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
	IWDG_Enable();
}

void PhotonWdgs::begin(bool _enableWwdg,bool _enableIwdg,unsigned long _timeout, TIMid id)
{
    if(!_enableWwdg && !_enableIwdg) {
        // nothing to do ...
        return;
    }
    PhotonWdgs::_aliveCount = 0;
    PhotonWdgs::_timeoutval = _timeout / 10;

    RCC_LSICmd(ENABLE); //LSI is needed for Watchdogs

    PhotonWdgs::_wdgTimer.begin(PhotonWdgs::_tickleWDGs, 20, hmSec, id);
    // OTA updates won't work with watchdog enabled
    System.disableUpdates();
    PhotonWdgs::_wwdgRunning = _enableWwdg;
    if(_enableWwdg) {
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);
        WWDG_SetPrescaler(WWDG_Prescaler_8);
        WWDG_SetWindowValue(0x7F);
        WWDG_Enable(0x7F);
    }
    PhotonWdgs::_iwdgRunning = _enableIwdg;
    if(_enableIwdg) {
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_SetPrescaler(IWDG_Prescaler_256);
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_SetReload(0xFFF);
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_Enable();
    }
}

/**
  * @brief   Main program
  * @param  None
  * @retval None
  */
int main(void)
{	
	RCC_Configuration();
	GPIO_Configuration();
	USART_Configuration();	
	SysTick_Config(SystemCoreClock/10);
	// Enable the LSI OSC 
 	RCC_LSICmd(ENABLE);
	// Wait till LSI is ready 
	while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {};
	
 	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	// IWDG counter clock: LSI/256 
	IWDG_SetPrescaler(IWDG_Prescaler_256);
	IWDG_SetReload(0x0FFF);
	// Reload IWDG counter 
	IWDG_ReloadCounter();
	// Enable IWDG (the LSI oscillator will be enabled by hardware) 
	IWDG_Enable(); 
	
	// Write memmory
	FLASH_UnlockBank1();
	FLASH_ErasePage(FLAG_ADDR);
	FLASH_ProgramWord(FLAG_ADDR,(u32)FLAG_UPDATED);
	FLASH_LockBank1();
	
	updateFW_control();
}

OSStatus PlatformWDGInitialize( uint32_t timeout_ms )
{
  plat_log_trace();
  OSStatus err = kNoErr;
// PLATFORM_TO_DO

  /* Get the LSI frequency:  TIM5 is used to measure the LSI frequency */
  LsiFreq = GetLSIFrequency();
   
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

  /* IWDG counter clock: LSI/32 */
  IWDG_SetPrescaler(IWDG_Prescaler_128);

  /* Set counter reload value to obtain 250ms IWDG TimeOut.
     Counter Reload Value = 250ms/IWDG counter clock period
                          = 250ms / (LSI/32)
                          = 0.25s / (LsiFreq/32)
                          = LsiFreq/(32 * 4)
                          = LsiFreq/128
   */
  IWDG_SetReload((uint16_t)(LsiFreq*timeout_ms/128000));

  /* Reload IWDG counter */
  IWDG_ReloadCounter();

  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();

  return err;
}

void InitWatchdog(void){
	
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetPrescaler(IWDG_Prescaler_4); 			
	IWDG_SetReload(0xFFF); 
	IWDG_Enable();
}

 //*******************初始化独立看门狗*************************************
//函数定义: void IWDG_Configuration(void) 
//描    述：初始化独立看门狗
//入口参数：无
//出口参数：无
//备    注：分频因子=4*2^prer.但最大值只能是256!时间计算(大概):Tout=40K/((4*2^prer)*rlr)值	 2S超时
//Editor：liuqh 2013-1-16  Company: BXXJS
//*******************************************************************
static void IWDG_Configuration(void) 
{
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);//使能对IWDG->PR和IWDG->RLR的写
	IWDG_SetPrescaler(IWDG_Prescaler_64);//64分频
	IWDG_SetReload(1300);
	IWDG_ReloadCounter();
	IWDG_Enable();		
}

/**
 * IWDG_Configuration
 */
static void IWDG_Configuration(void) 
{
    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
    IWDG_SetPrescaler(IWDG_Prescaler_64);
    IWDG_SetReload(1875);
    IWDG_ReloadCounter();
    IWDG_Enable();
}

void WDT_init(void)
{
	IWDG_WriteAccessEnable();
	IWDG_SetPrescaler(IWDG_Prescaler_256);
	IWDG_SetReload(0xFFF);
	IWDG_Enable();
	IWDG_ReloadCounter();
}

void IWDG_Init()
{
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetPrescaler(IWDG_Prescaler_256);
	IWDG_SetReload(781);
	IWDG_ReloadCounter();
	IWDG_Enable();
}

void watchdog_config(void)
{
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetReload(0x80);
	IWDG_SetPrescaler(IWDG_Prescaler_32);
	IWDG_Enable();
	tim13_config();
}

/**
  * @brief  初始化独立看门狗
  * @param  prer : IWDG预分频值 ,  rlr 重装载值
  * @retval None
  */
void IWDG_Init(u8 prer, u16 rlr)
{
    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);  //使能对寄存器IWDG_PR和IWDG_RLR的写操作
    IWDG_SetPrescaler(prer);  //设置IWDG预分频值:设置IWDG预分频值为64
    IWDG_SetReload(rlr);  //设置IWDG重装载值
    IWDG_ReloadCounter();  //按照IWDG重装载寄存器的值重装载IWDG计数器
    IWDG_Enable();  //使能IWDG
    IWDG_Feed();
}

/*******************************************************************************
* Function Name  : IWDG_Configuration
* Description    : ?/AA?·AaOA
* Input          : None
* Output         : None
* Return         : None
* Attention		 : None
*******************************************************************************/
void IWDG_Configuration(void)
{
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); 	/* ?/Ee0x5555,OAOUOE?i?·?·?A/????/Ee?¦AU */
  IWDG_SetPrescaler(IWDG_Prescaler_256);            /* AU²?µIEUE±OO256·O?µ 40K/256=156HZ(6.4ms) */ 
  /* ?/AA?·¶¨E±??Oc³oE±?a */
  IWDG_SetReload(781);							    /* I??·E±?a 5s/6.4MS=781 .??Oa²»AU/oOU0xfff*/
  IWDG_ReloadCounter();								/* I??·*/
  IWDG_Enable(); 									/* E?AU?/AA?·*/
}

void IWDG_Init(void)
{
  //konfigurowanie watchdoga IWDG
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);    // Zezwolenie na zapis rejestrów IWDG
IWDG_SetPrescaler(IWDG_Prescaler_64);             // IWDG taktowany zegarem: 37kHz/64 = 0.578kHz
IWDG_SetReload(0xFFF);                        // Przepelnienie IWDG po okolo 7s   
IWDG_ReloadCounter();                           // Przeladowanie IWDG
IWDG_Enable();                                  // Wlaczenie IWDG i LSI
}

/*******************************************************************************
函 数 名：void IWDG_Init(void)
功能描述：看门狗初始化						
入口参数：							
返回参数：
创建时间: 2011.6.24
********************************************************************************/
void IWDG_Init(void)
{
    IWDG_WriteAccessCmd( IWDG_WriteAccess_Enable );
    IWDG_SetPrescaler( IWDG_Prescaler_64);	//最小
    IWDG_SetReload( 0x138);		//40KHz内部时钟 (1/40000 * 64 * 0x138 = 0.5s)
    IWDG_WriteAccessCmd( IWDG_WriteAccess_Disable );
    IWDG_Enable();
    IWDG_ReloadCounter();
}

/*!
*	@brief
*	@note
		LSI clock between 30 and 60kHz
		WDTimeOut = 75 ms
		Prescaler = 64
		Tlsi = 1 / (LSI / prescaler) = 1 / (60kHz / 64) = 0.001067
		ReloadValue = WDTimeOut / Tlsi = 75ms / 0.001067 = 70

		this equals the minimum WDG-timeout!
		max. timeout occurs when LSI is @30 kHz (minimum): 2 * 75 ms = 150 ms
*/
void WatchDogInit( void )
{
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	IWDG_SetPrescaler( IWDG_Prescaler_64 );
	IWDG_SetReload(70);// max value 4095 (0xFFF)

	IWDG_Enable();
	IWDG_ReloadCounter();
}

void  main_init( void )
{
  int   sts;
  
  sts = get_reset_reason();
  main_status = MAIN_STS_NO_SNS_ERR;
  main_is_enter_stby_mode = 0;
  
  bio_init();
  clk_init();
  uart_init();
  dbg_wait();
  
#ifdef FEATURE_WDOG_TRIG
  IWDG_Enable();
  bio_led_ctrl( BIO_LED_IX_POWER, 0, 0, 0 );
#else // FEATURE_WDOG_TRIG
  dbg_out( "\r\n**********==> Watchdog Disabled!!!!!\r\n" );
  bio_led_ctrl( BIO_LED_IX_POWER, 500, 500, BIO_LED_ALWAYS_WINK );
#endif  // FEATURE_WDOG_TRIG
  
  dbg_out_pool_const( UART_DBG_MSG_ENTER3 );
  dbg_out( "================== 0x%02X =================\r\n", sts );
  dbg_out( "==== Welcome to %s  Ver %d.%02X ====\r\n",
           MAIN_TIT_STR, MAIN_VER_MAJ, MAIN_VER_MIN );
  dbg_out( "=====   i=%d, si=%d, li=%d, f=%d, d=%d   =====\r\n",
           sizeof( int ), sizeof( short int ),
           sizeof( long  int ),sizeof( float ),sizeof( double ) );
  dbg_out( "=====  %dMHz %s  %s  =====\r\n",
           SystemCoreClock / 1000000, __DATE__, __TIME__ );
  dbg_out_pool_const( UART_DBG_MSG_EQ_LINE );
  dbg_wait();
  
  view_reset_reason( sts );
  eep_param_init();
  IWDG_ReloadCounter();
  
  u3_ctrl.sw_baud = 115200;
  uart3_init();
  sns_init();
  adc_init();
  zb_init();
  encb_init();
  fnd_init();
  indc_init();
  
  bio_set_fan_pwm_base_freq( eep_hw_info.fan_base_f );
  cmd_rx_ptr = u1_ctrl.rx_bptr;
  
  // set monitor timer
  clk_set_timer( &monit_timer, MAIN_MONITOR_MS, MAIN_MONITOR_MS,
                 CLK_SIGS_MONITOR );
  
} // end of main_init()