/*******************************************************************************
* mvAhbToMbusWinRemap - Set CPU remap register for address windows.
*
* DESCRIPTION:
*       After a CPU address hits one of PCI address decode windows there is an
*       option to remap the address to a different one. For example, CPU
*       executes a read from PCI winNum window address 0x1200.0000. This
*       can be modified so the address on the PCI bus would be 0x1400.0000
*       Using the PCI address remap mechanism.
*
* INPUT:
*       winNum      - Peripheral winNum enumerator. Must be a PCI winNum.
*       pAddrDecWin - CPU winNum window information data structure.
*                     Note that caller has to fill in the base field only. The
*                     size field is ignored.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_ERROR if winNum is not a PCI one, MV_OK otherwise.
*
*******************************************************************************/
MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
	MV_U32 baseAddr;
	AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs;
	MV_U32 effectiveBaseAddress = 0, baseAddrValue = 0, windowSizeValue = 0;

	/* Get registers offsets of given winNum                */
	if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs))
		return 0xffffffff;

	/* 1) Set address remap low */
	baseAddr = pAddrWin->baseLow;

	/* BaseLow[31:16] => base register [31:16]              */
	baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK;

	MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr);
	MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh);

	baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum));
	windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum));

	baseAddrValue &= ATMWBR_BASE_MASK;
	windowSizeValue &= ATMWCR_WIN_SIZE_MASK;

	/* Start calculating the effective Base Address */
	effectiveBaseAddress = baseAddrValue;

	/* The effective base address will be combined from the chopped (if any)
	   remap value (according to the size value and remap mechanism) and the
	   window's base address */
	effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow);
	/* If the effectiveBaseAddress exceed the window boundaries return an
	   invalid value. */

	if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) {
		mvOsPrintf("mvAhbToMbusPciRemap: Error\n");
		return 0xffffffff;
	}

	return effectiveBaseAddress;
}

/*******************************************************************************
* mvDmaWinGet - Get dma peripheral target address window.
*
* DESCRIPTION:
*		Get IDMA peripheral target address window.
*
* INPUT:
*       winNum - IDMA to target address decode window number.
*
* OUTPUT:
*       pAddrDecWin - IDMA target window data structure.
*
* RETURN:
*       MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvDmaWinGet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin)
{

	MV_DEC_REGS decRegs;
	MV_TARGET_ATTRIB targetAttrib;

	/* Parameter checking   */
	if (winNum >= IDMA_MAX_ADDR_DEC_WIN)
	{
		mvOsPrintf("mvDmaWinGet: ERR. Invalid winNum %d\n", winNum);
		return MV_NOT_SUPPORTED;
	}
	
	decRegs.baseReg =  MV_REG_READ(IDMA_BASE_ADDR_REG(winNum));                                                                           
	decRegs.sizeReg = MV_REG_READ(IDMA_SIZE_REG(winNum));
 
	if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
	{
		mvOsPrintf("mvDmaWinGet: mvCtrlRegToAddrDec Failed \n");
		return MV_ERROR;
	}
	 
	/* attrib and targetId */
	targetAttrib.attrib = 
		(decRegs.baseReg & IDMA_WIN_ATTR_MASK) >> IDMA_WIN_ATTR_OFFS;
	targetAttrib.targetId = 
		(decRegs.baseReg & IDMA_WIN_TARGET_MASK) >> IDMA_WIN_TARGET_OFFS;
	 
	pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
	
	/* Check if window is enabled   */
	if (~(MV_REG_READ(IDMA_BASE_ADDR_ENABLE_REG)) & (IBAER_ENABLE(winNum)))
	{
		pAddrDecWin->enable = MV_TRUE;
	}
	else
	{
		pAddrDecWin->enable = MV_FALSE;
	}
	
	return MV_OK;
}

/*******************************************************************************
* mvGppValueGet - Get a GPP Pin list value.
*
* DESCRIPTION:
*       This function get GPP value.
*
* INPUT:
*       group - GPP group number
*       mask  - 32bit mask value. Each set bit in the mask means that the 
*               returned value is valid for it.
*
* OUTPUT:
*       None.
*
* EXAMPLE:
*       Get GPP8 and GPP15 value.
*       mvGppValueGet(0, (GPP8 | GPP15));
*
* RETURN:
*       32bit value that describes GPP activity mode per pin.
*
*******************************************************************************/
MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask)
{
	MV_U32 gppData;

	gppData = MV_REG_READ(GPP_DATA_IN_REG(group));

	gppData &= mask;

	return gppData;

}

/*******************************************************************************
 * mvNetaHwfMhSelSet - Set MH value on TX during HWF.
 *
 * DESCRIPTION:
 *
 * INPUT:
 *       int        port;		port number
 *       int        mh_sel_nask;	use the following values as mask
 *					NETA_MH_DONT_CHANGE
 *					NETA_MH_REPLACE_GPON_HDR
 *					NETA_MH_REPLACE_MH_REG(r)
 * RETURN:   MV_STATUS
 *               MV_OK - Success, Others - Failure
 *
 * NOTE:
 *******************************************************************************/
MV_STATUS mvNetaHwfMhSelSet(int port, MV_U8 mh_sel_mask)
{
	MV_U32	regVal;

	regVal = MV_REG_READ(NETA_HWF_RX_CTRL_REG(port));
	regVal &= ~NETA_MH_SEL_MASK;
	regVal |= (mh_sel_mask & NETA_MH_SEL_MASK);

	MV_REG_WRITE(NETA_HWF_RX_CTRL_REG(port), regVal);
	return MV_OK;
}

/*******************************************************************************
* mvSysTwsiMainCauseIsSet
*
* DESCRIPTION:
*	Check if the TWSI interrupt was triggered in the main interrupt cause 
*	register.
*
* INPUT:
*	chanNum	- TWSI channel number.
*
* OUTPUT:
*	None.
*
* RETURN:
*	MV_TRUE if interrupt was triggered.
*	MV_FALSE otherwise.
*
*******************************************************************************/
MV_BOOL mvSysTwsiMainCauseIsSet(MV_U32 chanNum)
{
	MV_U32 val;

	val = MV_REG_READ(MV_TWSI_CPU_MAIN_INT_CAUSE(chanNum));

	if (val & (1 << CPU_MAIN_INT_TWSI_OFFS(chanNum)))
		return MV_TRUE;

	return MV_FALSE;
}

/*******************************************************************************
* mvSdmmcWinInit - Initialize the integrated SDMMC target address window.
*
* DESCRIPTION:
*       Initialize the SDMMC peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*
*
* RETURN:
*       MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSdmmcWinInit(MV_VOID)
{
    int             winNum;
    MV_SDMMC_DEC_WIN  sdmmcWin;
    MV_CPU_DEC_WIN  cpuAddrDecWin;
    MV_U32          status, winPrioIndex = 0;

    /* Initiate Sdmmc address decode */

    /* First disable all address decode windows */
    for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++)
    {
        MV_U32  regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum));
        regVal &= ~MV_SDMMC_WIN_ENABLE_MASK;
        MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal);
    }

    winNum = 0;
    while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
           (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) )
    {
        /* first get attributes from CPU If */
        status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex],
                                     &cpuAddrDecWin);

        if(MV_NO_SUCH == status)
        {
            winPrioIndex++;
            continue;
        }
	if (MV_OK != status)
	{
            mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
	    return MV_ERROR;
	}

        if (cpuAddrDecWin.enable == MV_TRUE)
        {
            sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
            sdmmcWin.addrWin.baseLow  = cpuAddrDecWin.addrWin.baseLow;
            sdmmcWin.addrWin.size     = cpuAddrDecWin.addrWin.size;
            sdmmcWin.enable           = MV_TRUE;
            sdmmcWin.target           = sdmmcAddrDecPrioTab[winPrioIndex];

            if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin))
            {
                return MV_ERROR;
            }
            winNum++;
        }
        winPrioIndex++;
    }
    return MV_OK;
}

/*******************************************************************************
* mvCamSDIOWinRead - Get CAM_SDIO peripheral target address window.
*
* DESCRIPTION:
*       Get CAM_SDIO peripheral target address window.
*
* INPUT:
*       winNum - CAM_SDIO target address decode window number.
*
* OUTPUT:
*       pAddrDecWin - CAM_SDIO target window data structure.
*
* RETURN:
*       MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvCamSDIOWinRead(MV_U32 winNum, MV_UNIT_WIN_INFO *pAddrDecWin)
{
    MV_U32  baseReg, sizeReg;
    MV_U32  sizeRegVal;
                                                                                                                         
    /* Parameter checking   */
    if (winNum >= MV_CAM_SDIO_MAX_ADDR_DECODE_WIN)
    {
        mvOsPrintf("%s : ERR. Invalid winNum %d\n", 
                    __FUNCTION__, winNum);
        return MV_NOT_SUPPORTED;
    }

    baseReg = MV_REG_READ( MV_CAM_SDIO_WIN_BASE_REG(winNum) );
    sizeReg = MV_REG_READ( MV_CAM_SDIO_WIN_CTRL_REG(winNum) );

    sizeRegVal = (sizeReg & MV_CAM_SDIO_WIN_SIZE_MASK) >> 
	MV_CAM_SDIO_WIN_SIZE_OFFSET;
    pAddrDecWin->addrWin.size = (sizeRegVal + 1) * MV_CAM_SDIO_WIN_SIZE_ALIGN;

    /* Extract base address						*/
    pAddrDecWin->addrWin.baseLow = baseReg & MV_CAM_SDIO_WIN_BASE_MASK;
    pAddrDecWin->addrWin.baseHigh =  0;

    /* attrib and targetId */
    pAddrDecWin->attrib = (sizeReg & MV_CAM_SDIO_WIN_ATTR_MASK) >> 
		MV_CAM_SDIO_WIN_ATTR_OFFSET;
    pAddrDecWin->targetId = (sizeReg & MV_CAM_SDIO_WIN_TARGET_MASK) >> 
		MV_CAM_SDIO_WIN_TARGET_OFFSET;
 
    /* Check if window is enabled   */
    if(sizeReg & MV_CAM_SDIO_WIN_ENABLE_MASK) 
    {
        pAddrDecWin->enable = MV_TRUE;
    }
    else
    {
        pAddrDecWin->enable = MV_FALSE;
    }
    return MV_OK;
}

/*******************************************************************************
* mvSdmmcWinGet - Get SDMMC peripheral target address window.
*
* DESCRIPTION:
*       Get SDMMC peripheral target address window.
*
* INPUT:
*       winNum - SDMMC target address decode window number.
*d
* OUTPUT:
*       pAddrDecWin - SDMMC target window data structure.
*
* RETURN:
*       MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin)
{
    MV_DEC_REGS         decRegs;
    MV_TARGET_ATTRIB    targetAttrib;

    /* Parameter checking   */
    if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN)
    {
        mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
                    __FUNCTION__, dev, winNum);
        return MV_NOT_SUPPORTED;
    }

    decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) );
    decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) );

    if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
    {
        mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
        return MV_ERROR;
    }

    /* attrib and targetId */
    targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >>
		MV_SDMMC_WIN_ATTR_OFFSET;
    targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >>
		MV_SDMMC_WIN_TARGET_OFFSET;

    pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);

    /* Check if window is enabled   */
    if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK)
    {
        pAddrDecWin->enable = MV_TRUE;
    }
    else
    {
        pAddrDecWin->enable = MV_FALSE;
    }
    return MV_OK;
}

/*******************************************************************************
* mvSysTwsiMainCauseIsSet
*
* DESCRIPTION:
*	Check if the TWSI interrupt was triggered in the main interrupt cause
*	register.
*
* INPUT:
*	chanNum	- TWSI channel number.
*
* OUTPUT:
*	None.
*
* RETURN:
*	MV_TRUE if interrupt was triggered.
*	MV_FALSE otherwise.
*
*******************************************************************************/
MV_BOOL mvSysTwsiMainCauseIsSet(MV_U32 chanNum)
{
	MV_U32 val;

	/* Pass dummy 0 to keep compatibility with HAL */
	val = MV_REG_READ(MV_TWSI_CPU_MAIN_INT_CAUSE(chanNum, 0));

	if (val & (1 << CPU_MAIN_INT_TWSI_OFFS(chanNum)))
		return MV_TRUE;

	return MV_FALSE;
}

/*******************************************************************************
* mvXorCtrlSet - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*       None.
*
* RETURN:
*       GT_BAD_PARAM if parameters to function invalid, GT_OK otherwise.
* NOTE:
*    This function does not modify the OperationMode field of control register.
*
*******************************************************************************/
GT_STATUS mvXorCtrlSet(GT_U32 chan, GT_U32 xorCtrl)
{
	GT_U32 oldValue;

	/* update the XOR Engine [0..1] Configuration Registers (XExCR) */
	oldValue = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)))
	    & XEXCR_OPERATION_MODE_MASK;
	xorCtrl &= ~XEXCR_OPERATION_MODE_MASK;
	xorCtrl |= oldValue;
	MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xorCtrl);
	return GT_OK;
}

MV_STATUS mvTdmSpiWrite(MV_U32 val1, MV_U32 val2, MV_U32 cmd, MV_U8 cs)
{
	/*MV_TRC_REC("%s: cs = %d val1 = 0x%x val2 = 0x%x\n",__FUNCTION__,cs, val1, val2);*/

	/* Poll for ready indication */
	while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE);

	mvTdmSetCurrentUnit(cs);
	
	MV_REG_WRITE(SPI_CODEC_CMD_LO_REG, val1);
	MV_REG_WRITE(SPI_CODEC_CMD_HI_REG, val2);
	MV_REG_WRITE(SPI_CODEC_CTRL_REG, cmd);

	/* Activate */
	MV_REG_WRITE(SPI_CTRL_REG, MV_REG_READ(SPI_CTRL_REG) | SPI_ACTIVE);

	/* Poll for ready indication */
	while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE);

	return MV_OK;
}

/*******************************************************************************
* gppRegSet - Set a specific GPP pin on a specific GPP register
*
* DESCRIPTION:
*       This function set a specific GPP pin on a specific GPP register
*
* INPUT:
*		regOffs - GPP Register offset 
*       group - GPP group number
*       mask  - 32bit mask value. Each set bit in the mask means that the 
*               value of corresponding GPP will be set accordingly. Other GPP 
*               are not affected.
*       value - 32bit value that describes GPP value per pin.
*
* OUTPUT:
*       None.
*
* EXAMPLE:
*       Set GPP8 value of '0' and GPP15 value of '1'.
*       mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) );
*
* RETURN:
*       None.
*
*******************************************************************************/
static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value)
{
	MV_U32 gppData;

	gppData = MV_REG_READ(regOffs);

	gppData &= ~mask;

	gppData |= (value & mask);

	MV_REG_WRITE(regOffs, gppData);
}

MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value)
{

	MV_U32 regAddr;
	if (pexIf >= pexHalData[pexIf].maxPexIf) {
		mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf);
		return;
	}
	regAddr = (BIT31 | ((regOffset & 0x3fff) << 16));
	MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr);
	*value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf));
}

/*******************************************************************************
* twsiInit - Initialize TWSI interface
*
* DESCRIPTION:
*       This routine:
*   -Reset the TWSI.
*   -Initialize the TWSI clock baud rate according to given frequancy
*    parameter based on Tclk frequancy and enables TWSI slave.
*       -Set the ack bit.
*   -Assign the TWSI slave address according to the TWSI address Type.
*
* INPUT:
*   chanNum - TWSI channel
*       frequancy - TWSI frequancy in KHz. (up to 100KHZ)
*
* OUTPUT:
*       None.
*
* RETURN:
*       Actual frequancy.
*
*******************************************************************************/
MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable)
{
	MV_U32 n, m, freq, margin, minMargin = 0xffffffff;
	MV_U32 power;
	MV_U32 actualFreq = 0, actualN = 0, actualM = 0, val;

#ifdef MV88F67XX
	/* set twsi MPPS */
	val = (MV_REG_READ(REG_MPP_CONTROL_ADDR) | (REG_MPP_CONTROL_TWSI_VALUE << REG_MPP_CONTROL_TWSI_OFFS));
	MV_REG_WRITE(REG_MPP_CONTROL_ADDR, val);
#endif

	/* Calucalte N and M for the TWSI clock baud rate */
	for (n = 0; n < 8; n++) {
		for (m = 0; m < 16; m++) {
			power = 2 << n;	/* power = 2^(n+1) */
			freq = Tclk / (10 * (m + 1) * power);
			margin = MV_ABS(frequancy - freq);

			if ((freq <= frequancy) && (margin < minMargin)) {
				minMargin = margin;
				actualFreq = freq;
				actualN = n;
				actualM = m;
			}
		}
	}
	/* Reset the TWSI logic */
	twsiReset(chanNum);

	/* Set the baud rate */
	val = ((actualM << TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS);
	MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum), val);

	/* Enable the TWSI and slave */
	MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK);

	/* set the TWSI slave address */
	if (pTwsiAddr->type == ADDR10_BIT) {	/* 10 Bit deviceAddress */
		/* writing the 2 most significant bits of the 10 bit address */
		val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS);
		/* bits 7:3 must be 0x11110 */
		val |= TWSI_SLAVE_ADDR_10BIT_CONST;
		/* set GCE bit */
		if (generalCallEnable)
			val |= TWSI_SLAVE_ADDR_GCE_ENA;
		/* write slave address */
		MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val);

		/* writing the 8 least significant bits of the 10 bit address */
		val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK;
		MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val);
	} else {		/*7 bit address */

/*******************************************************************************
* twsiMainIntGet - Get twsi bit from main Interrupt cause.
*
* DESCRIPTION:
*       This routine returns the twsi interrupt flag value.
*
* INPUT:
*       None.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_TRUE is interrupt flag is set, MV_FALSE otherwise.
*
*******************************************************************************/
static MV_BOOL twsiMainIntGet(MV_U8 chanNum)
{
	MV_U32 temp;

	/* get the int flag bit */

	temp = MV_REG_READ(MV_TWSI_CPU_MAIN_INT_CAUSE(chanNum));
	if (temp & (1<<CPU_MAIN_INT_TWSI_OFFS(chanNum))) /*    (TWSI_CPU_MAIN_INT_BIT(chanNum))) */
		return MV_TRUE;

	return MV_FALSE;
}

static void mvEthPortSgmiiSet(int port, int enable)
{
	MV_U32 regVal;

	regVal = MV_REG_READ(ETH_GMAC_CTRL_2_REG(port));
	if (enable)
		regVal |= ETH_GMAC_PCS_ENABLE_MASK;
	else
		regVal &= ~ETH_GMAC_PCS_ENABLE_MASK;

	mvPp2WrReg(ETH_GMAC_CTRL_2_REG(port), regVal);
}

/*******************************************************************************
* mvPexModeGet - Get Pex Mode
*
* DESCRIPTION:
*
* INPUT:
*       pexIf   - PEX interface number.
*
* OUTPUT:
*       pexMode - Pex mode structure
*
* RETURN:
*       MV_OK on success , MV_ERROR otherwise
*
*******************************************************************************/
MV_U32 mvPexModeGet(MV_U32 pexIf, MV_PEX_MODE *pexMode)
{
	MV_U32 pexData;

	if (pexIf >= MV_PEX_MAX_IF)
		return MV_BAD_PARAM;

	
	pexData = MV_REG_READ(PEX_CTRL_REG(pexIf));

	switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) {
	case PXCR_DEV_TYPE_CTRL_CMPLX:
		pexMode->pexType = MV_PEX_ROOT_COMPLEX;
		break;
	case PXCR_DEV_TYPE_CTRL_POINT:
		pexMode->pexType = MV_PEX_END_POINT;
		break;

	}

	/* Check if we have link */
/*	if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) { */

	if ((MV_REG_READ(PEX_DBG_STATUS_REG(pexIf)) & 0x7f) != 0x7E) {

		pexMode->pexLinkUp = MV_FALSE;

		/* If there is no link, the auto negotiation data is worthless */
		pexMode->pexWidth = MV_PEX_WITDH_INVALID;
	}
	else { /* We have Link negotiation started */
			pexMode->pexLinkUp = MV_TRUE;
		/* We have link. The link width is now valid */
		pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG));
		pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> PXLCSR_NEG_LNK_WDTH_OFFS);
		pexMode->pexGen = ((pexData & PXLCSR_NEG_LNK_GEN_MASK) >> PXLCSR_NEG_LNK_GEN_OFFS);
	}

	return MV_OK;
}

/*******************************************************************************
* mvTwsiStartBitSet - Set start bit on the bus
*
* DESCRIPTION:
*       This routine sets the start bit on the TWSI bus.
*       The routine first checks for interrupt flag condition, then it sets
*       the start bit  in the TWSI Control register.
*       If the interrupt flag condition check previously was set, the function
*       will clear it.
*       The function then wait for the start bit to be cleared by the HW.
*       Then it waits for the interrupt flag to be set and eventually, the
*       TWSI status is checked to be 0x8 or 0x10(repeated start bit).
*
* INPUT:
*       chanNum - TWSI channel.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_OK is start bit was set successfuly on the bus.
*       MV_FAIL if interrupt flag was set before setting start bit.
*
*******************************************************************************/
MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum)
{
	MV_BOOL isIntFlag = MV_FALSE;
	MV_U32 timeout, temp;

	/* check Int flag */
	if (twsiMainIntGet(chanNum))
		isIntFlag = MV_TRUE;

	/* set start Bit */
	temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
	MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT);

	/* in case that the int flag was set before i.e. repeated start bit */
	if (isIntFlag)
		twsiIntFlgClr(chanNum);

	/* wait for interrupt */
	timeout = 0;
	while (!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE))
		;

	/* check for timeout */
	if (MV_TRUE == twsiTimeoutChk(timeout, "TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n"))
		return MV_TIMEOUT;

	/* check that start bit went down */
	if ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0)
		return MV_FAIL;

	/* check the status */
	temp = twsiStsGet(chanNum);
	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == temp) ||
		(TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == temp))
		return MV_TWSI_RETRY;
	else if ((temp != TWSI_START_CON_TRA) && (temp != TWSI_REPEATED_START_CON_TRA))
		return MV_FAIL;

	return MV_OK;
}

/*******************************************************************************
* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register.
*
* DESCRIPTION:
*
* INPUT:
*       group - GPP group number
*       mask  - 32bit mask value. Each set bit in the mask means that the 
*               returned value is valid for it.
*
* OUTPUT:
*       None.
*
* EXAMPLE:
*       Get GPP8 and GPP15 value.
*       mvGppPolarityGet(0, (GPP8 | GPP15));
*
* RETURN:
*       32bit value that describes GPP polatity mode per pin.
*
*******************************************************************************/
MV_U32  mvGppPolarityGet(MV_U32 group, MV_U32 mask)
{
    MV_U32  regVal;

  	if (group >= MV_GPP_MAX_GROUP)
	{
		DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n"));
		return MV_ERROR;
	}
    regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group));
    
    return (regVal & mask);
}

unsigned int wait_for_idma(MV_U32   channel)
{
	u32 timeout = 0;

	/* wait for completion */
        while( mvDmaStateGet(channel) != MV_IDLE )
	{
		DPRINTK(" ctrl low is %x \n", MV_REG_READ(IDMA_CTRL_LOW_REG(channel)));
		//udelay(1);
#ifdef RT_DEBUG
                dma_wait_loops++; 
#endif
		if(timeout++ > CPY_DMA_TIMEOUT)
                {
		    printk("dma_copy: IDMA %d timed out , ctrl low is %x \n",
                    channel, MV_REG_READ(IDMA_CTRL_LOW_REG(channel)));
                    return 1;
                }		
	}
	DPRINTK("IDMA complete in %x \n", timeout);
	return 0;
}