void xor_waiton_eng(int chan)
{
    int timeout = 0;
    if(!xor_channel[chan].chan_active)
	return;
    
    while(!(MV_REG_READ(XOR_CAUSE_REG) & XOR_CAUSE_DONE_MASK(chan))) 
    {
	if(timeout > XOR_TIMEOUT)
	    goto timeout; 
	timeout++;
    }

    timeout = 0;
    while(mvXorStateGet(chan) != MV_IDLE)
    {
	if(timeout > XOR_TIMEOUT)
	    goto timeout; 
	timeout++;
    }
    /* Clear int */
    MV_REG_WRITE(XOR_CAUSE_REG, ~(XOR_CAUSE_DONE_MASK(chan)));
    xor_channel[chan].chan_active = 0;

timeout:
    if(timeout > XOR_TIMEOUT)
    {
	printk("ERR: XOR eng got timedout!!\n");
	BUG();
    }
    return;

}

/*******************************************************************************
* mvDmaMemInit - Initialize a memory buffer with a given 64bit value pattern
* 
* DESCRIPTION:       
*       This function initiates IDMA channel, according to function parameters,
*       in order to perform DMA transaction for the purpose of initializing a 
*       memory buffer with a user supplied pattern.
*       This routine supports both chain and none chained DMA modes. 
*       To use the function in chain mode just set phyNextDesc parameter with
*       chain second descriptor address (the first one is given in other 
*       function paarameters). Otherwise (none chain mode) set it to NULL.
*       To gain maximum performance the user is asked to keep the following 
*       restrictions:
*       1) Selected engine is available (not busy).
*       1) This module does not take into consideration CPU MMU issues.
*          In order for the IDMA engine to access the appropreate source 
*          and destination, address parameters must be given in system 
*          physical mode.
*       2) This API does not take care of cache coherency issues. The source,
*          destination and in case of chain the descriptor list are assumed
*          to be cache coherent.
*       3) No chain mode support.
*       4) Parameters validity. For example, does size parameter exceeds 
*          maximum byte count of descriptor mode (16M or 64K).
*
* INPUT:
*       chan          - DMA channel number. See MV_DMA_CHANNEL enumerator.
*       ptrnPtr       - Physical source address of the 64bit pattern
*       startPtr      - Physical destinaation address to start with
*       size          - The total number of bytes to transfer.
*
* OUTPUT:
*       None.
*
* RETURS:
*       MV_OK.
*
*******************************************************************************/
MV_STATUS mvDmaMemInit(MV_U32 chan, MV_U32 ptrnPtr, MV_U32 startPtr, MV_U32 size)
{   
	/* Set byte count register			*/
	MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size);
	/* Set source address register		*/
	MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), ptrnPtr);
	/* Set destination address register	*/
	MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), startPtr);
	/* Lock the Source address in dma operation */
	MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD);
	
	/* Start DMA	*/
	MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE);
	
    return MV_OK;
}

/*******************************************************************************
* mvDmaProtWinSet - Set access protection of IDMA to target window.
*
* DESCRIPTION:
*       Each IDMA channel can be configured with access attributes for each 
*       of the IDMA to target windows (address decode windows). This
*       function sets access attributes to a given window for the given channel.
*
* INPUTS:
*       chan   - IDMA channel number. See MV_DMA_CHANNEL enumerator.
*       winNum - IDMA to target address decode window number.
*       access - IDMA access rights. See MV_ACCESS_RIGHTS enumerator.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_ERROR in case window number is invalid or access right reserved.
*
*******************************************************************************/
MV_STATUS mvDmaProtWinSet (MV_U32 chan, MV_U32 winNum, MV_ACCESS_RIGHTS access)
{    
    MV_U32 protReg;

    /* Parameter checking   */
    if ((chan >= MV_IDMA_MAX_CHAN) || (winNum >= IDMA_MAX_ADDR_DEC_WIN))
    {
		mvOsPrintf("mvDmaProtWinSet:ERR. Invalid chan number %d\n", chan);
        return MV_ERROR;
    }
	if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS))
	{
		mvOsPrintf("mvDmaProtWinSet:ERR. Inv access param %d\n", access);
        return MV_ERROR;
	}
    /* Read current protection register */
    protReg = MV_REG_READ(IDMA_ACCESS_PROTECT_REG(chan));
    
    /* Clear protection window field */
    protReg &= ~(ICAPR_PROT_WIN_MASK(winNum));

    /* Set new protection field value */
    protReg |= (access << (ICAPR_PROT_WIN_OFFS(winNum)));
    
    /* Write protection register back   */
    MV_REG_WRITE(IDMA_ACCESS_PROTECT_REG(chan), protReg);

	return MV_OK;
}               

/*******************************************************************************
* mvCntmrCtrlSet -
*
* DESCRIPTION:
*  	Set the Control to a given counter/timer
*
* INPUT:
*       countNum - counter number
*		pCtrl - pointer to MV_CNTMR_CTRL structure
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
*******************************************************************************/
MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl)
{
	MV_U32 cntmrCtrl;

	if (countNum >= MV_CNTMR_MAX_COUNTER) {
		DB(mvOsPrintf(("mvCntmrCtrlSet: Err. illegal counter number \n")));
		return MV_BAD_PARAM;;
	}

	/* read control register */
	cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(countNum));
	cntmrCtrl &= ~((CTCR_ARM_TIMER_EN_MASK(countNum)) | (CTCR_ARM_TIMER_AUTO_MASK(countNum)));

	if (pCtrl->enable)	/* enable counter\timer */
		cntmrCtrl |= (CTCR_ARM_TIMER_EN(countNum));

	if (pCtrl->autoEnable)	/* Auto mode */
		cntmrCtrl |= (CTCR_ARM_TIMER_AUTO_EN(countNum));

#ifndef MV88F78X60_Z1
	cntmrCtrl &= ~((CTCR_ARM_TIMER_RATIO_MASK(countNum)) | (CTCR_ARM_TIMER_25MhzFRQ_MASK(countNum)));

	cntmrCtrl |= (pCtrl->Ratio & 0x7) << (CTCR_ARM_TIMER_RATIO_OFFS(countNum));

	if (pCtrl->enable_25Mhz)	/* 25Mhz enable */
		cntmrCtrl |= (CTCR_ARM_TIMER_25MhzFRQ_EN(countNum));

#endif


	MV_REG_WRITE(CNTMR_CTRL_REG(countNum), cntmrCtrl);

	return MV_OK;

}

/*
 * cesa Interrupt polling routine.
 */
static irqreturn_t
cesa_interrupt_handler(int irq, void *arg)
{
        u32                  	cause;

	dprintk("%s()\n", __FUNCTION__);

	cesaTestTraceAdd(0);

  	/* Read cause register */
	cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG);

    	if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0)
    	{
        /* Empty interrupt */
		dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause);
        	return IRQ_HANDLED;
    	}
	
	/* clear interrupts */
    	MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0);

	cesaTestTraceAdd(1);
#ifdef CESA_OCF_TASKLET	
	tasklet_hi_schedule(&cesa_ocf_tasklet);
#else
	cesa_callback(0);
#endif
	return IRQ_HANDLED;
}

/*******************************************************************************
* mvAc97FifoDataWrite16
*
* DESCRIPTION:
*       Write the given amount of 16-bit samples to one of the Tx FIFOs.
*	This function is relevant only when the unit is configured in PIO mode.
*	It's the user's responsibility to make sure that there are enough 
*	place in the Tx fifo before calling this function.
*
* INPUT:
*	fifoType- The Fifo type to write to.
*       data	- A buffer holding the data to be written.
*	length	- Amount of 16-bit samples to write.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_OK	- On successfull init,
*	MV_BAD_PARAM - Cannot perform a write operation to the given Fifo.
*	MV_NOT_SUPPORTED - Requested access width not supported on the given Fifo.
*	MV_FAIL	- If initialization fails.
*******************************************************************************/
static MV_STATUS mvAc97FifoDataWrite16(MV_AC97_FIFO_TYPE fifoType, MV_U16 *data, MV_U16 length)
{
	MV_U32	regAddr;
	MV_U32	regData;
	MV_U32	i;

	if((data == NULL) || (length == 0))
	   return MV_BAD_PARAM;

	switch (fifoType) {
	case (AC97_MODEM_OUT):
		regAddr = MV_AC97_MODEM_DATA_REG;
		break;
	case (AC97_PCM_IN):
	case (AC97_MIC_IN):
	case (AC97_MODEM_IN):
		return MV_BAD_PARAM;
	case (AC97_PCM_OUT):
	case (AC97_PCM_CENTER_LFE_OUT):
	case (AC97_PCM_SURROUND_OUT):
		return MV_NOT_SUPPORTED;
	}

	for(i = 0; i < length; i++) {
		regData = (MV_U32)data[i];
		MV_REG_WRITE(regAddr,regData);
	}
	return MV_OK;
}

/*******************************************************************************
**
**  onuPonTxPowerControlInit
**  ____________________________________________________________________________
**
**  DESCRIPTION: The function initialyzes TX power control pins
**
**  PARAMETERS:  None
**
**  OUTPUTS:     None
**
**  RETURNS:     MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonTxPowerControlInit(void)
{
	MV_U32		gpioPinNum, gpioGroup, gpioMask;
	MV_U32		regVal, mppGroup;
	MV_GPP_HAL_DATA	halData;
	MV_U32		devId = mvCtrlModelGet();
	MV_STATUS	status = MV_OK;

	gpioPinNum = mvBoarGpioPinNumGet(BOARD_GPP_PON_XVR_TX_POWER, 0);
	if (gpioPinNum != MV_ERROR) {
		mppGroup = mvCtrlMppRegGet(gpioPinNum / 8);
		/* Set TX power MPP to GPP mode */
		regVal = MV_REG_READ(mppGroup);
		regVal &= ~(0xf << ((gpioPinNum % 8) * 4));
		MV_REG_WRITE(mppGroup, regVal);

		halData.ctrlRev = mvCtrlRevGet();

		status = mvGppInit(&halData);
		if (status == MV_OK) {
			/* Set TX power GPP pin direction to OUT */
			gpioGroup = gpioPinNum / 32;
			gpioMask = 1 << gpioPinNum;
			status = mvGppTypeSet(gpioGroup, gpioMask, (MV_GPP_OUT & gpioMask));
		}

	} else if (devId == MV_6601_DEV_ID)
		status = MV_ERROR;

	return(status);
}

/*******************************************************************************
* mvPexLocalDevNumSet - Set PEX interface local device number.
*
* DESCRIPTION:
*       This function sets given PEX interface its local device number.
*       Note: In case the PEX interface is PEX-X, the information is read-only.
*
* INPUT:
*       pexIf  - PEX interface number.
*       devNum - Device number.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_NOT_ALLOWED in case PEX interface is PEX-X.
*		MV_BAD_PARAM on bad parameters ,
*       otherwise MV_OK
*
*******************************************************************************/
MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum)
{
	MV_U32 pexStatus;

	if (pexIf >= MV_PEX_MAX_IF)
		return MV_BAD_PARAM;

	/* Parameter checking   */
	if (pexIf >= pexHalData[pexIf].maxPexIf) {
		mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n", pexIf);
		return MV_BAD_PARAM;
	}
	if (devNum >= MAX_PEX_DEVICES) {
		mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", devNum);
		return MV_BAD_PARAM;
	}

	pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf));

	pexStatus &= ~PXSR_PEX_DEV_NUM_MASK;

	pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;

	MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus);

	return MV_OK;
}

/* SPDIF Recording Related*/
MV_STATUS	mvSPDIFRecordTclockSet()
{
	MV_U32 tclock = mvBoardTclkGet();
	MV_U32 reg = MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG);

	reg &= ~ASRGR_CORE_CLK_FREQ_MASK;

	switch (tclock)
	{
	case MV_BOARD_TCLK_133MHZ:
		reg |= ASRGR_CORE_CLK_FREQ_133MHZ;
		break;
	case MV_BOARD_TCLK_150MHZ:
		reg |= ASRGR_CORE_CLK_FREQ_150MHZ;
		break;
	case MV_BOARD_TCLK_166MHZ:
		reg |= ASRGR_CORE_CLK_FREQ_166MHZ;
		break;
	case MV_BOARD_TCLK_200MHZ:
		reg |= ASRGR_CORE_CLK_FREQ_200MHZ;
		break;
	default:
		mvOsPrintf("mvSPDIFRecordTclockSet: Not supported core clock %d\n",tclock);
		return MV_NOT_SUPPORTED;
	}

	MV_REG_WRITE(MV_AUDIO_SPDIF_REC_GEN_REG, reg);
	
	return MV_OK;

}

void maskAllInt(void) {
	int i;
	/* for all interrupts (0-115) reset bit 0:3 and 8:11 to disable IRQ and FIQ */
	for (i=0; i < MV_IRQ_NR; i++)
		MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(i), MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(i)) & ~(0xF0F));

}

MV_VOID xorSetSrcBurstLimit(MV_U32 chan, MV_XOR_BURST_LIMIT srcBurstLimit)
{
    MV_U32 temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
    temp &= ~XEXCR_SRC_BURST_LIMIT_MASK;
    temp |= srcBurstLimit << XEXCR_SRC_BURST_LIMIT_OFFS;
    MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan)), temp);
}

/*******************************************************************************
* mvSataWinInit - Initialize the integrated SATA target address window.
*
* DESCRIPTION:
*       Initialize the SATA peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*     
*
* RETURN:
*       MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSataWinInit(MV_UNIT_WIN_INFO *addrWinMap)
{
    MV_U32		winNum;
    MV_UNIT_WIN_INFO	*addrDecWin;
    MV_U32		winPrioIndex = 0;

    /* Initiate Sata address decode */

    /* First disable all address decode windows */
    for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++)
    {
        MV_U32  regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum));
        regVal &= ~MV_SATA_WIN_ENABLE_MASK;
        MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal);
    }

    winNum = 0;
    while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
           (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) )
    {
	addrDecWin = &addrWinMap[sataAddrDecPrioTab[winPrioIndex]];
        if (addrDecWin->enable == MV_TRUE)
        {
            if(MV_OK != mvSataWinWrite(0/*dev*/, winNum, addrDecWin))
            {
                return MV_ERROR;
            }
            winNum++;
        }
        winPrioIndex++;
    }
    return MV_OK;
}

/*******************************************************************************
* mvPciCommandSet - Set PCI comman register value.
*
* DESCRIPTION:
*       This function sets a given PCI interface with its command register 
*       value.
*
* INPUT:
*       pciIf   - PCI interface number.
*       command - 32bit value to be written to comamnd register.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_BAD_PARAM if pciIf is not in range otherwise MV_OK
*
*******************************************************************************/
MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command)
{
	MV_U32 locBusNum, locDevNum, regVal;

	locBusNum =  mvPciLocalBusNumGet(pciIf);
	locDevNum =  mvPciLocalDevNumGet(pciIf);

	/* Parameter checking   */
	if (pciIf >= mvCtrlPciMaxIfGet()) {
		mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf);
		return MV_BAD_PARAM;
	}

	/* Set command register */
	MV_REG_WRITE(PCI_CMD_REG(pciIf), command);

	/* Upodate device max outstanding split tarnsaction */
	if ((command & PCR_CPU_TO_PCI_ORDER_EN) && (command & PCR_PCI_TO_CPU_ORDER_EN)) {
	        /* Read PCI-X command register */
        	regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND);
                        
	        /* clear bits 22:20 */
        	regVal &= 0xff8fffff;

	        /* set reset value */
        	regVal |= (0x3 << 20);
        
	        /* Write back the value */
        	mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal);
	}

	return MV_OK;
}

MV_STATUS mvXorOverrideSet(MV_U32 chan, MV_XOR_OVERRIDE_TARGET target, MV_U32 winNum, MV_BOOL enable)
{
	MV_U32 temp;

	/* Parameter checking   */
	if (chan >= MV_XOR_MAX_CHAN) {

		DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan));
		return MV_BAD_PARAM;
	}
	if (winNum >= XOR_MAX_OVERRIDE_WIN) {
		DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __func__, winNum));
		return MV_BAD_PARAM;
	}

	/* set the enable bit */
	if (enable)
		MV_REG_BIT_SET(XOR_OVERRIDE_CTRL_REG(chan), XEXAOCR_OVR_EN_MASK(target));
	 else
		MV_REG_BIT_RESET(XOR_OVERRIDE_CTRL_REG(chan), XEXAOCR_OVR_EN_MASK(target));

	/* read the override control register */
	temp = MV_REG_READ(XOR_OVERRIDE_CTRL_REG(chan));
	temp &= ~XEXAOCR_OVR_PTR_MASK(target);
	temp |= (winNum << XEXAOCR_OVR_PTR_OFFS(target));
	MV_REG_WRITE(XOR_OVERRIDE_CTRL_REG(chan), temp);
	return MV_OK;
}

/*******************************************************************************
* mvPciRetrySet - Set PCI retry counters
*
* DESCRIPTION:
*       This function specifies the number of times the PCI controller 
*       retries a transaction before it quits.
*       Applies to the PCI Master when acting as a requester.
*       Applies to the PCI slave when acting as a completer (PCI-X mode).
*       A 0x00 value means a "retry forever".
*
* INPUT:
*       pciIf   - PCI interface number.
*       counter - Number of times PCI controller retry. Use counter value 
*                 up to PRR_RETRY_CNTR_MAX.
*
* OUTPUT:
*       None.
*
* RETURN:
*       MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
*
*******************************************************************************/
MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter)
{
	MV_U32 pciRetry;

	/* Parameter checking   */
	if (pciIf >= mvCtrlPciMaxIfGet())
	{
		mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf);
		return MV_BAD_PARAM;
	}

	if (counter >= PRR_RETRY_CNTR_MAX)
	{
		mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter);
		return MV_BAD_PARAM;

	}

	/* Reading PCI retry register */
    pciRetry  = MV_REG_READ(PCI_RETRY_REG(pciIf));

	pciRetry &= ~PRR_RETRY_CNTR_MASK;

	pciRetry |= (counter << PRR_RETRY_CNTR_OFFS);

	/* write new value */
	MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry);

	return MV_OK;
}

/*******************************************************************************
* mvAc97CodecRegWrite
*
* DESCRIPTION:
*       Write to an attached AC'97 codec register.
*
* INPUT:
*       codecId - The Codec ID to write the register for.
*	regAddr	- The Codec register address to write to.
*	data	- Data to be written.
*
* OUTPUT:
*	None.
*
* RETURN:
*       MV_OK	- On successfull init,
*	MV_FAIL	- Otherwise.
*******************************************************************************/
MV_STATUS mvAc97CodecRegWrite(MV_AC97_CODEC_ID codecId, MV_U16 regAddr,MV_U16 data)
{
	MV_U32 	val;
	MV_U32	status = MV_OK;
	MV_U32 	accAddr;
	MV_U32	retries = AC97_READ_WRITE_MAX_RETRY;

	/* Get the access register.			*/
	mvAc97CodecAccessRegGet(codecId,regAddr,&accAddr);

	/* Clear the command / status done bits.	*/
	MV_REG_BIT_SET(MV_AC97_GLOBAL_STATUS_REG,
		       (AC97_GLB_STATUS_DONE_MASK | AC97_GLB_CMND_DONE_MASK));

	/* Issue the write operation.			*/
	val = (MV_U32)data;
	MV_REG_WRITE(accAddr,val);

	/* Wait till the status done bit is valid.	*/
	while(retries > 0)
	{
		retries--;
		val = MV_REG_READ(MV_AC97_GLOBAL_STATUS_REG);
		if(val & AC97_GLB_CMND_DONE_MASK)
			break;
	}

	/* Check for a timeout.				*/
	if(retries == 0)
		status = MV_TIMEOUT;

	return status;
}

/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
*	Do a basic Init to the Phy , including reset
*
* INPUT:
*       ethPortNum - Ethernet port number
*
* OUTPUT:
*       None.
*
* RETURN:   None
*
*******************************************************************************/
MV_VOID		mvEthE1116PhyBasicInit(MV_U32 ethPortNum)
{
	MV_U16 reg;

	/* Set phy address */
	MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));

	/* Leds link and activity*/
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
	mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,&reg);
	reg &= ~0xf;
	reg	|= 0x1;
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);

	/* Set RGMII delay */
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
	mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,&reg);
	reg	|= (BIT5 | BIT4);
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg);
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);

	/* reset the phy */
	mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,&reg);
	reg |= BIT15;
	mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}

/*******************************************************************************
* mvEthPhyRegRead - Read from ethernet phy register.
*
* DESCRIPTION:
*       This function reads ethernet phy register.
*
* INPUT:
*       phyAddr - Phy address.
*       regOffs - Phy register offset.
*
* OUTPUT:
*       None.
*
* RETURN:
*       16bit phy register value, or 0xffff on error
*
*******************************************************************************/
MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data)
{
	MV_U32 			smiReg;
	volatile MV_U32 timeout;

	/* check parameters */
	if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK)
	{
		mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY device address %d\n",
                   phyAddr);
		return MV_FAIL;
	}
	if ((regOffs <<  ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK)
	{
		mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY register offset %d\n",
                   regOffs);
		return MV_FAIL;
	}

	timeout = ETH_PHY_TIMEOUT;
	/* wait till the SMI is not busy*/
	do
	{
		/* read smi register */
		smiReg = MV_REG_READ(ETH_PHY_SMI_REG);
		if (timeout-- == 0)
		{
			mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
			return MV_FAIL;
		}
	}while (smiReg & ETH_PHY_SMI_BUSY_MASK);

	/* fill the phy address and regiser offset and read opcode */
	smiReg = (phyAddr <<  ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS )|
			   ETH_PHY_SMI_OPCODE_READ;

	/* write the smi register */
	MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg);

	timeout=ETH_PHY_TIMEOUT;

	/*wait till readed value is ready */
	do
	{
		/* read smi register */
		smiReg=MV_REG_READ(ETH_PHY_SMI_REG);

		if (timeout-- == 0) {
			mvOsPrintf("mvEthPhyRegRead: SMI read-valid timeout\n");
			return MV_FAIL;
		}
	}while (!(smiReg & ETH_PHY_SMI_READ_VALID_MASK));

	/* Wait for the data to update in the SMI register */
	for(timeout = 0 ; timeout < ETH_PHY_TIMEOUT ; timeout++);

	*data = (MV_U16)( MV_REG_READ(ETH_PHY_SMI_REG) & ETH_PHY_SMI_DATA_MASK);

	return MV_OK;
}

MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
{
	MV_U16 value;
	MV_U16 phyAddr = mvBoardPhyAddrGet(port);

	MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);

	/* Change page select to 2 */
	value = 2;
	mvEthPhyRegWrite(phyAddr, 22, value);
	mvOsDelay(10);

	/* Set RGMII rx delay */
	mvEthPhyRegRead(phyAddr, 21, &value);
	value |= BIT5;
	mvEthPhyRegWrite(phyAddr, 21, value);
	mvOsDelay(10);

	/* Change page select to 0 */
	value = 0;
	mvEthPhyRegWrite(phyAddr, 22, value);
	mvOsDelay(10);

	/* reset the phy */
	mvEthPhyRegRead(phyAddr, 0, &value);
	value |= BIT15;
	mvEthPhyRegWrite(phyAddr, 0, value);
	mvOsDelay(10);
}

void second_cpu_msi_init(void)
{
    unsigned long temp;
    /* Unmask private doorbells 16-31 */
    temp = MV_REG_READ(AXP_IN_DRBEL_MSK) | (0xFFFF0000);
    MV_REG_WRITE(AXP_IN_DRBEL_MSK, temp);
}