def led_dance(
  # ~~~[Ports]~~~
  clock,             # input : system sync clock
  reset,             # input : reset (level determined by RST_LEVEL)
  leds,              # output : to IO ports drive LEDs

  # ~~~[Parameters]~~~
  led_rate=33e-3,    # strobe change rate of 333ms
):
    """
    """
    gens = []

    cnt_max = int(clock.frequency * led_rate)
    clk_cnt = Signal(intbv(1, min=0, max=cnt_max))
    rled = Signal(modbv(0)[len(leds):])

    # assign the port LED to the internal register led
    gas = assign(leds, rled)

    # @todo: create a module to select a rate strobe,
    #    the module will return a signal that is from
    #    an existing rate or a generator and signal
    mb = len(leds)-1
    d = modbv(0)[len(leds):]

    @always_seq(clock.posedge, reset=reset)
    def rtl():
        if clk_cnt == 0:
            d[:] = (rled ^ 0x81) << 1
            rled.next = concat(d, rled[mb])
        clk_cnt.next = clk_cnt + 1

    gens += (gas, rtl,)
    return gas, rtl

def Test():
    depth = 4
    width = 4
    
    dout = Signal(modbv(0)[width:])
    din = Signal(modbv(0)[width:])
    full = Signal(bool(0))
    empty = Signal(bool(0))
    push = Signal(bool(0))
    clk = Signal(bool(0))
    
    stack = Stack(dout, din, full, empty, push, clk, width=width, depth=depth)
    
    @instance
    def stimulus():
        print('dout\tdin\tfull\tempty\tpush')
        push.next = 1
        for k in range(16):
            din.next = k + 1
            push.next = k < 8
            yield delay(10)
            clk.next = 1
            yield delay(10)
            clk.next = 0
            print(dout, din, full, empty, push, sep='\t')
            
    return instances()

def test_register_file():

    clock, write_enable = [Signal(False) for _ in range(2)]
    read_addr1, read_addr2, write_addr = [Signal(modbv(0)[REG_ADDR_WIDTH:]) for _ in range(3)]
    read_data1, read_data2, write_data = [Signal(modbv(0)[XPR_LEN:]) for _ in range(3)]

    reg_file_inst = register_file(clock, read_addr1, read_data1, read_addr2, read_data2, write_enable, write_addr, write_data)
    reg_file_inst.convert(hdl='Verilog')

    rand_value = randint(1, (1 << XPR_LEN) - 1)
    rand_addr = randint(1, (1 << REG_ADDR_WIDTH) - 1)

    @always(delay(1))
    def drive_clock():
        clock.next = not clock

    @instance
    def test():
        write_enable.next = True
        yield clock.posedge
        write_data.next = rand_value
        write_addr.next = rand_addr
        yield clock.posedge
        read_addr1.next = rand_addr
        read_addr2.next = rand_addr
        yield clock.posedge
        assert rand_value == read_data1 == read_data2

    return test, reg_file_inst, drive_clock

def led_dance(clock, reset, leds, led_rate=33e-3):
    """An interesting LED pattern

    Arguments:
        clock: system clock
        reset: system reset
        leds: LED bits

    Parameters:
        led_rate: the rate to blink, in seconds
    """
    cnt_max = int(clock.frequency * led_rate)
    clk_cnt = Signal(intbv(1, min=0, max=cnt_max))
    rled = Signal(modbv(0)[len(leds):])

    # assign the port LED to the internal register led
    assign(leds, rled)

    # @todo: create a module to select a rate strobe,
    #    the module will return a signal that is from
    #    an existing rate or a generator and signal
    mb = len(leds)-1
    d = modbv(0)[len(leds):]

    @always_seq(clock.posedge, reset=reset)
    def beh():
        if clk_cnt == 0:
            d[:] = (rled ^ 0x81) << 1
            rled.next = concat(d, rled[mb])
        clk_cnt.next = clk_cnt + 1

    return myhdl.instances()

def fifo_async(clock_write, clock_read, fifobus, reset, size=128):
    """
    The following is a general purpose, platform independent 
    asynchronous FIFO (dual clock domains).

    Cross-clock boundary FIFO, based on:
    "Simulation and Synthesis Techniques for Asynchronous FIFO Design"

    Typically in the "rhea" package the FIFOBus interface is used to
    interface with the FIFOs
    """
    # @todo: use the clock_write and clock_read from the FIFOBus
    # @todo: interface, make this interface compliant with the
    # @todo: fifos: fifo_async(reset, clock, fifobus)

    # for simplification the memory size is forced to a power of 
    # two - full address range, ptr (mem indexes) will wrap
    asz = int(ceil(log(size, 2)))
    fbus = fifobus   # alias
    
    # an extra bit is used to determine full vs. empty (see paper)
    waddr = Signal(modbv(0)[asz:])
    raddr = Signal(modbv(0)[asz:])
    wptr = Signal(modbv(0)[asz+1:])
    rptr = Signal(modbv(0)[asz+1:])
    wq2_rptr = Signal(intbv(0)[asz+1:])
    rq2_wptr = Signal(intbv(0)[asz+1:])

    wfull = Signal(bool(0))
    rempty = Signal(bool(1))

    # sync'd resets, the input reset is more than likely sync'd to one
    # of the clock domains, sync both regardless ...
    wrst = ResetSignal(reset.active, active=reset.active, async=reset.async)

 def accessor():
     if state == state_t.READY:
         coeff_ram_blk.next = True
         if enable and in_valid:
             delay_line_i_ram_addr.next = concat(bank1, bank0, n)
             delay_line_i_ram_din.next = in_i
             delay_line_i_ram_blk.next = False
             delay_line_i_ram_wen.next = False
             delay_line_q_ram_addr.next = concat(bank1, bank0, n)
             delay_line_q_ram_din.next = in_q
             delay_line_q_ram_blk.next = False
             delay_line_q_ram_wen.next = False
         else:
             delay_line_i_ram_blk.next = True
             delay_line_q_ram_blk.next = True
             
     elif state == state_t.WAIT1 or state == state_t.WAIT2 or state == state_t.RUN:
         delay_line_i_ram_addr.next = concat(bank1, bank0, modbv(n - k, min=0, max=2**7-1))
         delay_line_i_ram_blk.next = False
         delay_line_i_ram_wen.next = True
         delay_line_q_ram_addr.next = concat(bank1, bank0,
                 modbv(n - k, min=0, max=2**7-1))
         delay_line_q_ram_blk.next = False
         delay_line_q_ram_wen.next = True
         coeff_ram_addr.next = concat(bank1, bank0, k)
         coeff_ram_blk.next = False
         coeff_ram_wen.next = True
     else:
         delay_line_i_ram_blk.next = True
         delay_line_q_ram_blk.next = True
         coeff_ram_blk.next = True

 def rtl():
     b30_20.next = (
         instruction[31:20]
         if sel == Consts.IMM_U
         else concat(sign, sign, sign, sign, sign, sign, sign, sign, sign, sign, sign)
     )
     b19_12.next = (
         instruction[20:12]
         if (sel == Consts.IMM_U or sel == Consts.IMM_UJ)
         else concat(sign, sign, sign, sign, sign, sign, sign, sign)
     )
     b11.next = (
         False
         if (sel == Consts.IMM_U or sel == Consts.IMM_Z)
         else (instruction[20] if sel == Consts.IMM_UJ else (instruction[7] if sel == Consts.IMM_SB else sign))
     )
     b10_5.next = modbv(0)[6:] if (sel == Consts.IMM_U or sel == Consts.IMM_Z) else instruction[31:25]
     b4_1.next = (
         modbv(0)[4:]
         if sel == Consts.IMM_U
         else (
             instruction[12:8]
             if (sel == Consts.IMM_S or sel == Consts.IMM_SB)
             else (instruction[20:16] if sel == Consts.IMM_Z else instruction[25:21])
         )
     )
     b0.next = (
         instruction[7]
         if sel == Consts.IMM_S
         else (instruction[20] if sel == Consts.IMM_I else (instruction[15] if sel == Consts.IMM_Z else False))
     )

def IntToFloat(
        float_output,
        int_input,
        exponent_width,
        fraction_width,
        exponent_bias):
    INT_WIDTH = len(int_input)
    FLOAT_WIDTH = len(float_output)
    
    sign = Signal(bool(0))
    sign_getter = SignGetter(sign, int_input)
    
    abs_int = Signal(modbv(0)[INT_WIDTH:])           
    abs_calculator = Abs(abs_int, int_input)
    
    abs_float = Signal(modbv(0)[(1+exponent_width+fraction_width):])         
    float_calculator = UIntToFloat(
            abs_float, abs_int, 
            exponent_width, fraction_width, exponent_bias)
    
    signed_float = ConcatSignal(sign, abs_float(FLOAT_WIDTH-1, 0))
    
    @always_comb
    def make_output():
        float_output.next = signed_float
        
    return instances()

def Test():
    # IEEE754 Single
    EXPONENT_WIDTH = 8
    FRACTION_WIDTH = 23
    EXPONENT_BIAS = 127
    
    INT_WIDTH = 6
    
    float_sig = Signal(modbv(0)[(1+EXPONENT_WIDTH+FRACTION_WIDTH):])
    int_sig = Signal(modbv(0)[INT_WIDTH:])
    
    convertor = IntToFloat(
            float_sig,
            int_sig,
            exponent_width=EXPONENT_WIDTH,
            fraction_width=FRACTION_WIDTH,
            exponent_bias=EXPONENT_BIAS)
    
    @instance
    def stimulus():
        print('input', 'output', sep='\t')
        for k in range(-2**(INT_WIDTH-1), 2**(INT_WIDTH-1)):
            int_sig.next = k
            yield delay(10)
            int_val = int(int_sig)
            if k < 0:
                int_val = ~int_val + 1
                int_val &= 2**INT_WIDTH - 1
                int_val = -int_val
            print(int_val, uint_to_float(int(float_sig))[0], sep='\t')
            
    return instances()

def UIntToFloat(
        float_output,
        uint_input,
        exponent_width,
        fraction_width,
        exponent_bias
    ):
    
    # Calculating unbiased and biased exponent.
    unbiased_exponent = Signal(modbv(0)[exponent_width:])
    biased_exponent = Signal(modbv(0)[exponent_width:])
    nz_flag = Signal(bool(0))
    unbiased_exponent_calculator = PriorityEncoder(
            unbiased_exponent, nz_flag, uint_input)
    @always_comb
    def biased_exponent_calculator():
        biased_exponent.next = unbiased_exponent + exponent_bias
    
    # Calculating fraction part. 
    fraction = Signal(modbv(0)[fraction_width:])
    fraction_calculator = UIntToFraction(
            fraction, uint_input, unbiased_exponent)
    
    float_sig = ConcatSignal(bool(0), biased_exponent, fraction)
    
    @always_comb
    def make_output():
        if uint_input == 0:
            float_output.next = 0
        else:
            float_output.next = float_sig
        
            
    return instances()

    def test():
        PC_src_sel.next = PC_JAL_TARGET
        yield delay(10)
        assert PC_PIF == modbv(PC_DX + jal_offset)[XPR_LEN:]

        PC_src_sel.next = PC_JALR_TARGET
        yield delay(10)
        assert PC_PIF == modbv(rs1_data + jalr_offset)[XPR_LEN:]

        PC_src_sel.next = PC_BRANCH_TARGET
        yield delay(10)
        assert PC_PIF == modbv(PC_DX + imm_b)[XPR_LEN:]

        PC_src_sel.next = PC_REPLAY
        yield delay(10)
        assert PC_PIF == PC_IF

        PC_src_sel.next = PC_HANDLER
        yield delay(10)
        assert PC_PIF == handler_PC

        PC_src_sel.next = PC_EPC
        yield delay(10)
        assert PC_PIF == epc

        PC_src_sel.next = PC_PLUS_FOUR
        yield delay(10)
        assert PC_PIF == modbv(PC_IF + 4)[XPR_LEN:]

 def state_machine():
     if state == s_idle:
         if req_valid:
             result.next = 0
             a.next = abs_in_1
             b.next = concat(abs_in_2, modbv(0)[XPR_LEN:]) >> 1
             if op == MD_OP_REM:
                 negate_output.next = sign_in_1
             else:
                 negate_output.next = sign_in_1 ^ sign_in_2
             out_sel.next = req_out_sel
             op.next = req_op
             counter.next = XPR_LEN - 1
     elif state == s_compute:
         counter.next = counter + 1
         b.next = b >> 1
         if op == MD_OP_MUL:
             if a[counter]:
                 result.next = result + b
         else:
             b.next = b + 1
             if a_geq:
                 a.next = a - b
                 result.next = modbv(1 << counter)[DOUBLE_XPR_LEN:] | result
     elif state == s_setup_output:
         result.next = concat(modbv(0)[XPR_LEN:], final_result)

 def __init__(self):
     """
     Initializes the IO ports.
     """
     self.wa = Signal(modbv(0)[5:])
     self.we = Signal(False)
     self.wd = Signal(modbv(0)[32:])

 def assignments_0():
     sign_a.next = io.input1[31] if (io.cmd[0] or io.cmd[2]) else modbv(0)[1:]
     sign_b.next = io.input2[31] if io.cmd[0] else modbv(0)[1:]
     partial_sum.next = concat(modbv(0)[15:], result_mid_1) + concat(result_hh_1[32:], result_ll_1[32:16])
     io.output.next = -result_mult if sign_result3 else result_mult
     io.ready.next = active3
     io.active.next = active0 | active1 | active2 | active3

    def write_process1():
        
        if state_m == bp_states_m.WRITE1:
            
            index_r                           = random[26:20]
                        
            #btb_line[index_r][64:63].next     = Signal(True)  #Set Valid Bit
            #btb_line[index_r][61:32].next     = tag_pc[32:2]  #Store tag
            
 
            if BPio.valid_jump:
                btb_line[index_r].next        = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.ST)[2:])
                # btb_line[index_r][63:62].next = Signal(True)              #Set Unconditional Bit
                # btb_line[index_r][2:0].next   = Consts.ST                 #As a jump it'll always be ST
                # BPio.current_state.next       = Consts.ST                 #Send our current state to Cpath
                # btb_line[index_r][32:2].next  = BPio.pc_id_brjmp[32:2]    #Store jump address in BTB

            elif BPio.valid_branch:
                btb_line[index_r].next        = concat(True,False,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.WN)[2:])
                #btb_line[index_r][63:62].next = Signal(False)           #Clear unconditional bit
                #btb_line[index_r][2:0].next   = Consts.WN               #It will be initialized in WN
                #BPio.current_state.next       = Consts.WN               #Send our current state to Cpath
                #btb_line[index_r][32:2].next  = BPio.pc_id_brjmp[32:2]  #Store Branch address in BTB
        
            else:   #Corresponding to JALR
                #btb_line[index_r][63:62]      = Signal(True)            #Set Unconditional bit
                #btb_line[index_r][2:0]        = Consts.ST               #As an indirect jump it'll always be taken
                #BPio.current_state.next       = Consts.ST               #Send our current state to Cpath
                #btb_line[index_r][32:2]       = BPio.pc_id_jalr[32:2]   #Store jump address in BTB  
                btb_line[index_r].next        = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_jalr[32:2])[30:],modbv(Consts.ST)[2:])

            

            final_write1.next      = True

 def __init__(self):
     self.input1    = Signal(modbv(0)[32:])
     self.input2    = Signal(modbv(0)[32:])
     self.function  = Signal(modbv(0)[ALUOp.SZ_OP:])
     self.stall     = Signal(False)
     self.kill      = Signal(False)
     self.output    = Signal(modbv(0)[32:])
     self.req_stall = Signal(False)

def convert():
    shifted = Signal(modbv(0)[32:])
    data = Signal(modbv(0)[32:])
    num = Signal(modbv(0)[5:])
    direction = Signal(bool(0))
    
    inst = MultShifter(shifted=shifted, data=data, direction=direction, num=num)
    inst.convert(hdl='verilog')

def IMMGen(sel, instruction, imm):
    """
    Generate the immediate values.

    :param sel:         Select the type of instruction/immediate
    :param instruction: Current instruction
    :param imm:         A 32-bit immediate value
    """
    sign = Signal(False)
    b30_20 = Signal(modbv(0)[11:])
    b19_12 = Signal(modbv(0)[8:])
    b11 = Signal(False)
    b10_5 = Signal(modbv(0)[6:])
    b4_1 = Signal(modbv(0)[4:])
    b0 = Signal(False)

    @always_comb
    def _sign():
        sign.next = False if sel == Consts.IMM_Z else instruction[31]

    @always_comb
    def rtl():
        b30_20.next = (
            instruction[31:20]
            if sel == Consts.IMM_U
            else concat(sign, sign, sign, sign, sign, sign, sign, sign, sign, sign, sign)
        )
        b19_12.next = (
            instruction[20:12]
            if (sel == Consts.IMM_U or sel == Consts.IMM_UJ)
            else concat(sign, sign, sign, sign, sign, sign, sign, sign)
        )
        b11.next = (
            False
            if (sel == Consts.IMM_U or sel == Consts.IMM_Z)
            else (instruction[20] if sel == Consts.IMM_UJ else (instruction[7] if sel == Consts.IMM_SB else sign))
        )
        b10_5.next = modbv(0)[6:] if (sel == Consts.IMM_U or sel == Consts.IMM_Z) else instruction[31:25]
        b4_1.next = (
            modbv(0)[4:]
            if sel == Consts.IMM_U
            else (
                instruction[12:8]
                if (sel == Consts.IMM_S or sel == Consts.IMM_SB)
                else (instruction[20:16] if sel == Consts.IMM_Z else instruction[25:21])
            )
        )
        b0.next = (
            instruction[7]
            if sel == Consts.IMM_S
            else (instruction[20] if sel == Consts.IMM_I else (instruction[15] if sel == Consts.IMM_Z else False))
        )

    @always_comb
    def imm_concat():
        imm.next = concat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0)

    return instances()

def MultShifter(
        shifted,
        data,
        direction,        
        num
        ):
    WIDTH = len(data)
    MAX_SHIFT = 2**len(num)
        
    line_in_bits  = [Signal(bool(0)) for k in range(WIDTH)]    
    @always_comb
    def line_in_conn():
        for k in range(WIDTH):
            line_in_bits[k].next = data[k]
    line_in_origin   = ConcatSignal(*reversed(line_in_bits))
    line_in_reversed = ConcatSignal(*line_in_bits)
    line_in = Signal(modbv(0)[WIDTH:])
    @always_comb
    def line_in_mux():
        if direction==LEFT:
            line_in.next = line_in_origin
        else:
            line_in.next = line_in_reversed
    
    line_out = Signal(modbv(0)[WIDTH:])
    line_out_bits = [Signal(bool(0)) for k in range(WIDTH)]
    @always_comb
    def line_out_conn():
        for k in range(WIDTH):
            line_out_bits[k].next = line_out[k]
    line_out_origin   = ConcatSignal(*reversed(line_out_bits))
    line_out_reversed = ConcatSignal(*line_out_bits)    
    @always_comb
    def shifted_mux():
        if direction==LEFT:
            shifted.next = line_out_origin
        else:
            shifted.next = line_out_reversed
                
    m = Signal(modbv(0)[WIDTH:])
        
    @always_comb
    def num_to_pow():
        temp = modbv(0)[WIDTH:]
        for k in range(WIDTH):
            if k == num:
                temp[k] = 1
        m.next = temp
        
    @always_comb
    def shift():
        if num > WIDTH - 1:
            line_out.next = 0
        else:
            line_out.next = line_in * m
        
    return instances()

 def __init__(self):
     self.dividend  = Signal(modbv(0)[32:])
     self.divisor   = Signal(modbv(0)[32:])
     self.divs      = Signal(False)
     self.divu      = Signal(False)
     self.active    = Signal(False)
     self.ready     = Signal(False)
     self.quotient  = Signal(modbv(0)[32:])
     self.remainder = Signal(modbv(0)[32:])