def tbstim():
   yield delay(10)
   print("{0:<8d} ".format(now()))
   yield delay(1000)
   print("{0:<8d} ".format(now()))
   for _ in range(10):
     yield delay(1000)

    def bench(self):
        clk = Signal(0)
        sig1 = Signal(0)
        sig2 = Signal(0)
        td = 10

        def gen(s, n):
            for i in range(n-1):
                yield delay(td)
            s.next = 1
            yield delay(td)

        for i in range(10):
            offset = now()
            n0 = randrange(1, 50)
            n1 = randrange(1, 50)
            n2 = randrange(1, 50)
            sig1.next = 0
            sig2.next = 0
            yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
            assert sig1.val == 1
            assert sig2.val == 1
            assert now() == offset + td * max(n0, n1, n2)

        raise StopSimulation("Joined concurrent generator yield")

    def bench(self):
        clk = Signal(0)
        sig1 = Signal(0)
        sig2 = Signal(0)
        td = 10

        def gen(s, n):
            s.next = 0
            for i in range(n):
                yield delay(td)
            s.next = 1

        for i in range(100):
            offset = now()
            n1 = randrange(2, 10)
            n2 = randrange(n1+1, 20) # n2 > n1
            yield delay(0), gen(sig1, n1), gen(sig2, n2)
            self.assertEqual(sig1.val, 0)
            self.assertEqual(sig2.val, 0)
            self.assertEqual(now(), offset + 0)
            yield sig1.posedge
            self.assertEqual(sig2.val, 0)
            self.assertEqual(now(), offset + n1*td)
            yield sig2.posedge
            self.assertEqual(now(), offset + n2*td)
        
        raise StopSimulation, "Zero delay yield"

 def mon_state():
     print("  :{:<8d}: initial state {}".format(
         now(), str(state)))
         
     while True:
         yield state
         print("  :{:<8d}: state transition --> {}".format(
             now(), str(state)))

 def toHost_check():
     """
     Wait for a write to toHost register.
     """
     if toHost != 1:
         raise Error('Test failed. MTOHOST = {0}. Time = {1}'.format(toHost, now()))
     print("Time: {0}".format(now()))
     raise StopSimulation

        def test():
            for i in range(0, 100, 2):
                self.assertEquals(now(), i*half_period)
                yield clk.posedge
                self.assertEquals(now(), (i+1)*half_period)
                yield clk.negedge

            raise StopSimulation()

 def tb_monitor():
     if SLWR or SLRD or SLOE or FLAGA or FLAGB or FLAGC or FLAGD:
         fm.trace_print('   %d control signal changed' % (now()))
     if ADDR == 0:
         fm.trace_print('   %d address is zero' % (now()))
     else:
         fm.trace_print('   %d address not zero %d' % (now(), ADDR))
     if FDI != FDO:
         fm.trace_print('   %d data input != output' % (now()))

 def stimulus():
     a = Signal(0)
     yield delay(10)
     a.next = 1
     yield None, delay(10)
     assert a.val == 0
     assert now() == 10
     yield delay(0)
     assert a.val == 1
     assert now() == 10

 def stimulus():
     a = Signal(0)
     yield delay(10)
     a.next = 1
     yield None, delay(10)
     self.assertEqual(a.val, 0)
     self.assertEqual(now(), 10)
     yield delay(0)
     self.assertEqual(a.val, 1)
     self.assertEqual(now(), 10)

 def tb_reset():
     while True:
         print('%8d ... Wait Reset' % (now()))
         yield self.doreset.posedge
         print('%8d ... Do Reset' % (now()))
         fx.RST.next = False
         yield delay(13*self.IFCLK_TICK)
         fx.RST.next = True
         yield delay(13*self.IFCLK_TICK)
         self.doreset.next = False
         print('%8d ... End Reset' % (now()))

 def _wait_empty(self, ep, timeout=100):
     ok = False
     to = timeout * 1e6
     te = now() + to
     for ii in range(timeout):
         if self.isempty(ep):
             ok = True
             break
         time.sleep(1)
         if now() > te:
             break
     return ok

 def tbstim():
     yield clkwait(hostintf.clk, count=20)
     yield hostintf.writeconfig(0x340, 0x00000002)
     yield mdiointf.mdc.posedge
     time_mdc = now()
     yield mdiointf.mdc.posedge
     time_mdc = now() - time_mdc
     yield hostintf.clk.posedge
     time_hostclk = now()
     yield hostintf.clk.posedge
     time_hostclk = now() - time_hostclk
     assert time_hostclk == time_mdc / 6

 def computePL1():
     done.next = state_done
     if not state_go: # state_go
         state_done.next = False # state_done
         stage_m.next = False # stage_mp
         sig_l1c.next = 0
         for i in range(r_l1m): sig_l1m[i] = 0
         conv_cord_x.next = 0
         conv_cord_y.next = 0
         patch_x.next = 0
         patch_y.next = 0
         patch_cumu.next = False
         if go:
             state_go.next = True
             if __debug__:
                 print " now %s good state start" % now()
     else:
         if not state_done: # state_done
             if not stage_m: # stage_mp
                 if __debug__:
                     print " now %s stage p x %u y %u p %u %u" % (
                         now(), conv_cord_x, conv_cord_y,
                         patch_x, patch_y)
                 if not patch_cumu:
                     fltidx = patch_x + patch_y * p
                     pixidx = (conv_cord_x + patch_x) + (conv_cord_y + patch_y) * p
                     sig_l1c.next = sig_l1c + filter[fltidx] * pixels[pixidx]
                     if patch_x >= p-1 and patch_y >= p-1:
                         patch_cumu.next = True
                     elif patch_x >= p-1:
                         patch_x.next = 0
                         patch_y.next = patch_y + 1
                     else:
                         patch_x.next = patch_x + 1
                 else:
                     pixidx = conv_cord_x + conv_cord_y * p
                     mid1c[pixidx] = sig_l1c[16:8]
                     patch_cumu.next = False
                     patch_x.next = 0
                     patch_y.next = 0
                     if conv_cord_x >= n_l1c - 1 and conv_cord_y >= n_l1c - 1:
                         stage_m.next = True
                     elif conv_cord_x == n_l1c - 1:
                         conv_cord_x.next = 0
                         conv_cord_y.next = conv_cord_y + 1
                     else:
                         conv_cord_x.next = conv_cord_x + 1
             else:
                 if __debug__:
                     print " now %s stage m x %u y %u p %u %u" % (
                         now(), conv_cord_x, conv_cord_y,
                         patch_x, patch_y)
                 state_done.next = True

 def _wait_data(self, ep, num=1, timeout=100):
     ok = False
     to = timeout * 1e6
     te = now() + to
     for ii in range(timeout):
         if self.isdata(ep, num=num):
             ok = True
             break
         time.sleep(1)
         if now() > te:
             break
     return ok

 def response(self, clause, expected):
     self.assert_(len(expected) > 100) # we should test something
     i = 0
     while 1:
         yield clause
         self.assertEqual(now(), expected[i])
         i += 1

 def monitor():
     yield self.rx_ready.posedge, delay(500000)
     yield delay(1)
     print(now())
     self.assertEquals(self.rx_msg, 0x0FFFFFFFFFFF)
     self.assertTrue(self.rx_ready)
     self.stop_simulation()

        def tbstim():
            resetext.next = not resetext.active
            yield delay(33*ticks_per_ns)

            for ii in range(3):
                yield dripple.posedge
                ts = myhdl.now()
                yield dripple.posedge
                td = myhdl.now() - ts
                yield delay(100*ticks_per_ns)
                print(td, 2*ticks_per_ns*1e3)
                # assert td == 2 * ticks_per_ns * 1e3

            yield delay(100*ticks_per_ns)

            raise myhdl.StopSimulation

 def response(self, clause, expected):
     assert len(expected) > 100  # we should test something
     i = 0
     while 1:
         yield clause
         assert now() == expected[i]
         i += 1

 def testlogic():
     reset.next = 0
     yield delay(15)
     reset.next = 1
     yield delay(20)
     print("Converted! %d" % now())
     raise StopSimulation

 def testRedundantNegedges(self):
     """ Redundant negedge waveform test """
     s = self.sig
     stimulus = self.stimulus()
     expected = getExpectedTimes(self.waveform, isNegedge)
     response = self.response(clause=(s.negedge,) * 9, expected=expected)
     self.runSim(Simulation(stimulus, response))
     assert self.duration <= now()