本文整理汇总了Python中pyverilog.ast_code_generator.codegen.ASTCodeGenerator类的典型用法代码示例。如果您正苦于以下问题：Python ASTCodeGenerator类的具体用法？Python ASTCodeGenerator怎么用？Python ASTCodeGenerator使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了ASTCodeGenerator类的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的Python代码示例。
示例1: test
def test():
params = vast.Paramlist( [] )
clk = vast.Ioport( vast.Input('CLK') )
rst = vast.Ioport( vast.Input('RST') )
width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
led = vast.Ioport( vast.Output('led', width=width), vast.Reg('led', width=width) )
ports = vast.Portlist( (clk, rst, led) )
items = [ vast.EmbeddedCode("""
// Embedded code
reg [31:0] count;
always @(posedge CLK) begin
if(RST) begin
count <= 0;
led <= 0;
end else begin
if(count == 1024 - 1) begin
count <= 0;
led <= led + 1;
end else begin
count <= count + 1;
end
end
end
""") ]
ast = vast.ModuleDef("top", params, ports, items)
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)
assert(expected == rslt)
开发者ID:PyHDI，项目名称:Pyverilog，代码行数:31，代码来源:test_ast_embeddedcode.py
示例2: instantiate
def instantiate(self, instanceName, rank):
inst = Instance(self.name, instanceName, self.portlist, self.paramlist)
self.set_core_params(inst.parameterlist)
for line in inst.portlist:
if (line.argname.name != "wb_clk") & (line.argname.name != "wb_rst") & line.argname.name.startswith("wb"):
if rank == "slave":
if line.argname.name.endswith("i"):
line.argname.name = "wb_m2s_{modul_name}_{port}".format(modul_name=self.name,
port=line.argname.name[3:-2])
else:
line.argname.name = "wb_s2m_{modul_name}_{port}".format(modul_name=self.name,
port=line.argname.name[3:-2])
else:
if line.argname.name.endswith("o"):
line.argname.name = "wb_m2s_{modul_name}_{port}".format(modul_name=self.name,
port=line.argname.name[3:-2])
else:
line.argname.name = "wb_s2m_{modul_name}_{port}".format(modul_name=self.name,
port=line.argname.name[3:-2])
# Call the code generator
cg = ASTCodeGenerator()
val = cg.visit(inst)
val += "\n\n"
print(rank)
print(val)
return val
开发者ID:janosmurai，项目名称:top_gen_fusesoc，代码行数:28，代码来源:top_gen.py
示例3: fix_modelsim_altera_sdf_annotation
def fix_modelsim_altera_sdf_annotation(top_verilog):
base, ext = os.path.splitext(top_verilog)
new_file = '.'.join([base, "fixed"]) + ext;
#
#Load the original verilog
#
ast, directives = verilog_parser.parse([top_verilog])
#
#Add an unused stratixiv cell
#
mod_def = ast.description.definitions[0] #Definition of top
new_inst = vast.Instance('stratixiv_io_ibuf', 'fix_modelsim_altera_sdf_annotation', [], []);
new_inst_list = vast.InstanceList('stratixiv_io_ibuf', [], [new_inst])
items = list(mod_def.items) + [new_inst_list]
new_mod_def = vast.ModuleDef(mod_def.name, mod_def.paramlist, mod_def.portlist, items)
#
#Write out the new verilog
#
codegen = ASTCodeGenerator()
with open(new_file, "w") as f:
print >>f, codegen.visit(new_mod_def)
return new_file
开发者ID:kmurray，项目名称:esta，代码行数:29，代码来源:esta_flow.py
示例4: read_verilog_stubmodule
def read_verilog_stubmodule(*filelist, **opt):
module_dict = to_module_dict(*filelist, **opt)
codegen = ASTCodeGenerator()
stubs = collections.OrderedDict()
for name, m in module_dict.items():
description = vast.Description((m,))
source = vast.Source('', description)
code = codegen.visit(source)
stubs[name] = module.StubModule(name, code=code)
return stubs
开发者ID:PyHDI，项目名称:veriloggen，代码行数:10，代码来源:from_verilog.py
示例5: findParameters
def findParameters(self, node, lst):
if isinstance(node, Parameter):
var = node.value.var
cg = ASTCodeGenerator()
val = cg.visit(var)
self.paramlist.append(ParamArg(Identifier(node.name), var))
lst.append((node.name, val))
for child in node.children():
self.findParameters(child, lst)
return lst
开发者ID:janosmurai，项目名称:top_gen_fusesoc，代码行数:11，代码来源:top_gen.py
示例6: test
def test():
datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
params = vast.Paramlist( [datawid] )
clk = vast.Ioport( vast.Input('CLK') )
rst = vast.Ioport( vast.Input('RST') )
width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
led = vast.Ioport( vast.Output('led', width=width) )
ports = vast.Portlist( [clk, rst, led] )
width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
count = vast.Reg('count', width=width)
assign = vast.Assign(
vast.Lvalue(vast.Identifier('led')),
vast.Rvalue(
vast.Partselect(
vast.Identifier('count'), # count
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
senslist = vast.SensList([ sens ])
assign_count_true = vast.NonblockingSubstitution(
vast.Lvalue(vast.Identifier('count')),
vast.Rvalue(vast.IntConst('0')))
if0_true = vast.Block([ assign_count_true ])
# (count + 1) * 2
count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
cp1_times_2 = vast.Times(count_plus_1, vast.IntConst('2'))
cp1t2_plus_1 = vast.Plus(cp1_times_2, vast.IntConst('1'))
assign_count_false = vast.NonblockingSubstitution(
vast.Lvalue(vast.Identifier('count')),
vast.Rvalue(cp1t2_plus_1))
if0_false = vast.Block([ assign_count_false ])
if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
statement = vast.Block([ if0 ])
always = vast.Always(senslist, statement)
items = []
items.append(count)
items.append(assign)
items.append(always)
ast = vast.ModuleDef("top", params, ports, items)
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)
assert(expected == rslt)
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:54，代码来源:test_ast_always.py
示例7: test_led
def test_led():
led_module = led.mkLed()
led_code = led_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == led_code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:12，代码来源:test_led.py
示例8: test_led
def test_led():
modules = led.mkThread()
code = ''.join([ m.to_verilog() for m in modules.values() ])
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:12，代码来源:test_led.py
示例9: test_bram
def test_bram():
bram_module = bram.mkTop()
bram_code = bram_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == bram_code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:12，代码来源:test_bram.py
示例10: test_led
def test_led():
test_module = instance_noname_args.mkTop()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:12，代码来源:test_instance_noname_args.py
示例11: test
def test():
test_module = submodule_read_verilog_nested.mkTop()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:12，代码来源:test_submodule_read_verilog_nested.py
示例12: test
def test():
veriloggen.reset()
test_module = thread_intrinsic_method_prefix.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_thread_intrinsic_method_prefix.py
示例13: test_sort
def test_sort():
sort_module = sort.mkSimSort()
sort_code = sort_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert expected_code == sort_code
开发者ID:hoangt，项目名称:veriloggen，代码行数:13，代码来源:test_sort.py
示例14: test
def test():
veriloggen.reset()
test_module = regchain.mkRegChain(length=120)
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_regchain.py
示例15: test
def test():
veriloggen.reset()
test_module = thread_multibank_ram_rtl_connect.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_thread_multibank_ram_rtl_connect.py
示例16: test
def test():
veriloggen.reset()
modules = from_verilog_pycoram_object.mkUserlogic()
code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ])
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_from_verilog_pycoram_object.py
示例17: test
def test():
veriloggen.reset()
test_module = seq_delayed_eager_val_lazy_cond.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_seq_delayed_eager_val_lazy_cond.py
示例18: test
def test():
veriloggen.reset()
test_module = types_axi_read_lite.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_types_axi_read_lite.py
示例19: test
def test():
veriloggen.reset()
test_module = dataflow_two_outputs_mul.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_dataflow_two_outputs_mul.py
示例20: test
def test():
veriloggen.reset()
test_module = pipeline_acc_add_valid.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_pipeline_acc_add_valid.py
注：本文中的pyverilog.ast_code_generator.codegen.ASTCodeGenerator类示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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