本文整理汇总了Python中pyverilog.dataflow.dataflow_analyzer.VerilogDataflowAnalyzer类的典型用法代码示例。如果您正苦于以下问题：Python VerilogDataflowAnalyzer类的具体用法？Python VerilogDataflowAnalyzer怎么用？Python VerilogDataflowAnalyzer使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了VerilogDataflowAnalyzer类的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的Python代码示例。
示例1: test
def test():
filelist = [codedir + 'reset.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
开发者ID:hoangt，项目名称:Pyverilog-1，代码行数:14，代码来源:test_reset.py
示例2: test
def test():
filelist = [codedir + 'signed_task.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append(list(binddict.values())[0][0].tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:28，代码来源:test_dat_signed_task.py
示例3: test
def test():
filelist = [codedir + 'supply.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
开发者ID:hoangt，项目名称:Pyverilog-1，代码行数:31，代码来源:test_supply.py
示例4: main
def main():
INFO = "Verilog dataflow optimizer with Pyverilog"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_optimizer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
print('Directive:')
for dr in directives:
print(dr)
print('Term:')
for tk, tv in sorted(resolved_terms.items(), key=lambda x:len(x[0])):
print(tv.tostr())
print('Bind:')
for bk, bv in sorted(resolved_binddict.items(), key=lambda x:len(x[0])):
for bvi in bv:
print(bvi.tostr())
print('Const:')
for ck, cv in sorted(constlist.items(), key=lambda x:len(x[0])):
print(ck, cv)
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:58，代码来源:example_optimizer.py
示例5: test
def test():
filelist = [codedir + 'blocking.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append('Directive:\n')
for dr in sorted(directives, key=lambda x:str(x)):
output.append(str(dr))
output.append('\n')
output.append('Instance:\n')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
output.append(str((module, instname)))
output.append('\n')
output.append('Term:\n')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
output.append(tv.tostr())
output.append('\n')
output.append('Bind:\n')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
开发者ID:hoangt，项目名称:Pyverilog-1，代码行数:47，代码来源:test_blocking.py
示例6: test
def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist()
)
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert(expected == rslt)
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:40，代码来源:test_dat_partselect_assign.py
示例7: showVersion
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
开发者ID:hoangt，项目名称:Pyverilog-1，代码行数:31，代码来源:active_analyzer.py
示例8: main
def main():
INFO = "Code generator from Verilog dataflow definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_codegen.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("-o","--output",dest="outputfile",
default="helperthread.v",help="Output File name, Default=helperthread.v")
optparser.add_option("--clockname",dest="clockname",
default="CLK",help="Clock signal name")
optparser.add_option("--resetname",dest="resetname",
default="RST_X",help="Reset signal name")
optparser.add_option("--clockedge",dest="clockedge",
default="posedge",help="Clock signal edge")
optparser.add_option("--resetedge",dest="resetedge",
default="negedge",help="Reset signal edge")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
codegen = VerilogCodeGenerator(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
codegen.set_clock_info(options.clockname, options.clockedge)
codegen.set_reset_info(options.resetname, options.resetedge)
code = codegen.generateCode(options.searchtarget)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:75，代码来源:example_dataflow_codegen.py
示例9: main
def main():
INFO = "Dataflow walker"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_walker.py -t TOPMODULE -s TARGETSIGNAL file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
walker = VerilogDataflowWalker(options.topmodule, terms, binddict, resolved_terms,
resolved_binddict, constlist)
for target in options.searchtarget:
tree = walker.walkBind(target)
print('target: %s' % target)
print(tree.tostr())
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:63，代码来源:example_walker.py
示例10: main
def main():
INFO = "Active condition analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_active_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
active_conditions = canalyzer.getActiveConditions( signal )
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )
print('Active Cases: %s' % signal)
for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
print('FSM: %s' % fsm_sig)
for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
s = []
s.append('state: %d -> ' % state)
if active_condition: s.append(active_condition.tocode())
else: s.append('empty')
print(''.join(s))
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:63，代码来源:example_active_analyzer.py
示例11: main
def main():
INFO = "Active condition analyzer (Obsoluted)"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
print('Active Conditions: %s' % signal)
active_conditions = aanalyzer.getActiveConditions( signal )
print(sorted(active_conditions, key=lambda x:str(x)))
print('Changed Conditions')
changed_conditions = aanalyzer.getChangedConditions( signal )
print(sorted(changed_conditions, key=lambda x:str(x)))
print('Changed Condition Dict')
changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
print('Unchanged Conditions')
unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
print(sorted(unchanged_conditions, key=lambda x:str(x)))
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:65，代码来源:example_active_range.py
示例12: main
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("--graphformat",dest="graphformat",
default="png",help="Graph file format, Default=png")
optparser.add_option("--nograph",action="store_true",dest="nograph",
default=False,help="Non graph generation")
optparser.add_option("--nolabel",action="store_true",dest="nolabel",
default=False,help="State Machine Graph without Labels")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] + options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.'+options.graphformat, nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:71，代码来源:example_controlflow_analyzer.py
示例13: main
def main():
INFO = "Subset generator from Verilog dataflow definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_subset.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("--clockname",dest="clockname",
default="CLK",help="Clock signal name")
optparser.add_option("--resetname",dest="resetname",
default="RST_X",help="Reset signal name")
optparser.add_option("--clockedge",dest="clockedge",
default="posedge",help="Clock signal edge")
optparser.add_option("--resetedge",dest="resetedge",
default="negedge",help="Reset signal edge")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
subset = VerilogSubset(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
subset.set_clock_info(options.clockname, options.clockedge)
subset.set_reset_info(options.resetname, options.resetedge)
sub_binds, sub_terms = subset.getBindSourceSubset(options.searchtarget)
terms, parameter, assign, always_clockedge, always_combination = subset.getSubset(options.searchtarget)
for k, v in terms.items():
print(v.tocode())
for k, v in parameter.items():
print(v.tocode())
for k, v in assign.items():
for vv in v:
print(vv.tocode())
for k, v in always_clockedge.items():
for vv in v:
print(vv.tocode())
for k, v in always_combination.items():
for vv in v:
print(vv.tocode())
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:86，代码来源:example_subset.py
示例14: main
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
print('Directive:')
for dr in sorted(directives, key=lambda x:str(x)):
print(dr)
instances = analyzer.getInstances()
print('Instance:')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
print((module, instname))
if options.nobind:
print('Signal:')
signals = analyzer.getSignals()
for sig in signals:
print(sig)
print('Const:')
consts = analyzer.getConsts()
for con in consts:
print(con)
else:
terms = analyzer.getTerms()
print('Term:')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
print(tv.tostr())
binddict = analyzer.getBinddict()
print('Bind:')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
print(bvi.tostr())
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:75，代码来源:example_dataflow_analyzer.py
示例15: main
def main():
INFO = "Graph generator from dataflow"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_graphgen.py -t TOPMODULE -s TARGETSIGNAL file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("-o","--output",dest="outputfile",
default="out.png",help="Graph file name, Default=out.png")
optparser.add_option("--identical",action="store_true",dest="identical",
default=False,help="# Identical Laef, Default=False")
optparser.add_option("--walk",action="store_true",dest="walk",
default=False,help="Walk contineous signals, Default=False")
optparser.add_option("--step",dest="step",type='int',
default=1,help="# Search Steps, Default=1")
optparser.add_option("--reorder",action="store_true",dest="reorder",
default=False,help="Reorder the contineous tree, Default=False")
optparser.add_option("--delay",action="store_true",dest="delay",
default=False,help="Inset Delay Node to walk Regs, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
graphgen = VerilogGraphGenerator(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, options.outputfile)
for target in options.searchtarget:
graphgen.generate(target, walk=options.walk, identical=options.identical,
step=options.step, reorder=options.reorder, delay=options.delay)
graphgen.draw()
开发者ID:MayaMS，项目名称:Pyverilog，代码行数:76，代码来源:example_graphgen.py
注：本文中的pyverilog.dataflow.dataflow_analyzer.VerilogDataflowAnalyzer类示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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