Using wire or reg with input or output in Verilog

Question

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

question from:https://stackoverflow.com/questions/5360508/using-wire-or-reg-with-input-or-output-in-verilog

Answer 1

reg and wire specify how the object will be assigned and are therefore only meaningful for outputs.

If you plan to assign your output in sequential code,such as within an always block, declare it as a reg (which really is a misnomer for "variable" in Verilog). Otherwise, it should be a wire, which is also the default.