void EmitterAARCH64::emitRelOpImm(
        unsigned opcode, Register dest, Register src1, RegValue src2imm, codeGen &gen, bool s)
{
    //Register src2 = gen.rs()->allocateRegister(gen, true);
    Register src2 = gen.rs()->getScratchRegister(gen);
    emitLoadConst(src2, src2imm, gen);

    // CMP is an alias to SUBS;
    // dest here has src1-src2, which it's not important because the flags are
    // used for the comparison, not the subtration value.
    // Besides that dest must contain 1 for true or 0 for false, and the content
    // of dest is gonna be changed as follow.
    insnCodeGen::generateAddSubShifted(gen, insnCodeGen::Sub, 0, 0, src2, src1, dest, true);

    // make dest = 1, meaning true
    insnCodeGen::loadImmIntoReg<Address>(gen, dest, 0x1);

    // insert conditional jump to skip dest=0 in case the comparison resulted true
    // therefore keeping dest=1
    insnCodeGen::generateConditionalBranch(gen, 8, opcode, s);

    // make dest = 0, in case it fails the branch
    insnCodeGen::loadImmIntoReg<Address>(gen, dest, 0x0);

    gen.rs()->freeRegister(src2);
    gen.markRegDefined(dest);
}

void EmitterAARCH64::emitLoadOrigRegRelative(
        Register dest, Address offset, Register base, codeGen &gen, bool deref)
{

    gen.markRegDefined(dest);

    // either load the address or the contents at that address
    if(deref)
    {
        Register scratch = gen.rs()->getScratchRegister(gen);
        assert(scratch);
        gen.markRegDefined(scratch);
        // load the stored register 'base' into scratch
        insnCodeGen::generateMove(gen, scratch, base, true);
        // move offset(%scratch), %dest
        insnCodeGen::generateMemAccess(gen, insnCodeGen::Load, dest,
            scratch, offset, /*size==8?true:false*/4, insnCodeGen::Offset);
    }
    else
    {
        // load the stored register 'base' into dest
        insnCodeGen::generateMove(gen, dest, base, true);
        // add $offset, %dest
        emitImm(plusOp, dest, offset, dest, gen, false);
    }
}

bool insnCodeGen::modifyCall(Address targetAddr, NS_x86::instruction &insn, codeGen &gen) {
   // If we're within a 32-bit displacement, we reuse the original call. 
   // Otherwise we say "welp, sucks to be us", strip any prefixes, 
   // and do a 64-bit long thang

   const unsigned char *origInsn = insn.ptr();
   unsigned insnType = insn.type();
   codeBufIndex_t cur = gen.getIndex();

   // Let's try copying prefixes

   GET_PTR(newInsn, gen);
   copy_prefixes_nosize(origInsn, newInsn, insnType);
   SET_PTR(newInsn, gen);

   // If we're within 32-bits, then okay; otherwise rewind and use
   // 64-bit
   long disp = (targetAddr - (gen.currAddr() + CALL_REL32_SZ));
   if (is_disp32(disp)) {
      insnCodeGen::generateCall(gen, gen.currAddr(), targetAddr);
      return true;
   }

   // Otherwise suck monkey
   gen.setIndex(cur);
   insnCodeGen::generateCall(gen, gen.currAddr(), targetAddr);
   
   return true;
}

// Could be a lot smarter here...
bool InstWidgetPatch::apply(codeGen &gen, CodeBuffer *) {
   relocation_cerr << "\t\t InstWidgetPatch::apply " << this << " /w/ tramp " << tramp << endl;

   gen.registerInstrumentation(tramp, gen.currAddr());
   bool ret = tramp->generateCode(gen, gen.currAddr());
   return ret;
}

void EmitterAARCH64::emitLoadOrigRegister(Address register_num, Register destination, codeGen &gen)
{
    int offset = TRAMP_GPR_OFFSET(gen.width());
    // its on the stack so load it.
    // #sasha could it not be on the stack?
    insnCodeGen::restoreRegister(gen, destination, offset + (register_num * gen.width()),
            insnCodeGen::Offset);
}

void BinaryEdit::addTrap(Address from, Address to, codeGen &gen) {
   gen.invalidate();
   gen.allocate(4);
   gen.setAddrSpace(this);
   gen.setAddr(from);
   insnCodeGen::generateTrap(gen);
   trapMapping.addTrapMapping(from, to, true);
   springboard_cerr << "Generated springboard trap " << hex << from << "->" << to << dec << endl;
}

bool PCWidget::PCtoReturnAddr(const codeGen &templ, const RelocBlock *t, CodeBuffer &buffer) {
  if(templ.addrSpace()->proc()) {
    std::vector<unsigned char> newInsn;
#if defined(arch_x86_64)
    codeGen gen(16);
    Address RIP = addr_ + insn_.size();
    insnCodeGen::generatePush64(gen, RIP);
    buffer.addPIC(gen, tracker(t));
#elif defined(arch_x86)
    newInsn.push_back(0x68); // push
    Address EIP = addr_ + insn_.size();
    unsigned char *tmp = (unsigned char *) &EIP;
    newInsn.insert(newInsn.end(),
		   tmp,
		   tmp+sizeof(unsigned int));
    buffer.addPIC(newInsn, tracker(t));
#else
    // We want to get a value into LR, which is the return address.
    // Fun for the whole family... we need a spare register. Argh!

    codeGen gen(16);
    gen.applyTemplate(templ);
    // Must be in LR
    instPoint *point = templ.point();
    // If we do not have a point then we have to invent one
    if (!point || 
	(point->type() != instPoint::PreInsn &&
	 point->insnAddr() != addr())) {
      point = instPoint::preInsn(t->func(), t->block(), addr(), insn_, true);
    }
    assert(point);
    
    registerSpace *rs = registerSpace::actualRegSpace(point);
    gen.setRegisterSpace(rs);
    int stackSize = 0;
    pdvector<Register> freeReg;
    pdvector<Register> excludeReg;
    
    Address origRet = addr() + insn_.size();
    Register scratch = gen.rs()->getScratchRegister(gen, true);
    if (scratch == REG_NULL) {
      stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg);
      assert(stackSize == 1);
      scratch = freeReg[0];
    }
    insnCodeGen::loadImmIntoReg(gen, scratch, origRet);
    insnCodeGen::generateMoveToLR(gen, scratch);
    buffer.addPIC(gen, tracker(t));
#endif
  }
  else {
    IPPatch *newPatch = new IPPatch(IPPatch::Push, addr_, insn_, t->block(), t->func());
    buffer.addPatch(newPatch, tracker(t));
  }	
   
  return true;
}

void SpringboardBuilder::generateBranch(Address from, Address to, codeGen &gen) {
  gen.invalidate();
  gen.allocate(16);

  gen.setAddrSpace(addrSpace_);
  gen.setAddr(from);

  insnCodeGen::generateBranch(gen, from, to);

  springboard_cerr << "Generated springboard branch " << hex << from << "->" << to << dec << endl;
}

bool RelDataPatch::apply(codeGen &gen, CodeBuffer *) {
  instruction ugly_insn(orig_insn.ptr(), (gen.width() == 8));
  instPoint *point = gen.point();
  if (!point || (point->type() != instPoint::PreInsn && point->insnAddr() != orig)) {
      point = instPoint::preInsn(func, block, orig, orig_insn, true);
  }
  registerSpace *rs = registerSpace::actualRegSpace(point);
  gen.setRegisterSpace(rs);

  if (!insnCodeGen::modifyData(target_addr, ugly_insn, gen)) {
      relocation_cerr << "RelDataPatch returned false from modifyData (original address: " << std::hex<< orig << ")" <<endl;
      return false;
  }
  return true;
}

//#sasha Fix parameters number
void EmitterAARCH64::emitGetParam(
        Register dest, Register param_num,
        instPoint::Type pt_type, opCode op,
        bool addr_of, codeGen &gen)
{
    registerSlot *regSlot = NULL;
    switch (op) {
        case getParamOp:
            if(param_num <= 3) {
                // param_num is 0..8 - it's a parameter number, not a register
                regSlot = (*(gen.rs()))[registerSpace::r0 + param_num];
                break;

            } else {
                assert(0);
            }
            break;
        default:
            assert(0);
            break;
    } // end of swich(op)

    assert(regSlot);
    Register reg = regSlot->number;

    //return reg;
}

bool PCWidget::PCtoReg(const codeGen &templ, const RelocBlock *t, CodeBuffer &buffer) {
  bool ignored;
  Register reg = convertRegID(a_.reg(), ignored);

  if(templ.addrSpace()->proc()) {
#if defined(arch_x86) || defined(arch_x86_64)
     std::vector<unsigned char> newInsn;
     newInsn.push_back(static_cast<unsigned char>(0xb8 + reg));
     // MOV family, destination of the register encoded by
     // 'reg', source is an Iv immediate
     
     Address EIP = addr_ + insn_->size();
     unsigned char *tmp = (unsigned char *) &EIP;
     newInsn.insert(newInsn.end(),
                    tmp,
                    tmp + sizeof(unsigned int));
     buffer.addPIC(newInsn, tracker(t));
#else
     // Move immediate to register?
     codeGen gen(16);
     insnCodeGen::loadImmIntoReg(gen, reg, addr_);
     buffer.addPIC(gen, tracker(t));
#endif
  }
  else {
    IPPatch *newPatch = new IPPatch(IPPatch::Reg, addr_, reg, thunkAddr_, insn_, t->block(), t->func());
    buffer.addPatch(newPatch, tracker(t));
  }
  return true;
}

bool CFPatch::handleTOCUpdate(codeGen &gen) {
  // Annoying, pain in the butt case...

  assert(target->type() == TargetInt::BlockTarget);
  Target<block_instance *> *t = static_cast<Target<block_instance *> *>(target);


  if (type == Jump)
    return gen.codeEmitter()->emitTOCJump(t->t(), gen);
  else if (type == Call)
    return gen.codeEmitter()->emitTOCCall(t->t(), gen);
  else {
    assert(0);
    return false;
  }
}

void insnCodeGen::generateInterFunctionBranch(codeGen &gen,
                                              Address from,
                                              Address to,
                                              bool link) {
    long disp = to - from;

    if (ABS(disp) <= MAX_BRANCH) {
        // We got lucky...
        return generateBranch(gen, from, to);
    }
    instPoint *point = gen.point();
    if (!point) {
        return generateBranchViaTrap(gen, from, to, false);
    }
    assert(point);
    bitArray liveRegs = point->liveRegisters();
    if (liveRegs[registerSpace::ctr] == true) 
    {
	fprintf(stderr, " COUNT REGISTER NOT AVAILABLE. We cannot insterument this point. skipping ...\n");
	return;
    }

    insnCodeGen::loadImmIntoReg(gen, 0, to);
    insnCodeGen::generateMoveToCR(gen, 0);
    // And branch to CTR
    instruction btctr(link ? BCTRLraw : BCTRraw);
    insnCodeGen::generate(gen,btctr);
}

bool CodeBuffer::BufferElement::generate(CodeBuffer *buf,
                                         codeGen &gen,
                                         int &shift,
                                         bool &regenerate) {
   codeBufIndex_t start = gen.getIndex();
   addr_ = gen.currAddr();

   // By definition, labels can only apply to the start of a
   // BufferElement. Update it now with our current address.
   buf->updateLabel(labelID_, addr_ - gen.startAddr(), regenerate);

   // Get the easy bits out of the way
   gen.copy(buffer_);

   if (patch_) {
      // Now things get interesting
      if (!patch_->apply(gen, buf)) {
	relocation_cerr << "Patch failed application, ret false" << endl;
         return false;
      }
   }
   unsigned newSize = gen.getDisplacement(start, gen.getIndex());
   if (newSize > size_) {
      shift += newSize - size_;
      size_ = newSize;
      regenerate = true;
   }
   else {
      gen.fill(size_ - newSize, codeGen::cgNOP);
   }
#if 0
   else if (newSize < size_) {

void SpringboardBuilder::generateBranch(Address from, Address to, codeGen &gen) {
  gen.invalidate();
  gen.allocate(16);

  gen.setAddrSpace(addrSpace_);
  gen.setAddr(from);

  insnCodeGen::generateBranch(gen, from, to);

  springboard_cerr << "Generated springboard branch " << hex << from << "->" << to << dec << endl;

#if 0
#include "InstructionDecoder.h"
    using namespace Dyninst::InstructionAPI;
    Address base = 0;
    InstructionDecoder deco(gen.start_ptr(),gen.size(),Arch_aarch64);
    Instruction::Ptr insn = deco.decode();
    while(base<gen.used()+5) {
        std::stringstream rawInsn;
        unsigned idx = insn->size();
        while(idx--) rawInsn << hex << setfill('0') << setw(2) << (unsigned int) insn->rawByte(idx);

        cerr << "\t" << hex << base << ":   " << rawInsn.str() << "   "
            << insn->format(base) << dec << endl;
        base += insn->size();
        insn = deco.decode();
    }
#endif
}

bool CFPatch::applyPLT(codeGen &gen, CodeBuffer *) {
   // We should try and keep any prefixes that were on the instruction. 
   // However... yeah, right. I'm not that good with x86. So instead
   // I'm copying the code from emitCallInstruction...
      
   if (target->type() != TargetInt::BlockTarget) {
      return false;
   }
   // And can only handle calls right now. That's a TODO...
   if (type != Call &&
       type != Jump) {
      return false;
   }

   relocation_cerr << "\t\t\t ApplyPLT..." << endl;

   Target<block_instance *> *t = static_cast<Target<block_instance *> *>(target);
   block_instance *tb = t->t();

   // Set caller in codegen structure
   gen.setFunction(const_cast<func_instance *>(func));

   // We can (for now) only jump to functions
   func_instance *callee = tb->entryOfFunc();
   if (!callee) {
      return false;
   }

   // We need a RegisterSpace for this. Amusingly,
   // we want to use the RegisterSpace corresponding to the
   // entry of the callee, as it doesn't matter what's live
   // here. 
   instPoint *calleeEntry = instPoint::funcEntry(callee);
   gen.setRegisterSpace(registerSpace::actualRegSpace(calleeEntry));

   if (type == Call) 
      gen.codeEmitter()->emitPLTCall(callee, gen);
   else if (type == Jump)
      gen.codeEmitter()->emitPLTJump(callee, gen);
   else
      assert(0);

   return true;
}

void insnCodeGen::generate(codeGen &gen, instruction&insn) {
#if defined(endian_mismatch)
  // Writing an instruction.  Convert byte order if necessary.
  unsigned raw = swapBytesIfNeeded(insn.asInt());
#else
  unsigned raw = insn.asInt();
#endif
  
  gen.copy(&raw, sizeof(unsigned));
}

bool PaddingPatch::apply(codeGen &gen, CodeBuffer *) {
   //TODO: find smarter way of telling that we're doing CFG modification, 
   // in which case we don't want to add padding in between blocks
   if (BPatch_defensiveMode != block_->obj()->hybridMode()) {
      bpwarn("WARNING: Disabling post-call block padding %s[%d]\n",FILE__,__LINE__);
      return true;
   }
   //malware_cerr << "PaddingPatch::apply, addr [" << hex << block_->end() << "]["<< gen.currAddr() << "], size " << size_ << ", registerDefensive " << (registerDefensive_ ? "<true>" : "<false>") << dec << endl;
   if (noop_) {
      gen.fill(size_, codeGen::cgNOP);
   }
   else if ( 0 == (size_ % 2) ) {
      gen.fill(size_, codeGen::cgIllegal);
   } else {
      gen.fill(size_, codeGen::cgTrap);
   }
   //cerr << "\t After filling, current addr " << hex << gen.currAddr() << dec << endl;
   //gen.fill(10, codeGen::cgNOP);
   return true;
}

void insnCodeGen::generateBranch(codeGen &gen,
                                 Address fromAddr, Address toAddr)
{
  GET_PTR(insn, gen);
  long disp;

  disp = toAddr - (fromAddr + 2);
  if (is_disp8(disp)) {
     *insn++ = 0xEB;
     *((signed char*) insn) = (signed char) disp;
     insn += sizeof(signed char);
     SET_PTR(insn, gen);
     return;
  }
  /*  
  disp = toAddr - (fromAddr + 4);
  if (is_disp16(disp) && gen.addrSpace()->getAddressWidth() != 8) {
     *insn++ = 0x66;
     *insn++ = 0xE9;
     *((signed short*) insn) = (signed short) disp;
     insn += sizeof(signed short);
     SET_PTR(insn, gen);
     return;
  }
  */
  disp = toAddr - fromAddr;
  if (is_disp32(disp) || gen.addrSpace()->getAddressWidth() == 4) {
     generateBranch(gen, disp);
     return;
  }
  
  if(gen.addrSpace()->getAddressWidth() == 8)
  {
      generateBranch64(gen, toAddr);
  }
  else
  {
      generateBranch32(gen, toAddr);
  }
  return;
}

bool CFPatch::isPLT(codeGen &gen) {
   if (!gen.addrSpace()->edit()) return false;

   // We need to PLT if we're in two different 
   // AddressSpaces - the current codegen and
   // the target.

   // First check the target type.
   if (target->type() != TargetInt::BlockTarget) {
      // Either a RelocBlock (which _must_ be local)
      // or an Address (which has to be local to be
      // meaningful); neither reqs PLT
      return false;
   }

   Target<block_instance *> *t = static_cast<Target<block_instance *> *>(target);
   block_instance *tb = t->t();
   if (tb->proc() != gen.addrSpace())
      return true;
   else
      return false;
}