本文整理汇总了C++中tr::Register类的典型用法代码示例。如果您正苦于以下问题:C++ Register类的具体用法?C++ Register怎么用?C++ Register使用的例子?那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了Register类的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: if
TR::Register *IA32LinkageUtils::pushLongArg(
TR::Node *child,
TR::CodeGenerator *cg)
{
TR::Register *pushRegister;
if (child->getRegister() == NULL)
{
if (child->getOpCode().isLoadConst())
{
TR_X86OpCodes pushOp;
int32_t highValue = child->getLongIntHigh();
if (highValue >= -128 && highValue <= 127)
{
pushOp = PUSHImms;
}
else
{
pushOp = PUSHImm4;
}
generateImmInstruction(pushOp, child, highValue, cg);
int32_t lowValue = child->getLongIntLow();
if (lowValue >= -128 && lowValue <= 127)
{
pushOp = PUSHImms;
}
else
{
pushOp = PUSHImm4;
}
generateImmInstruction(pushOp, child, lowValue, cg);
cg->decReferenceCount(child);
return NULL;
}
else if (child->getOpCodeValue() == TR::dbits2l &&
!child->normalizeNanValues() &&
child->getReferenceCount() == 1)
{
pushRegister = pushDoubleArg(child->getFirstChild(), cg);
cg->decReferenceCount(child);
return pushRegister;
}
else if (child->getOpCode().isMemoryReference() &&
child->getReferenceCount() == 1)
{
TR::MemoryReference *lowMR = generateX86MemoryReference(child, cg);
generateMemInstruction(PUSHMem, child, generateX86MemoryReference(*lowMR,4, cg), cg);
generateMemInstruction(PUSHMem, child, lowMR, cg);
lowMR->decNodeReferenceCounts(cg);
return NULL;
}
}
pushRegister = cg->evaluate(child);
generateRegInstruction(PUSHReg, child, pushRegister->getHighOrder(), cg);
generateRegInstruction(PUSHReg, child, pushRegister->getLowOrder(), cg);
cg->decReferenceCount(child);
return pushRegister;
}
开发者ID:LinHu2016,项目名称:omr,代码行数:60,代码来源:IA32LinkageUtils.cpp
示例2: defined
rcount_t
OMR::CodeGenerator::incReferenceCount(TR::Node *node)
{
TR::Register *reg = node->getRegister();
#ifdef J9_PROJECT_SPECIFIC
#if defined(TR_TARGET_S390)
if (reg && reg->getOpaquePseudoRegister())
{
TR_OpaquePseudoRegister * pseudoReg = reg->getOpaquePseudoRegister();
TR_StorageReference * pseudoRegStorageReference = pseudoReg->getStorageReference();
TR_ASSERT(pseudoRegStorageReference, "the pseudoReg should have a non-null storage reference\n");
pseudoRegStorageReference->incrementTemporaryReferenceCount();
}
#endif
#endif
rcount_t count = node->incReferenceCount();
if (self()->comp()->getOptions()->getTraceCGOption(TR_TraceCGEvaluation))
{
self()->getDebug()->printNodeEvaluation(node, "++ ", reg);
}
return count;
}
开发者ID:TianyuZuo,项目名称:omr,代码行数:26,代码来源:NodeEvaluation.cpp
示例3: cg
void TR::ARM64MemSrc1Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
TR::Machine *machine = cg()->machine();
TR::MemoryReference *mref = getMemoryReference();
TR::Register *sourceVirtual = getSource1Register();
if (getDependencyConditions())
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
sourceVirtual->block();
mref->assignRegisters(this, cg());
sourceVirtual->unblock();
mref->blockRegisters();
TR::RealRegister *assignedRegister = sourceVirtual->getAssignedRealRegister();
if (assignedRegister == NULL)
{
assignedRegister = machine->assignOneRegister(this, sourceVirtual);
}
mref->unblockRegisters();
setSource1Register(assignedRegister);
if (getDependencyConditions())
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindToBeAssigned, cg());
}
开发者ID:LinHu2016,项目名称:omr,代码行数:26,代码来源:ARM64Instruction.cpp
示例4: decFutureUseCounts
void decFutureUseCounts(uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
for (uint32_t i = 0; i< numberOfRegisters; i++)
{
TR::Register *virtReg = _dependencies[i].getRegister();
virtReg->decFutureUseCount();
}
}
开发者ID:hangshao0,项目名称:omr,代码行数:9,代码来源:OMRRegisterDependency.hpp
示例5:
// also handles ilload
TR::Register *OMR::X86::AMD64::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *sourceMR = generateX86MemoryReference(node, cg);
TR::Register *reg = TR::TreeEvaluator::loadMemory(node, sourceMR, TR_RematerializableLong, node->getOpCode().isIndirect(), cg);
reg->setMemRef(sourceMR);
node->setRegister(reg);
sourceMR->decNodeReferenceCounts(cg);
return reg;
}
开发者ID:dinogun,项目名称:omr,代码行数:11,代码来源:OMRTreeEvaluator.cpp
示例6: switch
TR::Register* OMR::X86::TreeEvaluator::SIMDsplatsEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
TR::Node* childNode = node->getChild(0);
TR::Register* childReg = cg->evaluate(childNode);
TR::Register* resultReg = cg->allocateRegister(TR_VRF);
switch (node->getDataType())
{
case TR::VectorInt32:
generateRegRegInstruction(MOVDRegReg4, node, resultReg, childReg, cg);
generateRegRegImmInstruction(PSHUFDRegRegImm1, node, resultReg, resultReg, 0x00, cg); // 00 00 00 00 shuffle xxxA to AAAA
break;
case TR::VectorInt64:
if (TR::Compiler->target.is32Bit())
{
TR::Register* tempVectorReg = cg->allocateRegister(TR_VRF);
generateRegRegInstruction(MOVDRegReg4, node, tempVectorReg, childReg->getHighOrder(), cg);
generateRegImmInstruction(PSLLQRegImm1, node, tempVectorReg, 0x20, cg);
generateRegRegInstruction(MOVDRegReg4, node, resultReg, childReg->getLowOrder(), cg);
generateRegRegInstruction(PORRegReg, node, resultReg, tempVectorReg, cg);
cg->stopUsingRegister(tempVectorReg);
}
else
{
generateRegRegInstruction(MOVQRegReg8, node, resultReg, childReg, cg);
}
generateRegRegImmInstruction(PSHUFDRegRegImm1, node, resultReg, resultReg, 0x44, cg); // 01 00 01 00 shuffle xxBA to BABA
break;
case TR::VectorFloat:
generateRegRegImmInstruction(PSHUFDRegRegImm1, node, resultReg, childReg, 0x00, cg); // 00 00 00 00 shuffle xxxA to AAAA
break;
case TR::VectorDouble:
generateRegRegImmInstruction(PSHUFDRegRegImm1, node, resultReg, childReg, 0x44, cg); // 01 00 01 00 shuffle xxBA to BABA
break;
default:
if (cg->comp()->getOption(TR_TraceCG))
traceMsg(cg->comp(), "Unsupported data type, Node = %p\n", node);
TR_ASSERT(false, "Unsupported data type");
break;
}
node->setRegister(resultReg);
cg->decReferenceCount(childNode);
return resultReg;
}
开发者ID:dinogun,项目名称:omr,代码行数:45,代码来源:SIMDTreeEvaluator.cpp
示例7: generateRegisterDependencyConditions
// Create a NoReg dependency for each child of a call that has been evaluated into a register.
// Ignore children that do not have a register since their live range should not persist outside of
// the helper call stream.
//
TR::RegisterDependencyConditions *TR_OutlinedInstructions::formEvaluatedArgumentDepList()
{
int32_t i, c=0;
for (i=_callNode->getFirstArgumentIndex(); i<_callNode->getNumChildren(); i++)
{
TR::Register *reg = _callNode->getChild(i)->getRegister();
if (reg)
{
TR::RegisterPair *regPair = reg->getRegisterPair();
c += regPair? 2 : 1;
}
}
TR::RegisterDependencyConditions *depConds = NULL;
if (c)
{
TR::Machine *machine = _cg->machine();
depConds = generateRegisterDependencyConditions(0, c, _cg);
for (i=_callNode->getFirstArgumentIndex(); i<_callNode->getNumChildren(); i++)
{
TR::Register *reg = _callNode->getChild(i)->getRegister();
if (reg)
{
TR::RegisterPair *regPair = reg->getRegisterPair();
if (regPair)
{
depConds->addPostCondition(regPair->getLowOrder(), TR::RealRegister::NoReg, _cg);
depConds->addPostCondition(regPair->getHighOrder(), TR::RealRegister::NoReg, _cg);
}
else
{
depConds->addPostCondition(reg, TR::RealRegister::NoReg, _cg);
}
}
}
depConds->stopAddingConditions();
}
return depConds;
}
开发者ID:TianyuZuo,项目名称:omr,代码行数:48,代码来源:OutlinedInstructions.cpp
示例8: self
TR::Register *
OMR::X86::I386::CodeGenerator::longClobberEvaluate(TR::Node *node)
{
TR_ASSERT(node->getOpCode().is8Byte(), "assertion failure");
if (node->getReferenceCount() > 1)
{
TR::Register *temp = self()->evaluate(node);
TR::Register *lowReg = self()->allocateRegister();
TR::Register *highReg = self()->allocateRegister();
TR::RegisterPair *longReg = self()->allocateRegisterPair(lowReg, highReg);
generateRegRegInstruction(MOV4RegReg, node, lowReg, temp->getLowOrder(), self());
generateRegRegInstruction(MOV4RegReg, node, highReg, temp->getHighOrder(), self());
return longReg;
}
else
{
return self()->evaluate(node);
}
}
开发者ID:lmaisons,项目名称:omr,代码行数:20,代码来源:OMRCodeGenerator.cpp
示例9: self
void OMR::X86::Instruction::clobberRegsForRematerialisation()
{
// We assume most instructions modify all registers that appear in their
// postconditions, with a few exceptions.
//
if ( self()->cg()->enableRematerialisation()
&& self()->getDependencyConditions()
&& (self()->getOpCodeValue() != ASSOCREGS) // reg associations aren't really instructions, so they don't modify anything
&& (self()->getOpCodeValue() != LABEL) // labels must already be handled properly for a variety of reasons
&& (!self()->getOpCode().isShiftOp())
&& (!self()->getOpCode().isRotateOp()) // shifts and rotates often have a postcondition on ecx but don't clobber it
){
// Check the live discardable register list to see if this is the first
// instruction that kills the rematerialisable range of a register.
//
TR::ClobberingInstruction *clob = NULL;
TR_X86RegisterDependencyGroup *post = self()->getDependencyConditions()->getPostConditions();
for (uint32_t i = 0; i < self()->getDependencyConditions()->getNumPostConditions(); i++)
{
TR::Register *reg = post->getRegisterDependency(i)->getRegister();
if (reg->isDiscardable())
{
if (!clob)
{
clob = new (self()->cg()->trHeapMemory()) TR::ClobberingInstruction(self(), self()->cg()->trMemory());
self()->cg()->addClobberingInstruction(clob);
}
clob->addClobberedRegister(reg);
self()->cg()->removeLiveDiscardableRegister(reg);
self()->cg()->clobberLiveDependentDiscardableRegisters(clob, reg);
if (debug("dumpRemat"))
diagnostic("---> Clobbering %s discardable postcondition register %s at instruction %s\n",
self()->cg()->getDebug()->toString(reg->getRematerializationInfo()),
self()->cg()->getDebug()->getName(reg),
self()->cg()->getDebug()->getName(self()));
}
}
}
}
开发者ID:TianyuZuo,项目名称:omr,代码行数:41,代码来源:OMRInstruction.cpp
示例10: if
rcount_t
OMR::CodeGenerator::decReferenceCount(TR::Node * node)
{
TR::Register *reg = node->getRegister();
// restricted registers go dead when ref count==2 because
// their ref count was inced in prepareNodeForInstructionSelection
if ((node->getReferenceCount() == 1) &&
reg && self()->getLiveRegisters(reg->getKind()))
{
TR_ASSERT(reg->isLive() ||
(diagnostic("\n*** Error: Register %s for node "
"[%s] died prematurely\n",
reg->getRegisterName(self()->comp()),
node->getName(self()->comp()->getDebug())),
0),
"Node %s register should be live",self()->getDebug()->getName(node));
TR_LiveRegisterInfo *liveRegister = reg->getLiveRegisterInfo();
TR::Register *pair = reg->getRegisterPair();
if (pair)
{
pair->getHighOrder()->getLiveRegisterInfo()->decNodeCount();
pair->getLowOrder()->getLiveRegisterInfo()->decNodeCount();
}
if (liveRegister && liveRegister->decNodeCount() == 0)
{
// The register is now dead
//
self()->getLiveRegisters(reg->getKind())->registerIsDead(reg);
}
}
#ifdef J9_PROJECT_SPECIFIC
#if defined(TR_TARGET_S390)
if (reg && reg->getOpaquePseudoRegister())
{
TR_OpaquePseudoRegister *pseudoReg = reg->getOpaquePseudoRegister();
TR_StorageReference *storageReference = pseudoReg->getStorageReference();
TR_ASSERT(storageReference,"the pseudoReg should have a non-null storage reference\n");
storageReference->decrementTemporaryReferenceCount();
if (node->getReferenceCount() == 1)
{
storageReference->decOwningRegisterCount();
if (self()->traceBCDCodeGen())
traceMsg(self()->comp(),"\tdecrement owningRegisterCount %d->%d on ref #%d (%s) for reg %s as %s (%p) refCount == 1 (going to 0)\n",
storageReference->getOwningRegisterCount()+1,
storageReference->getOwningRegisterCount(),
storageReference->getReferenceNumber(),
self()->getDebug()->getName(storageReference->getSymbol()),
self()->getDebug()->getName(reg),
node->getOpCode().getName(),
node);
}
}
else if (node->getOpCode().hasSymbolReference() && node->getSymbolReference() && node->getSymbolReference()->isTempVariableSizeSymRef())
{
TR_ASSERT(false,"tempMemSlots should only be attached to pseudoRegisters and not node %p\n",node);
}
#endif
#endif
rcount_t count = node->decReferenceCount();
if (self()->comp()->getOptions()->getTraceCGOption(TR_TraceCGEvaluation))
{
self()->getDebug()->printNodeEvaluation(node, "-- ", reg);
}
return count;
}
开发者ID:TianyuZuo,项目名称:omr,代码行数:70,代码来源:NodeEvaluation.cpp
示例11: assignRegisters
void TR_OutlinedInstructions::assignRegisters(TR_RegisterKinds kindsToBeAssigned, TR::X86VFPSaveInstruction *vfpSaveInstruction)
{
if (hasBeenRegisterAssigned())
return;
// nested internal control flow assert:
_cg->setInternalControlFlowSafeNestingDepth(_cg->internalControlFlowNestingDepth());
// Create a dependency list on the first instruction in this stream that captures all
// current real register associations. This is necessary to get the register assigner
// back into its original state before the helper stream was processed.
//
TR::RegisterDependencyConditions *liveRealRegDeps = _cg->machine()->createDepCondForLiveGPRs();
_firstInstruction->setDependencyConditions(liveRealRegDeps);
#if 0
// If the outlined section jumps back to a section that's expecting a certain register
// state then add register dependencies on the exit branch to set that state.
//
if (_postDependencyMergeList)
{
TR::RegisterDependencyConditions *mergeDeps = _postDependencyMergeList->clone(_cg);
TR_ASSERT(_appendInstruction->getDependencyConditions() == NULL, "unexpected reg deps on OOL append instruction");
_appendInstruction->setDependencyConditions(mergeDeps);
TR_X86RegisterDependencyGroup *depGroup = mergeDeps->getPostConditions();
for (int32_t i=0; i<mergeDeps->getNumPostConditions(); i++)
{
TR::RegisterDependency *dependency = depGroup->getRegisterDependency(i);
TR::Register *virtReg = dependency->getRegister();
virtReg->incTotalUseCount();
virtReg->incFutureUseCount();
#ifdef DEBUG
// Ensure all register dependencies have been assigned.
//
TR_ASSERT(dependency->getRealRegister() != TR::RealRegister::NoReg, "unassigned merge dep register");
TR_ASSERT(virtReg->getAssignedRealRegister() == _cg->machine()->getX86RealRegister(dependency->getRealRegister()), "unexpected(?) register assignment");
#endif
}
}
#endif
// TODO:AMD64: Fix excessive register assignment exchanges in outlined instruction dispatch.
// Ensure correct VFP state at the start of the outlined instruction sequence.
//
generateVFPRestoreInstruction(comp()->getAppendInstruction(), vfpSaveInstruction, _cg);
// Link in the helper stream into the mainline code.
//
TR::Instruction *appendInstruction = comp()->getAppendInstruction();
appendInstruction->setNext(_firstInstruction);
_firstInstruction->setPrev(appendInstruction);
comp()->setAppendInstruction(_appendInstruction);
// Register assign the helper dispatch instructions.
//
_cg->doBackwardsRegisterAssignment(kindsToBeAssigned, _appendInstruction, appendInstruction);
// Returning to mainline, reset this counter
_cg->setInternalControlFlowSafeNestingDepth(0);
setHasBeenRegisterAssigned(true);
}
开发者ID:TianyuZuo,项目名称:omr,代码行数:69,代码来源:OutlinedInstructions.cpp
示例12: if
// Build arguments for system linkage dispatch.
//
int32_t TR::AMD64SystemLinkage::buildArgs(
TR::Node *callNode,
TR::RegisterDependencyConditions *deps)
{
TR::SymbolReference *methodSymRef = callNode->getSymbolReference();
TR::MethodSymbol *methodSymbol = methodSymRef->getSymbol()->castToMethodSymbol();
TR::RealRegister::RegNum noReg = TR::RealRegister::NoReg;
TR::RealRegister *espReal = machine()->getX86RealRegister(TR::RealRegister::esp);
int32_t firstNodeArgument = callNode->getFirstArgumentIndex();
int32_t lastNodeArgument = callNode->getNumChildren() - 1;
int32_t offset = 0;
int32_t sizeOfOutGoingArgs= 0;
uint16_t numIntArgs = 0,
numFloatArgs = 0;
int32_t first, last, direction;
int32_t numCopiedRegs = 0;
TR::Register *copiedRegs[TR::X86LinkageProperties::MaxArgumentRegisters];
if (getProperties().passArgsRightToLeft())
{
first = lastNodeArgument;
last = firstNodeArgument - 1;
direction = -1;
}
else
{
first = firstNodeArgument;
last = lastNodeArgument + 1;
direction = 1;
}
// If the dispatch is indirect we must add the VFT register to the preconditions
// so that it gets register assigned with the other preconditions to the call.
//
if (callNode->getOpCode().isIndirect())
{
TR::Node *vftChild = callNode->getFirstChild();
TR_ASSERT(vftChild->getRegister(), "expecting VFT child to be evaluated");
TR::RealRegister::RegNum scratchRegIndex = getProperties().getIntegerScratchRegister(1);
deps->addPreCondition(vftChild->getRegister(), scratchRegIndex, cg());
}
int32_t i;
for (i = first; i != last; i += direction)
{
TR::parmLayoutResult layoutResult;
TR::RealRegister::RegNum rregIndex = noReg;
TR::Node *child = callNode->getChild(i);
layoutParm(child, sizeOfOutGoingArgs, numIntArgs, numFloatArgs, layoutResult);
if (layoutResult.abstract & TR::parmLayoutResult::IN_LINKAGE_REG_PAIR)
{
// TODO: AMD64 SysV ABI might put a struct into a pair of linkage registerr
TR_ASSERT(false, "haven't support linkage_reg_pair yet.\n");
}
else if (layoutResult.abstract & TR::parmLayoutResult::IN_LINKAGE_REG)
{
TR_RegisterKinds regKind = layoutResult.regs[0].regKind;
uint32_t regIndex = layoutResult.regs[0].regIndex;
TR_ASSERT(regKind == TR_GPR || regKind == TR_FPR, "linkage registers includes TR_GPR and TR_FPR\n");
rregIndex = (regKind == TR_FPR) ? getProperties().getFloatArgumentRegister(regIndex): getProperties().getIntegerArgumentRegister(regIndex);
}
else
{
offset = layoutResult.offset;
}
TR::Register *vreg;
vreg = cg()->evaluate(child);
bool needsStackOffsetUpdate = false;
if (rregIndex != noReg)
{
// For NULL JNI reference parameters, it is possible that the NULL value will be evaluated into
// a different register than the child. In that case it is not necessary to copy the temporary scratch
// register across the call.
//
if ((child->getReferenceCount() > 1) &&
(vreg == child->getRegister()))
{
TR::Register *argReg = cg()->allocateRegister();
if (vreg->containsCollectedReference())
argReg->setContainsCollectedReference();
generateRegRegInstruction(TR::Linkage::movOpcodes(RegReg, movType(child->getDataType())), child, argReg, vreg, cg());
vreg = argReg;
copiedRegs[numCopiedRegs++] = vreg;
}
deps->addPreCondition(vreg, rregIndex, cg());
}
else
{
// Ideally, we would like to push rather than move
generateMemRegInstruction(TR::Linkage::movOpcodes(MemReg, fullRegisterMovType(vreg)),
child,
generateX86MemoryReference(espReal, offset, cg()),
vreg,
//.........这里部分代码省略.........
开发者ID:lmaisons,项目名称:omr,代码行数:101,代码来源:AMD64SystemLinkage.cpp
示例13: cg
TR::Register *
TR::AMD64SystemLinkage::buildVolatileAndReturnDependencies(
TR::Node *callNode,
TR::RegisterDependencyConditions *deps)
{
if (callNode->getOpCode().isIndirect())
{
TR::Node *vftChild = callNode->getFirstChild();
if (vftChild->getRegister() && (vftChild->getReferenceCount() > 1))
{
}
else
{
// VFT child dies here; decrement it early so it doesn't interfere with dummy regs.
cg()->recursivelyDecReferenceCount(vftChild);
}
}
TR_ASSERT(deps != NULL, "expected register dependencies");
// Figure out which is the return register.
//
TR::RealRegister::RegNum returnRegIndex;
TR_RegisterKinds returnKind;
switch (callNode->getDataType())
{
case TR::NoType:
returnRegIndex = TR::RealRegister::NoReg;
returnKind = TR_NoRegister;
break;
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Int64:
case TR::Address:
returnRegIndex = getProperties().getIntegerReturnRegister();
returnKind = TR_GPR;
break;
case TR::Float:
case TR::Double:
returnRegIndex = getProperties().getFloatReturnRegister();
returnKind = TR_FPR;
break;
case TR::Aggregate:
default:
TR_ASSERT(false, "Unrecognized call node data type: #%d", (int)callNode->getDataType());
break;
}
// Kill all non-preserved int and float regs besides the return register.
//
int32_t i;
TR::RealRegister::RegNum scratchIndex = getProperties().getIntegerScratchRegister(1);
for (i=0; i<getProperties().getNumVolatileRegisters(); i++)
{
TR::RealRegister::RegNum regIndex = getProperties()._volatileRegisters[i];
if (regIndex != returnRegIndex)
{
TR_RegisterKinds rk = (i < getProperties()._numberOfVolatileGPRegisters) ? TR_GPR : TR_FPR;
TR::Register *dummy = cg()->allocateRegister(rk);
deps->addPostCondition(dummy, regIndex, cg());
// Note that we don't setPlaceholderReg here. If this volatile reg is also volatile
// in the caller's linkage, then that flag doesn't matter much anyway. If it's preserved
// in the caller's linkage, then we don't want to set that flag because we want this
// use of the register to count as a "real" use, thereby motivating the prologue to
// preserve the register.
// A scratch register is necessary to call the native without a trampoline.
//
if (callNode->getOpCode().isIndirect() || (regIndex != scratchIndex))
cg()->stopUsingRegister(dummy);
}
}
#if defined (PYTHON) && 0
// Evict the preserved registers across the call
//
for (i=0; i<getProperties().getNumberOfPreservedGPRegisters(); i++)
{
TR::RealRegister::RegNum regIndex = getProperties()._preservedRegisters[i];
TR::Register *dummy = cg()->allocateRegister(TR_GPR);
deps->addPostCondition(dummy, regIndex, cg());
// Note that we don't setPlaceholderReg here. If this volatile reg is also volatile
// in the caller's linkage, then that flag doesn't matter much anyway. If it's preserved
// in the caller's linkage, then we don't want to set that flag because we want this
// use of the register to count as a "real" use, thereby motivating the prologue to
// preserve the register.
// A scratch register is necessary to call the native without a trampoline.
//
if (callNode->getOpCode().isIndirect() || (regIndex != scratchIndex))
//.........这里部分代码省略.........
开发者ID:lmaisons,项目名称:omr,代码行数:101,代码来源:AMD64SystemLinkage.cpp
示例14: stackMemoryRegion
int32_t TR::ARM64SystemLinkage::buildArgs(TR::Node *callNode,
TR::RegisterDependencyConditions *dependencies)
{
const TR::ARM64LinkageProperties &properties = getProperties();
TR::ARM64MemoryArgument *pushToMemory = NULL;
TR::Register *argMemReg;
TR::Register *tempReg;
int32_t argIndex = 0;
int32_t numMemArgs = 0;
int32_t argSize = 0;
int32_t numIntegerArgs = 0;
int32_t numFloatArgs = 0;
int32_t totalSize;
int32_t i;
TR::Node *child;
TR::DataType childType;
TR::DataType resType = callNode->getType();
uint32_t firstArgumentChild = callNode->getFirstArgumentIndex();
/* Step 1 - figure out how many arguments are going to be spilled to memory i.e. not in registers */
for (i = firstArgumentChild; i < callNode->getNumChildren(); i++)
{
child = callNode->getChild(i);
childType = child->getDataType();
switch (childType)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Int64:
case TR::Address:
if (numIntegerArgs >= properties.getNumIntArgRegs())
numMemArgs++;
numIntegerArgs++;
break;
case TR::Float:
case TR::Double:
if (numFloatArgs >= properties.getNumFloatArgRegs())
numMemArgs++;
numFloatArgs++;
break;
default:
TR_ASSERT(false, "Argument type %s is not supported\n", childType.toString());
}
}
// From here, down, any new stack allocations will expire / die when the function returns
TR::StackMemoryRegion stackMemoryRegion(*trMemory());
/* End result of Step 1 - determined number of memory arguments! */
if (numMemArgs > 0)
{
pushToMemory = new (trStackMemory()) TR::ARM64MemoryArgument[numMemArgs];
argMemReg = cg()->allocateRegister();
}
totalSize = numMemArgs * 8;
// align to 16-byte boundary
totalSize = (totalSize + 15) & (~15);
numIntegerArgs = 0;
numFloatArgs = 0;
for (i = firstArgumentChild; i < callNode->getNumChildren(); i++)
{
TR::MemoryReference *mref = NULL;
TR::Register *argRegister;
TR::InstOpCode::Mnemonic op;
child = callNode->getChild(i);
childType = child->getDataType();
switch (childType)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Int64:
case TR::Address:
if (childType == TR::Address)
argRegister = pushAddressArg(child);
else if (childType == TR::Int64)
argRegister = pushLongArg(child);
else
argRegister = pushIntegerWordArg(child);
if (numIntegerArgs < properties.getNumIntArgRegs())
{
if (!cg()->canClobberNodesRegister(child, 0))
{
if (argRegister->containsCollectedReference())
tempReg = cg()->allocateCollectedReferenceRegister();
else
tempReg = cg()->allocateRegister();
//.........这里部分代码省略.........
开发者ID:LinHu2016,项目名称:omr,代码行数:101,代码来源:ARM64SystemLinkage.cpp
示例15: assignRegisters
void TR_PPCRegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
// *this swipeable for debugging purposes
TR::Machine *machine = cg->machine();
TR::Register *virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister *dependentRealReg, *assignedRegister, *realReg;
int i, j;
TR::Compilation *comp = cg->comp();
int num_gprs = 0;
int num_fprs = 0;
int num_vrfs = 0;
// Use to do lookups using real register numbers
TR_PPCRegisterDependencyMap map(_dependencies, numberOfRegisters);
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
traceMsg (comp,"\nOOL: Found register spilled in main line and re-assigned inside OOL");
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(currentNode, (TR::SymbolReference*)virtReg->getBackingStorage()->getSymbolReference(), sizeof(uintptr_t), cg);
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
opCode =TR::InstOpCode::Op_load;
break;
case TR_FPR:
opCode = virtReg->isSinglePrecision() ? TR::InstOpCode::lfs : TR::InstOpCode::lfd;
break;
default:
TR_ASSERT(0, "\nRegister kind not supported in OOL spill\n");
break;
}
TR::Instruction *inst = generateTrg1MemInstruction(cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (comp->getDebug())
cg->traceRegisterAssignment("Generate reload of virt %s due to spillRegIndex dep at inst %p\n",comp->getDebug()->getName(virtReg),currentInstruction);
cg->traceRAInstruction(inst);
}
if (!(std::find(cg->getSpilledRegisterList()->begin(), cg->getSpilledRegisterList()->end(), virtReg) != cg->getSpilledRegisterList()->end()))
cg->getSpilledRegisterList()->push_front(virtReg);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR::PPCLabelInstruction *labelInstr = (TR::PPCLabelInstruction *)currentInstruction;
TR_BackingStore * location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (labelInstr->getLabelSymbol()->isStartOfColdInstructionStream() && location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
for (i = 0; i < numberOfRegisters; i++)
{
map.addDependency(_dependencies[i], i);
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum != TR::RealRegister::SpilledReg)
{
if (virtReg->getKind() == TR_GPR)
num_gprs++;
else if (virtReg->getKind() == TR_FPR)
//.........这里部分代码省略.........
开发者ID:rservant,项目名称:omr,代码行数:101,代码来源:OMRRegisterDependency.cpp
示例16: assignContendedRegisters
static void assignContendedRegisters(TR::Instruction *currentInstruction,
TR::RegisterDependency *dep,
TR_PPCRegisterDependencyMap& map,
bool depsBlocked,
TR::CodeGenerator *cg)
{
// *this swipeable for debugging purposes
TR::Machine *machine = cg->machine();
dep = findDependencyChainHead(dep, map);
TR::Register *virtReg = dep->getRegister();
TR::RealRegister::RegNum targetRegNum = dep->getRealRegister();
TR::RealRegister *targetReg = machine->getPPCRealRegister(targetRegNum);
TR::RealRegister *assignedReg = virtReg->getAssignedRealRegister() ?
toRealRegister(virtReg->getAssignedRealRegister()) : NULL;
// Chain of length 1
if (!assignedReg || !map.getDependencyWithTarget(assignedReg->getRegisterNumber()))
{
machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
virtReg->block();
return;
}
// Chain of length 2, handled here instead of below to get 3*xor exchange on GPRs
if (map.getDependencyWithTarget(assignedReg->getRegisterNumber()) == map.getDependencyWithAssigned(targetRegNum))
{
TR::Register *targetVirtReg = targetReg->getAssignedRegister();
machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
virtReg->block();
targetVirtReg->block();
return;
}
// Grab a spare reg in order to free the target of the first dep
// At this point the first dep's target could be blocked, assigned, or NoReg
// If it's blocked or assigned we allocate a spare and assign the target's virtual to it
// If it's NoReg, the spare reg will be used as the first dep's actual target
TR::RealRegister *spareReg = machine->findBestFreeRegister(currentInstruction, virtReg->getKind(),
targetRegNum == TR::RealRegister::NoReg ? dep->getExcludeGPR0() : false, false,
targetRegNum == TR::RealRegister::NoReg ? virtReg : targetReg->getAssignedRegister());
bool haveFreeSpare = spareReg != NULL;
if (!spareReg)
{
// If the regs in this dep group are not blocked we need to make sure we don't spill a reg that's in the middle of the chain
if (!depsBlocked)
{
if (targetRegNum == TR::RealRegister::NoReg)
spareReg = machine->freeBestRegister(currentInstruction,
map.getDependencyWithTarget(assignedReg->getRegisterNumber())->getRegister(),
assignedReg, false);
else
spareReg = machine->freeBestRegister(currentInstruction, virtReg, targetReg, false);
}
else
{
if (targetRegNum == TR::RealRegister::NoReg)
spareReg = machine->freeBestRegister(currentInstruction, virtReg, NULL, dep->getExcludeGPR0());
else
spareReg = machine->freeBestRegister(currentInstruction, targetReg->getAssignedRegister(), NULL, false);
}
}
if (targetRegNum != TR::RealRegister::NoReg && spareReg != targetReg)
{
machine->coerceRegisterAssignment(currentInstruction, targetReg->getAssignedRegister(), spareReg->getRegisterNumber());
}
TR_ASSERT(targetRegNum == TR::RealRegister::NoReg ||
targetReg->getState() == TR::RealRegister::Free, "Expecting free target register");
if (depsBlocked || targetRegNum != TR::RealRegister::NoReg || haveFreeSpare)
{
machine->coerceRegisterAssignment(currentInstruction, virtReg,
targetRegNum == TR::RealRegister::NoReg ?
spareReg->getRegisterNumber() : targetRegNum);
virtReg->block();
}
dep = map.getDependencyWithTarget(assignedReg->getRegisterNumber());
while (dep)
{
virtReg = dep->getRegister();
targetRegNum = dep->getRealRegister();
targetReg = machine->getPPCRealRegister(targetRegNum);
assignedReg = virtReg->getAssignedRealRegister() ?
toRealRegister(virtReg->getAssignedRealRegister()) : NULL;
TR_ASSERT(targetReg->getState() == TR::RealRegister::Free || targetReg == spareReg,
"Expecting free target register or target to have been filled to free spare register");
machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
virtReg->block();
dep = assignedReg ?
map.getDependencyWithTarget(assignedReg->getRegisterNumber()) : NULL;
}
//.........这里部分代码省略.........
开发者ID:rservant,项目名称:omr,代码行数:101,代码来源:OMRRegisterDependency.cpp
示例17: if
void OMR::X86::Instruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
{
if (!self()->getDependencyConditions())
{
// Fast path when there are no dependency conditions.
//
return;
}
if (self()->getOpCodeValue() != ASSOCREGS)
{
self()->aboutToAssignRegDeps();
if ((self()->cg()->getAssignmentDirection() == self()->cg()->Backward))
{
self()->getDependencyConditions()->assignPostConditionRegisters(self(), kindsToBeAssigned, self()->cg());
self()->getDependencyConditions()->assignPreConditionRegisters(self(), kindsToBeAssigned, self()->cg());
}
else
{
self()->getDependencyConditions()->assignPreConditionRegisters(self()->getPrev(), kindsToBeAssigned, self()->cg());
self()->getDependencyConditions()->assignPostConditionRegisters(self(), kindsToBeAssigned, self()->cg());
}
}
else if ((self()->getOpCodeValue() == ASSOCREGS) && self()->cg()->enableRegisterAssociations())
{
if (kindsToBeAssigned & TR_GPR_Mask)
{
TR::Machine *machine = self()->cg()->machine();
// First traverse the existing associations and remove them
// so that they don't interfere with the new ones
//
for (int i = TR::RealRegister::FirstGPR;
i <= TR::RealRegister::LastAssignableGPR;
++i)
{
// Skip non-assignable registers
//
if (machine->getX86RealRegister((TR::RealRegister::RegNum)i)->getState() == TR::RealRegister::Locked)
continue;
TR::Register *virtReg = machine->getVirtualAssociatedWithReal((TR::RealRegister::RegNum)i);
if (virtReg)
{
virtReg->setAssociation(TR::RealRegister::NoReg);
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