static void
init_channel(channel_data_t* __ch_data)
{
	cyg_uint8* base = __ch_data->base;
	cyg_uint8 lcr;
    cyg_uint32 brd;

	// 8-1-no parity.
	lcr = PXA2X0_UART_LCR_WLS0 | PXA2X0_UART_LCR_WLS1;
	lcr |= PXA2X0_UART_LCR_DLAB;
	HAL_WRITE_UINT8( base+PXA2X0_UART_LCR, lcr );

	//	Setup divisor
    brd = PXA2X0_UART_BAUD_RATE_DIVISOR( __ch_data->baud_rate );
    HAL_WRITE_UINT8( base+PXA2X0_UART_DLH, (brd >> 8) & 0xff );
    HAL_WRITE_UINT8( base+PXA2X0_UART_DLL, brd & 0xff );


	//	DLAB = 0 to allow access to FIFOs
    lcr &= ~PXA2X0_UART_LCR_DLAB;
    HAL_WRITE_UINT8(base+PXA2X0_UART_LCR, lcr);

	//  Enable & clear FIFOs
	//  set Interrupt Trigger Level to be 1 byte
	HAL_WRITE_UINT8(base+PXA2X0_UART_FCR, 
		(PXA2X0_UART_FCR_FCR0 | PXA2X0_UART_FCR_FCR1 | PXA2X0_UART_FCR_FCR2));  // Enable & clear FIFO

	//	Configure NRZ, disable DMA requests and enable UART
	HAL_WRITE_UINT8(base+PXA2X0_UART_IER, PXA2X0_UART_IER_UUE);
}

// Sending out a command. The controller command, if any, gets sent here.
// This is followed by the first byte for the keyboard or mouse. The
// remaining bytes and any retransmits will be handled by the interrupt
// handler.
static void
ps2_send_command(int controller_command, unsigned char* command, int length, int mouse)
{
    int     status;
    
    CYG_PRECONDITION(NULL == ps2_command, "Only one send command is allowed at a time");
    CYG_PRECONDITION((KC_CONTROL_NULL != controller_command) || (NULL != command), "no-op");
    CYG_PRECONDITION(!mouse || (KC_CONTROL_NULL == controller_command), "cannot combine controller and mouse commands");
    
    ps2_command         = command;
    ps2_command_index   = 0;
    ps2_command_length  = length;
    ps2_command_mouse   = 0;
    ps2_command_ack     = 0;

    if (KC_CONTROL_NULL != controller_command) {
        do {
            HAL_READ_UINT8(KC_STATUS, status);
        } while (status & KC_STATUS_INPB);
        HAL_WRITE_UINT8(KC_CONTROL, controller_command);
    }

    if (length > 0) {
        if (mouse) {
            do {
                HAL_READ_UINT8(KC_STATUS, status);
            } while (status & KC_STATUS_INPB);
            HAL_WRITE_UINT8(KC_CONTROL, KC_CONTROL_WRITE_AUX);
        }
        do {
            HAL_READ_UINT8(KC_STATUS, status);
        } while (status & KC_STATUS_INPB);
        HAL_WRITE_UINT8(KC_INPUT, command[0]);
    }
}

static void
aeb_setup_timer1(cyg_uint32 period)
{
    cyg_uint32 iocr;

    // Set counter GATE input low (0) to halt counter while it's being setup
    HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);

    // Scale timer0 clock
    HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16);

    // Initialize counter, mode 2 = rate generator
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, 
                    TIMER_CTL_TYPE_BIN|
                    TIMER_CTL_MODE_RG|
                    TIMER_CTL_RW_BOTH|
                    TIMER_CTL_SC_CTR1);
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF));        // LSB
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB
    // Enable timer
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1,
                             99,             // Priority
                             0,              // Data item passed to interrupt handler
                             aeb_timer1_isr,
                             0,
                             &timer1_interrupt_handle,
                             &timer1_interrupt);
    cyg_drv_interrupt_attach(timer1_interrupt_handle);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1);
}

void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8* base = chan->base;
    cyg_uint16 fdr, sr;
    cyg_uint8 scscr = 0;
    CYGARC_HAL_SAVE_GP();

    HAL_READ_UINT8(base+_REG_SCSCR, scscr);
    if (chan->irda_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE);
    }
#endif

    do {
        HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);

    HAL_WRITE_UINT8(base+_REG_SCFTDR, c);

    // Clear FIFO-empty/transmit end flags (read back SR first)
    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK   
                     & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));

    // Hang around until all characters have been safely sent.
    do {
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
    } while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0);


    if (chan->irda_mode) {
#ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // In IrDA mode there will be generated spurious RX events when
        // the TX unit is switched on. Eat that character.
        cyg_uint8 _junk;
        HAL_READ_UINT8(base+_REG_SCFRDR, _junk);

        // Clear buffer full flag (read back first)
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR, 
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
#endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // Disable transmitter again
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        // Disable transmitter, enable receiver
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX

    CYGARC_HAL_RESTORE_GP();
}

void hal_clock_initialize(cyg_uint32 period)
{
    cyg_uint8 prescale;
    cyg_uint8 tmp;
#if CYGNUM_HAL_H8300_RTC_PRESCALE == 8
    prescale = 0x01;
#else
#if CYGNUM_HAL_H8300_RTC_PRESCALE == 64
    prescale = 0x02;
#else
#if CYGNUM_HAL_H8300_RTC_PRESCALE == 8192
    prescale = 0x03;
#else
#error illigal RTC prescale setting
#endif
#endif
#endif
    HAL_READ_UINT8(CYGARC_MSTPCRL, tmp);
    tmp &= ~0x01;
    HAL_WRITE_UINT8(CYGARC_MSTPCRL, tmp);
    HAL_WRITE_UINT8(CYGARC_8TCORA1, period);
    HAL_WRITE_UINT8(CYGARC_8TCNT1, 0x00);
    HAL_WRITE_UINT8(CYGARC_8TCR1, 0x48 | prescale);
    HAL_WRITE_UINT8(CYGARC_8TCSR1, 0x00);
}

void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
    cyg_uint8* port;
    cyg_uint8 _lcr;

    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    // Go ahead and assume it is channels[0].
    if (__ch_data == 0)
      __ch_data = (void*)&channels[0];

    port = ((channel_data_t*)__ch_data)->base;

    // Disable port interrupts while changing hardware
    HAL_WRITE_UINT8(port+SER_16550_IER, 0);

    // Set databits, stopbits and parity.
    _lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);

    // Set baud rate.
    cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);

    // Enable and clear FIFO
    HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));

    // enable RTS to keep host side happy
    HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS );
    
    // Don't allow interrupts.
    HAL_WRITE_UINT8(port+SER_16550_IER, 0);
}

static int
cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc, 
                    CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    cyg_uint8 c, sr;
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    int res = 0;
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;
    HAL_READ_UINT8(base+_REG_SCSSR, sr);
    if (sr & CYGARC_REG_SCI_SCSSR_ORER) {
        // Serial RX overrun. Clear error and hope protocol recovers.
        HAL_WRITE_UINT8(base+_REG_SCSSR, 
                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_ORER);
        res = CYG_ISR_HANDLED;
    } else if (sr & CYGARC_REG_SCI_SCSSR_RDRF) {
        // Received character
        HAL_READ_UINT8(base+_REG_SCRDR, c);

        // Clear buffer full flag.
        HAL_WRITE_UINT8(base+_REG_SCSSR, 
                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);

        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

void
cyg_hal_plf_scif_sync_rxtx(int scif_index, bool async_rxtx_mode)
{
    channel_data_t* chan = &channels[scif_index];
    chan->async_rxtx_mode = async_rxtx_mode;
    if (async_rxtx_mode)
        HAL_WRITE_UINT8(chan->base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
    else
        HAL_WRITE_UINT8(chan->base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE|CYGARC_REG_SCIF_SCSCR_TE);
}

static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
    cyg_uint8 ser_port_reg;
    int ret = 0;
    va_list ap;

    CYGARC_HAL_SAVE_GP();
    va_start(ap, __func);

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        chan->irq_state = 1;
        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
        HAL_INTERRUPT_UNMASK(chan->isr_vector);

        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);

        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = chan->irq_state;
        chan->irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);

        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
        chan->baud_rate = va_arg(ap, cyg_int32);
        // Should we verify this value here?
        cyg_hal_plf_serial_init_channel(chan);
        ret = 0;
        break;
    default:
        break;
    }

    va_end(ap);
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    int ret = 0;
    CYGARC_HAL_SAVE_GP();

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        irq_state = 1;

	HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;

	HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
        HAL_INTERRUPT_MASK(chan->isr_vector);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
    {
        va_list ap;

        va_start(ap, __func);

        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);

        va_end(ap);
    }        
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
    {
        va_list ap;
        va_start(ap, __func);
        chan->baud_rate = va_arg(ap, cyg_int32);
        va_end(ap);
        ret = set_baud(chan);
        break;
    }
    default:
        break;
    }
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    
    // 8-1-no parity.
    HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
    chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
    set_baud( chan );
    HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);  // Enable & clear FIFO
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    int ret = -1;
    cyg_uint8 ier;
	va_list ap;

    CYGARC_HAL_SAVE_GP();
    va_start(ap, __func);

    switch (__func) {
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
        chan->baud_rate = va_arg(ap, cyg_int32);
        // Should we verify this value here?
        init_channel(chan);
        ret = 0;
        break;
    case __COMMCTL_IRQ_ENABLE:
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
        HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
        ier |= PXA2X0_UART_IER_RAVIE;
        HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
        irq_state = 1;
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);
        HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
        ier &= ~PXA2X0_UART_IER_RAVIE;
        HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);
        break;
    default:
        break;
    }
    va_end(ap);
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

void MoveCursor
(
	void
)
{
	int pos = XPos + YPos * ScreenWidth;

	HAL_WRITE_UINT8(DisplayPort, 0x0e );
	HAL_WRITE_UINT8(DisplayPort+1, pos >> 8 );

	HAL_WRITE_UINT8(DisplayPort, 0x0f );
	HAL_WRITE_UINT8(DisplayPort+1, pos & 0xFF );
	
} /* MoveCursor */

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8 ier;
    int ret = 0;
    CYGARC_HAL_SAVE_GP();

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        irq_state = 1;

        HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
        ier |= CYG_DEVICE_BK0_IER_RXHDL_IE;
        HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);

        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;

        HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
        ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE;
        HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);

        HAL_INTERRUPT_MASK(chan->isr_vector);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
    {
        va_list ap;

        va_start(ap, __func);

        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);

        va_end(ap);
    }        
    default:
        break;
    }
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

void cyg_hal_plf_pci_init(void)
{
        int i;
        cyg_uint32 val;
#if 0
        char idbuf[16];

        for(i=0; i<16; i++)
                HAL_READ_UINT8(GAPSPCI_REGS+i, idbuf[i]);

        if(strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
                return;
#endif

        gapspci_initialized = false;

        HAL_WRITE_UINT32(GAPSPCI_REGS+0x18, 0x5a14a501);

        for(i=0; i<1000000; i++);

        HAL_READ_UINT32(GAPSPCI_REGS+0x18, val);
        if (val != 1) return;

        HAL_WRITE_UINT32(GAPSPCI_REGS+0x20, 0x01000000);
        HAL_WRITE_UINT32(GAPSPCI_REGS+0x24, 0x01000000);

        HAL_WRITE_UINT32(GAPSPCI_REGS+0x28, GAPSPCI_DMA_BASE);
        HAL_WRITE_UINT32(GAPSPCI_REGS+0x2c, GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE);

        HAL_WRITE_UINT32(GAPSPCI_REGS+0x14, 1);
        HAL_WRITE_UINT32(GAPSPCI_REGS+0x34, 1);

#if 1
        /* Setting up Broadband Adapter */
        HAL_WRITE_UINT16(GAPSPCI_BBA_CONFIG+0x06, 0xf900);
        HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x30, 0x00000000);
        HAL_WRITE_UINT8 (GAPSPCI_BBA_CONFIG+0x3c, 0x00);
        HAL_WRITE_UINT8 (GAPSPCI_BBA_CONFIG+0x0d, 0xf0);
        HAL_WRITE_UINT16(GAPSPCI_BBA_CONFIG+0x04, 0x0006);
        HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x10, 0x00002001);
        HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x14, 0x01000000);
#endif

        /* Enable interrupt */
        HAL_READ_UINT32(GAPSPCI_INTC, val);
        val |= (1<<3);
        HAL_WRITE_UINT32(GAPSPCI_INTC, val);

        gapspci_initialized = true;
}

// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
mipsidt_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
    mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv;
    cyg_addrword_t port = mipsidt_chan->base;
    cyg_uint32 baud_divisor = select_baud[new_config->baud]; ;
    cyg_uint8 _lcr, _ier;

    if (baud_divisor == 0)
        return false;    // Invalid baud rate selected

	baud_divisor = (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL * 10) / (16 * select_baud[new_config->baud]);

	baud_divisor +=5;
	baud_divisor =  ((cyg_int32)baud_divisor) / 10;


    // Disable port interrupts while changing hardware
    HAL_READ_UINT8(port+SER_16550_IER, _ier);
    HAL_WRITE_UINT8(port+SER_16550_IER, 0);

    // Set databits, stopbits and parity.
    _lcr = select_word_length[(new_config->word_length -
                               CYGNUM_SERIAL_WORD_LENGTH_5)] | 
        select_stop_bits[new_config->stop] |
        select_parity[new_config->parity];
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);

    // Set baud rate.
    _lcr |= LCR_DL;
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8);
    HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff);
    _lcr &= ~LCR_DL;
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);

    if (init) {
        // Enable and clear FIFO
        HAL_WRITE_UINT8(port+SER_16550_FCR,
                        (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));

        if (chan->out_cbuf.len != 0) {
            HAL_WRITE_UINT8(port+SER_16550_IER, SIO_IER_ERDAI);
        } else {
            HAL_WRITE_UINT8(port+SER_16550_IER, 0);
        }
    } else {
        HAL_WRITE_UINT8(port+SER_16550_IER, _ier);
    }
    if (new_config != &chan->config) {
        chan->config = *new_config;
    }
    return true;
}

static void
cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor)
{
    cyg_uint8 _lcr;

    HAL_READ_UINT8(port+SER_16550_LCR, _lcr);
    _lcr |= LCR_DL;
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);

    HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8);
    HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff);

    _lcr &= ~LCR_DL;
    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
}

externC bool
hal_ppc405_i2c_put_bytes(int addr, cyg_uint8 *val, int len)
{
    cyg_uint8 stat, extstat, xfrcnt, cmd, size;
    int i, j;

    // The hardware can only move up to 4 bytes in a single operation
    // This code breaks the request down into chunks of up to 4 bytes
    // and checks the status after each chunk.
    // Note: the actual device may impose additional size restrictions,
    // e.g. some EEPROM devices may limit a single write to 32 bytes.
    for (i = 0;  i < len;  i += size) {
        HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA));
        HAL_WRITE_UINT8(IIC0_EXTSTS, (IIC0_EXTSTS_IRQP|IIC0_EXTSTS_IRQD));
        HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB));
        cmd = IIC0_CNTL_RW_WRITE|IIC0_CNTL_PT;
        size = (len - i);
        if (size > 4) {
            size = 4;
            cmd |= IIC0_CNTL_CHT;
        }
        cmd |= ((size-1)<<IIC0_CNTL_TCT_SHIFT);
        for (j = 0;  j < size;  j++) {
            HAL_WRITE_UINT8(IIC0_MDBUF, val[i+j]);
        }
        HAL_WRITE_UINT8(IIC0_LMADR, addr);
        HAL_WRITE_UINT8(IIC0_CNTL, cmd);
        while (true) {
            CYGACC_CALL_IF_DELAY_US(10);   // 10us
            HAL_READ_UINT8(IIC0_STS, stat);
            if ((stat & IIC0_STS_PT) == 0) {
                if ((stat & IIC0_STS_ERR) != 0) {
                    // Some sort of error
                    HAL_READ_UINT8(IIC0_EXTSTS, extstat);
                    HAL_READ_UINT8(IIC0_XFRCNT, xfrcnt);
                    HAL_WRITE_UINT8(IIC0_EXTSTS, extstat);
                    HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB));
                    HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA));
                    diag_printf("%s addr: %x, len: %d, err: %x/%x, count: %d, cmd: %x\n",
                                __FUNCTION__, addr, len, stat, extstat, xfrcnt, cmd);
                    diag_printf("buf: ");
                    for (j = 0;  j < size;  j++) {
                        diag_printf("0x%02x ", val[i+j]);
                    }
                    diag_printf("\n");
                    return false;
                }
                break;
            }
        }
    }
    return true;
}

void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
{
    cyg_uint8* port;
    cyg_uint8 _lsr;

    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    // Go ahead and assume it is channels[0].
    if (__ch_data == 0)
      __ch_data = (void*)&channels[0];

    port = ((channel_data_t*)__ch_data)->base;

    CYGARC_HAL_SAVE_GP();

    do {
        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    } while ((_lsr & SIO_LSR_THRE) == 0);

    // Now, the transmit buffer is empty
    HAL_WRITE_UINT8(port+SER_16550_THR, __ch);

    // Hang around until the character has been safely sent.
    do {
        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    } while ((_lsr & SIO_LSR_THRE) == 0);

    CYGARC_HAL_RESTORE_GP();
}

//static 
cyg_bool
cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint16 fdr, sr;
    cyg_bool res = false;

    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    if (sr & CYGARC_REG_SCIF_SCSSR_ER) {
        cyg_uint8 ssr2;
        HAL_WRITE_UINT16(base+_REG_SCFER, 0);
        HAL_READ_UINT8(base+_REG_SC2SSR, ssr2);
        ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER;
        HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER));
    }


    HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) {

        HAL_READ_UINT8(base+_REG_SCFRDR, *ch);

        // Clear DR/RDF flags
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR));

        res = true;
    }

    return res;
}