/**
*
* Find the common supported voltage on all nodes, taken into account of the
* user option for performance and power saving.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return TRUE - No fatal error occurs.
* @return FALSE - Fatal error occurs.
*/
BOOLEAN
MemMLvDdr3PerformanceEnhPre (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
BOOLEAN RetVal;
DIMM_VOLTAGE VDDIO;
MEM_NB_BLOCK *NBPtr;
MEM_PARAMETER_STRUCT *ParameterPtr;
MEM_SHARED_DATA *mmSharedPtr;
PLATFORM_POWER_POLICY PowerPolicy;
NBPtr = MemMainPtr->NBPtr;
mmSharedPtr = MemMainPtr->mmSharedPtr;
ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;
IDS_OPTION_HOOK (IDS_MEMORY_POWER_POLICY, &PowerPolicy, &NBPtr->MemPtr->StdHeader);
IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n");
if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) {
mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));
SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);
IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n");
RetVal = TRUE;
} else {
RetVal = MemMLvDdr3 (MemMainPtr);
VDDIO = ParameterPtr->DDR3Voltage;
if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) {
// When there is no commonly supported voltage, do not optimize performance
// For cases where we can maximize performance, do the following
// When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO
// So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance.
ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
}
IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);
if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {
// When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance
mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n");
} else {
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
}
// Reprogram the leveling result as temporal candidate
ParameterPtr->DDR3Voltage = VDDIO;
}
}
ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);
return RetVal;
}
/**
* Main entry point for the AMD_INIT_ENV function.
*
* This entry point is responsible for copying the heap contents from the
* temp RAM area to main memory.
*
* @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV
* entry point.
*
* @return Aggregated status across all internal AMD env calls invoked.
*
*/
AGESA_STATUS
AmdInitEnv (
IN OUT AMD_ENV_PARAMS *EnvParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitEnvStatus;
AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
ASSERT (EnvParams != NULL);
AmdInitEnvStatus = AGESA_SUCCESS;
//Copy Temp Ram heap content to Main Ram
AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
// Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.
// After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.
//Heap have been relocated, so Debug Print need be init again to get new address
IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);
AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);
AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;
IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);
AgesaStatus = GnbInitAtEnv (EnvParams);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
return AmdInitEnvStatus;
}
/**
*
* Find the common supported voltage on all nodes, taken into account of the
* user option for performance and power saving.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return TRUE - No fatal error occurs.
* @return FALSE - Fatal error occurs.
*/
BOOLEAN
MemMLvDdr3PerformanceEnhPre (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
BOOLEAN RetVal;
DIMM_VOLTAGE VDDIO;
MEM_NB_BLOCK *NBPtr;
MEM_PARAMETER_STRUCT *ParameterPtr;
MEM_SHARED_DATA *mmSharedPtr;
PLATFORM_POWER_POLICY PowerPolicy;
NBPtr = MemMainPtr->NBPtr;
mmSharedPtr = MemMainPtr->mmSharedPtr;
ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;
IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader);
IDS_HDT_CONSOLE (MEM_STATUS, (PowerPolicy == Performance) ? "Maximize Performance\n" : "Maximize Battery Life\n");
RetVal = MemMLvDdr3 (MemMainPtr);
VDDIO = ParameterPtr->DDR3Voltage;
ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
if (mmSharedPtr->VoltageMap == 0) {
// When there is no commonly supported voltage, do not optimize performance
mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
} else if (PowerPolicy == BatteryLife) {
ParameterPtr->DDR3Voltage = VDDIO;
}
IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);
if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {
// When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance
mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
IDS_HDT_CONSOLE (MEM_STATUS, "VDDIO is determined. No further optimization will be done.\n");
} else {
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
NBPtr[Node].MaxFreqVDDIO[VOLT1_5] = UNSUPPORTED_DDR_FREQUENCY;
NBPtr[Node].MaxFreqVDDIO[VOLT1_35] = UNSUPPORTED_DDR_FREQUENCY;
NBPtr[Node].MaxFreqVDDIO[VOLT1_25] = UNSUPPORTED_DDR_FREQUENCY;
}
}
// Reprogram the leveling result
ParameterPtr->DDR3Voltage = VDDIO;
return RetVal;
}
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
D18F4x15C_STRUCT CpbControl;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader);
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
CpbControl.Field.BoostSrc = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
SMUx0Bx8580.Value = 0;
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:48，代码来源:F12Cpb.c
示例7: SetF10DaCacheFlushOnHaltRegister
/**
* Enable DA-C Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF10DaCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CoreCount;
UINT32 AndMask;
UINT32 OrMask;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID LogicalId;
if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
// F3xDC[25:19] = 04h
// F3xDC[18:16] = 111b
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
AndMask = 0xFC00FFFF;
OrMask = 0x00270000;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if (LogicalId.Revision == AMD_F10_DA_C2) {
//For DA_C2 single Core, F3xDC[18:16] = 0
GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
if (CoreCount == 1) {
OrMask = 0x00200000;
}
}
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
}
}
/**
* Dispatches all features needing to perform some initialization at
* this time point.
*
* This routine searches the feature table for features needing to
* run at this time point, and invokes them.
*
* @param[in] EntryPoint Timepoint designator
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Standard AMD configuration parameters.
*
* @return The most severe status of any called service.
*/
AGESA_STATUS
DispatchCpuFeatures (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN i;
AGESA_STATUS AgesaStatus;
AGESA_STATUS CalledStatus;
AGESA_STATUS IgnoredStatus;
AgesaStatus = AGESA_SUCCESS;
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);
if (IsBsp (StdHeader, &IgnoredStatus)) {
for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {
if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {
CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
}
}
}
}
return AgesaStatus;
}
BOOLEAN
MemNDQSTiming3Nb (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
MEM_TECH_BLOCK *TechPtr;
TechPtr = NBPtr->TechPtr;
if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {
// Right now we do not have anything to do if the callout is implemented
}
AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
//Execute Technology specific training features
if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) {
if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);
if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);
if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);
// If target speed is higher than start-up speed, do frequency change and second pass of WL
if (MemTHwWlPart2 (TechPtr)) {
if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) {
IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));
if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) {
if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
do {
if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) {
MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
}
} while (NBPtr->ChangeNbFrequency (NBPtr));
}
}
}
}
}
}
}
}
}
}
MemTMarkTrainFail (TechPtr);
}
return TRUE;
}
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