static int s3c_serial_probe(struct device_d *dev)
{
	struct resource *iores;
	struct s3c_uart *priv;
	struct console_device *cdev;

	priv = xzalloc(sizeof(struct s3c_uart));
	cdev = &priv->cdev;
	iores = dev_request_mem_resource(dev, 0);
	if (IS_ERR(iores))
		return PTR_ERR(iores);
	priv->regs = IOMEM(iores->start);
	dev->priv = priv;
	cdev->dev = dev;
	cdev->tstc = s3c_serial_tstc;
	cdev->putc = s3c_serial_putc;
	cdev->getc = s3c_serial_getc;
	cdev->flush = s3c_serial_flush;
	cdev->setbrg = s3c_serial_setbaudrate;

	s3c_serial_init_port(cdev);

	/* Enable UART */
	console_register(cdev);

	return 0;
}

int mt_devapc_clear_emi_violation(void)
{
    if ((readl(IOMEM(DEVAPC0_D0_VIO_STA_3)) & ABORT_EMI) != 0) {
        mt_reg_sync_writel(ABORT_EMI, DEVAPC0_D0_VIO_STA_3);
    }
    return 0;
}

static struct syscon *of_syscon_register(struct device_node *np)
{
	int ret;
	struct syscon *syscon;
	struct resource res;

	if (!of_device_is_compatible(np, "syscon"))
		return ERR_PTR(-EINVAL);

	syscon = xzalloc(sizeof(*syscon));

	if (of_address_to_resource(np, 0, &res)) {
		ret = -ENOMEM;
		goto err_map;
	}

	syscon->base = IOMEM(res.start);
	syscon->np   = np;

	list_add_tail(&syscon->list, &syscon_list);

	syscon->regmap = regmap_init(NULL,
				     &syscon_regmap_bus,
				     syscon,
				     &syscon_regmap_config);
	return syscon;

err_map:
	kfree(syscon);
	return ERR_PTR(ret);
}

int get_ddr_type(void)
{
  unsigned int value;
  
  value = DRAMC_READ(DRAMC_LPDDR2);
  if((value>>28) & 0x1) //check LPDDR2_EN
  {
    return LPDDR2;
  }  
  
  value = DRAMC_READ(DRAMC_ACTIM1);
  if((value>>28) & 0x1) //check LPDDR3_EN
  {
       
	value = readl(IOMEM(EMI_CONA));       
	if (value & 0x01)   //support 2 channel
	{
	    return DUAL_LPDDR3_1600;
	}
	else
	{
	    return LPDDR3_1866;
	}	
  }  
  
  return mDDR;  
}

static void __init kzm_init(void)
{
	regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
				     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
	regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));

	sh73a0_pinmux_init();

	/* SMSC */
	gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */

	/* LCDC */
	gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
	gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */

	/* Touchscreen */
	gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
#endif

	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
	i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices));
	i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices));

	sh73a0_add_standard_devices();
	platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));

	sh73a0_pm_init();
}

void __init hawaii_timer_init(void)
{
	struct gp_timer_setup gpt_setup;

	/*
	 * IMPORTANT:
	 * If we have to use slave-timer as system timer, two modifications are required
	 * 1) modify the name of timer as, gpt_setup.name = "slave-timer";
	 * 2) By default when the clock manager comes up it disables most of
	 *    the clock. So if we switch to slave-timer we should prevent the
	 *    clock manager from doing this. So, modify plat-kona/include/mach/clock.h
	 *
	 * By default aon-timer as system timer the following is the config
	 * #define BCM2165x_CLK_TIMERS_FLAGS     (TYPE_PERI_CLK | SW_GATE | DISABLE_ON_INIT)
	 * #define BCM2165x_CLK_HUB_TIMER_FLAGS  (TYPE_PERI_CLK | SW_GATE)
	 *
	 * change it as follows to use slave timer as system timer
	 *
	 * #define BCM2165x_CLK_TIMERS_FLAGS     (TYPE_PERI_CLK | SW_GATE)
	 * #define BCM2165x_CLK_HUB_TIMER_FLAGS  (TYPE_PERI_CLK | SW_GATE | DISABLE_ON_INIT)
	 */
	gpt_setup.name = "aon-timer";
	gpt_setup.ch_num = 3;
	gpt_setup.rate = CLOCK_TICK_RATE;

	/* Call the init function of timer module */
	gp_timer_init(&gpt_setup);
	profile_timer_init(IOMEM(KONA_PROFTMR_VA));
}

static int imx6_mmu_init(void)
{
    void __iomem *l2x0_base = IOMEM(0x00a02000);
    u32 val;

    if (!cpu_is_mx6())
        return 0;

    /* Configure the L2 PREFETCH and POWER registers */
    val = readl(l2x0_base + L310_PREFETCH_CTRL);
    val |= 0x70800000;

    /*
     * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
     * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
     * But according to ARM PL310 errata: 752271
     * ID: 752271: Double linefill feature can cause data corruption
     * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
     * Workaround: The only workaround to this erratum is to disable the
     * double linefill feature. This is the default behavior.
     */
    if (cpu_is_mx6q())
        val &= ~(1 << 30 | 1 << 23);

    writel(val, l2x0_base + L310_PREFETCH_CTRL);

    l2x0_init(l2x0_base, 0x0, ~0UL);

    return 0;
}

/*
 * board init
 */
static void __init eva_init(void)
{

	r8a7740_clock_init(MD_CK0 | MD_CK2);
	eva_clock_init();

	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
	r8a7740_pinmux_init();

	r8a7740_meram_workaround();

	/*
	 * Touchscreen
	 * TODO: Move reset GPIO over to .dts when we can reference it
	 */
	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
#endif

	r8a7740_add_standard_devices_dt();
	r8a7740_pm_init();
}

static void glantank_power_off(void)
{
	__raw_writeb(0x01, IOMEM(0xfe8d0004));

	while (1)
		;
}

static void
kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw)
{
	void __iomem *base = IOMEM(timer_base);
	int loop_limit = 4;

	/*
	 * Read 64-bit free running counter
	 * 1. Read hi-word
	 * 2. Read low-word
	 * 3. Read hi-word again
	 * 4.1
	 *      if new hi-word is not equal to previously read hi-word, then
	 *      start from #1
	 * 4.2
	 *      if new hi-word is equal to previously read hi-word then stop.
	 */

	while (--loop_limit) {
		*msw = readl(base + KONA_GPTIMER_STCHI_OFFSET);
		*lsw = readl(base + KONA_GPTIMER_STCLO_OFFSET);
		if (*msw == readl(base + KONA_GPTIMER_STCHI_OFFSET))
			break;
	}
	if (!loop_limit) {
		pr_err("bcm_kona_timer: getting counter failed.\n");
		pr_err(" Timer will be impacted\n");
	}

	return;
}

int imx7_init(void)
{
	const char *cputypestr;
	void __iomem *src = IOMEM(MX7_SRC_BASE_ADDR);

	imx7_init_lowlevel();

	imx7_init_csu();

	imx7_boot_save_loc();

	psci_set_ops(&imx7_psci_ops);

	switch (imx7_cpu_type()) {
	case IMX7_CPUTYPE_IMX7D:
		cputypestr = "i.MX7d";
		break;
	case IMX7_CPUTYPE_IMX7S:
		cputypestr = "i.MX7s";
		break;
	default:
		cputypestr = "unknown i.MX7";
		break;
	}

	imx_set_silicon_revision(cputypestr, imx7_cpu_revision());
	imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);

	return 0;
}

static void __init kota2_init(void)
{
	regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
				     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
	regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	pinctrl_register_mappings(kota2_pinctrl_map,
				  ARRAY_SIZE(kota2_pinctrl_map));
	sh73a0_pinmux_init();

	/* SMSC911X */
	gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
	gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */

	/* MMCIF */
	gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
#endif
	sh73a0_add_standard_devices();
	platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
}

void MET_BM_Enable(const unsigned int enable)
{
	const unsigned int value = readl(IOMEM(ADDR_EMI+EMI_BMEN));

	mt_reg_sync_writel((value & ~(BUS_MON_PAUSE | BUS_MON_EN)) |
			   (enable ? BUS_MON_EN : 0), ADDR_EMI+EMI_BMEN);
}

static int board_eth_init(void)
{
	void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR);
	struct ge_product_data product;
	int st;

	/* Toggle eth0 reset pin */
	gpio_set_value(4, 0);
	udelay(5);
	gpio_set_value(4, 1);

	/* Disable eTSEC3 */
	out_be32(gur + MPC85xx_DEVDISR_OFFSET,
		 in_be32(gur + MPC85xx_DEVDISR_OFFSET) &
		 ~MPC85xx_DEVDISR_TSEC3);

	st = ge_get_product_data(&product);
	if (((product.v2.mac.count > 0) && (product.v2.mac.count <= MAX_MAC))
	    && (st == 0))
		eth_register_ethaddr(0, (const char *)&product.v2.mac.mac[0]);

	fsl_eth_init(1, &gfar_info[0]);

	return 0;
}

static void __init wakeup_secondary(void)
{
#if defined(CHIPREG_BOOT_2ND_ADDR_OFFSET)
	void __iomem *chipRegBase;

	chipRegBase = IOMEM(KONA_CHIPREG_VA);

	/* Chip-it FPGA has problems writing to this address hence
	 * workaround */
#ifdef CONFIG_MACH_HAWAII_FPGA
	writel((virt_to_phys(kona_secondary_startup) & (~0x3))|0x1, chipRegBase + 0x1C4);
#else
	writel((virt_to_phys(kona_secondary_startup) & (~0x3))|0x1, chipRegBase + CHIPREG_BOOT_2ND_ADDR_OFFSET);
#endif

	smp_wmb();

	/*
	 * Send a 'sev' to wake the secondary core from WFE.
	 * Drain the outstanding writes to memory
	 */
	dsb_sev();
	
	mb();
#endif
}

static void imx7_init_csu(void)
{
	void __iomem *csu = IOMEM(MX7_CSU_BASE_ADDR);
	int i = 0;

	for (i = 0; i < CSU_NUM_REGS; i++)
		writel(CSU_INIT_SEC_LEVEL0, csu + i * 4);
}

int get_dram_type(void)
{
    unsigned int value = readl(IOMEM(DRAMC_BASE_ADDR + DRAMC_ACTIM1));

    if((value >> 28) & 0x1)
        return LPDDR3_1600;
    else 
        return LPDDR2_1066; 

int mt_devapc_emi_initial(void)
{
    /*IO remap*/
    
    struct device_node *node = NULL;
    
    xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG  ," AO_ADDRESS %x,  \n",DEVAPC0_AO_BASE);
    xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ," PD_ADDRESS %x \n",DEVAPC0_PD_BASE);
    
    if( DEVAPC0_AO_BASE == 0 || DEVAPC0_PD_BASE == 0 )
    {
        xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ," DPAC driver  not initial yet \n");

        node = of_find_compatible_node(NULL, NULL, "mediatek,DEVAPC_AO");

        if(node){
           DEVAPC0_AO_BASE = of_iomap(node, 0);
           xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG  ," AO_ADDRESS %x \n",DEVAPC0_AO_BASE );
        } else{
             xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ," can't find DAPC_AO compatible node \n");
             return -1;
        }

        node = of_find_compatible_node(NULL, NULL, "mediatek,DEVAPC");

        if(node){
           DEVAPC0_PD_BASE = of_iomap(node, 0);
           xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ," PD_ADDRESS %x \n",DEVAPC0_PD_BASE );
        } else{
             xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ," can't find DAPC_PD compatible node \n");
             return -1;
        }
    }
    

    mt_reg_sync_writel(readl(IOMEM(DEVAPC0_APC_CON)) & (0xFFFFFFFF ^ (1<<2)), DEVAPC0_APC_CON);
    mt_reg_sync_writel(readl(IOMEM(DEVAPC0_PD_APC_CON)) & (0xFFFFFFFF ^ (1<<2)), DEVAPC0_PD_APC_CON);

    mt_reg_sync_writel(ABORT_EMI, DEVAPC0_D0_VIO_STA_4);
    mt_reg_sync_writel(readl(IOMEM(DEVAPC0_D0_VIO_MASK_4)) & (0xFFFFFFFF ^ (ABORT_EMI)), DEVAPC0_D0_VIO_MASK_4);

    xlog_printk(ANDROID_LOG_ERROR, EMIMPU_TAG   ,"EMI_DAPC Init done \n");

    return 0;
}

/**************************************************************************
*EXTERN FUNCTION
**************************************************************************/
int mt_devapc_check_emi_violation(void)
{
    if ((readl(IOMEM(DEVAPC0_D0_VIO_STA_3)) & ABORT_EMI) == 0) {
        return -1;
    } else {
        pr_err("EMI violation! It should be cleared by EMI MPU driver later!\n");
        return 0;
    }
}

static inline void setup_uart(void)
{
	void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
	void __iomem *ccm   = IOMEM(MX7_CCM_BASE_ADDR);

	writel(CCM_CCGR_SETTINGn_NEEDED(0),
	       ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2));
	writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M,
	       ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT));
	writel(CCM_CCGR_SETTINGn_NEEDED(0),
	       ccm + CCM_CCGRn_SET(CCM_CCGR_UART2));

	mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);

	imx7_uart_setup_ll();

	putc_ll('>');
}