void tegra_init_fuse(void)
{
	u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
	reg |= 1 << 28;
	writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
	tegra_init_speedo_data();

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
		tegra_revision_name[tegra_get_revision()],
		tegra_sku_id(), tegra_cpu_process_id(),
		tegra_core_process_id());
}

int tegra_vi_csi_readl(u32 offset, u32 *val)
{
	if (vi_clk == NULL) {
		vi_clk = tegra_get_clock_by_name("vi");
		if (IS_ERR_OR_NULL(vi_clk)) {
			pr_err("vi: can't get vi clock\n");
			return -EINVAL;
		}
	}
	tegra_clk_prepare_enable(vi_clk);

	if (csi_clk == NULL) {
		csi_clk = tegra_get_clock_by_name("csi");
		if (IS_ERR_OR_NULL(csi_clk)) {
			pr_err("csi: can't get csi clock\n");
			return -EINVAL;
		}
	}
	tegra_clk_prepare_enable(csi_clk);

	*val = readl(IO_TO_VIRT(TEGRA_VI_BASE) + offset * 4);

	tegra_clk_disable_unprepare(csi_clk);
	tegra_clk_disable_unprepare(vi_clk);

	return 0;
}

u32 tegra_apb_readl(unsigned long offset)
{
	struct tegra_dma_req req;
	int ret;

	if (!tegra_apb_dma && !tegra_apb_init())
		return readl(IO_TO_VIRT(offset));

	mutex_lock(&tegra_apb_dma_lock);
	req.complete = apb_dma_complete;
	req.to_memory = 1;
	req.dest_addr = tegra_apb_bb_phys;
	req.dest_bus_width = 32;
	req.dest_wrap = 1;
	req.source_addr = offset;
	req.source_bus_width = 32;
	req.source_wrap = 4;
	req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
	req.size = 4;

	INIT_COMPLETION(tegra_apb_wait);

	tegra_dma_enqueue_req(tegra_apb_dma, &req);

	ret = wait_for_completion_timeout(&tegra_apb_wait,
		msecs_to_jiffies(50));

	if (WARN(ret == 0, "apb read dma timed out")) {
		tegra_dma_dequeue_req(tegra_apb_dma, &req);
		*(u32 *)tegra_apb_bb = 0;
	}

	mutex_unlock(&tegra_apb_dma_lock);
	return *((u32 *)tegra_apb_bb);
}

static inline void apb_writel(u32 value, unsigned long offset)
{
    struct tegra_dma_req req;
    int ret;

    if (!tegra_apb_dma) {
        writel(value, IO_TO_VIRT(offset));
        return;
    }

    mutex_lock(&tegra_apb_dma_lock);
    *((u32 *)tegra_apb_bb) = value;
    req.complete = apb_dma_complete;
    req.to_memory = 0;
    req.dest_addr = offset;
    req.dest_wrap = 4;
    req.dest_bus_width = 32;
    req.source_addr = tegra_apb_bb_phys;
    req.source_bus_width = 32;
    req.source_wrap = 1;
    req.req_sel = 0;
    req.size = 4;

    INIT_COMPLETION(tegra_apb_wait);

    tegra_dma_enqueue_req(tegra_apb_dma, &req);

    ret = wait_for_completion_timeout(&tegra_apb_wait,
                                      msecs_to_jiffies(400));

    if (WARN(ret == 0, "apb write dma timed out"))
        tegra_dma_dequeue_req(tegra_apb_dma, &req);

    mutex_unlock(&tegra_apb_dma_lock);
}

void tegra_mc_set_priority(unsigned long client, unsigned long prio)
{
	unsigned long mc_base = IO_TO_VIRT(TEGRA_MC_BASE);
	unsigned long reg = client >> 8;
	int field = client & 0xff;
	unsigned long val;
	unsigned long flags;

	spin_lock_irqsave(&tegra_mc_lock, flags);
	val = readl(mc_base + reg);
	val &= ~(TEGRA_MC_PRIO_MASK << field);
	val |= prio << field;
	writel(val, mc_base + reg);
	spin_unlock_irqrestore(&tegra_mc_lock, flags);
}

static void utmip_temp_dep_update(int curr_rtemp, int utmip_temp_bound)
{
	static int prev_temp;
	static char initial_update = 1;
	unsigned int fuse_usb_calib_value = s_fuse_usb_calib_value;
	int i;
	char utmip_update_require = 0;

	/* Extract bits[3:0]. */
	fuse_usb_calib_value = fuse_usb_calib_value & 0xF;

	/* If previous and currentt temperatures falls in the same temperature
	   boundary then no need to update the  UTMIP_SPARE_CFG */
	if ((prev_temp >= utmip_temp_bound) && (curr_rtemp >= utmip_temp_bound))
		utmip_update_require = 0;
	else if ((prev_temp < utmip_temp_bound) &&
				(curr_rtemp < utmip_temp_bound))
		utmip_update_require = 0;
	else
		utmip_update_require = 1;

	/*  For Initial call , need to update the UTMIP_SPARE_CFG */
	if (initial_update) {
		utmip_update_require = 1;
		initial_update = 0;
		prev_temp = curr_rtemp;
	}

	if (utmip_update_require) {
		prev_temp = curr_rtemp;
		if (curr_rtemp >= utmip_temp_bound) {
			fuse_usb_calib_value += 0x1;
			/*  Check if there is a overflow. */
			if (fuse_usb_calib_value > UTMIP_XCVR_SETUP_MAX_VAL)
				fuse_usb_calib_value = UTMIP_XCVR_SETUP_MAX_VAL;
		}

		for (i = 0; i < ARRAY_SIZE(s_tegra_usb_base); i++) {
			unsigned int regval;
			regval = readl(IO_TO_VIRT(s_tegra_usb_base[i] +
					UTMIP_SPARE_CFG0));
			regval &= ~FUSE_SETUP_SEL;
			writel(regval, IO_TO_VIRT(s_tegra_usb_base[i] +
					UTMIP_SPARE_CFG0));

			regval = readl(IO_TO_VIRT(s_tegra_usb_base[i] +
					UTMIP_XCVR_CFG0));
			/* If low_to_high, then write 0x2 to HSSLEW_MSB
			 else write 0x8 */
			regval &= ~UTMIP_XCVR_HSSLEW_MSB_MSK;
			regval |= (curr_rtemp >= utmip_temp_bound) ?
					UTMIP_XCVR_HSSLEW_MSB_HIGH_TEMP_VAL :
					UTMIP_XCVR_HSSLEW_MSB_LOW_TEMP_VAL;
			/* write fuse_usb_calib_value to SETUP field
			of UTMIP_XCVR_CFG0. */
			regval &= ~UTMIP_XCVR_SETUP_MSK;
			regval |= fuse_usb_calib_value;
			writel(regval, IO_TO_VIRT(s_tegra_usb_base[i] +
					UTMIP_XCVR_CFG0));
		}
	}
}

static inline void pg_writel(unsigned long value, unsigned long offset)
{
	writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
}

static void get_fuse_usb_calib_value(void)
{
	s_fuse_usb_calib_value = readl(IO_TO_VIRT(TEGRA_FUSE_BASE +
						FUSE_USB_CALIB_0));
}

static inline void gizmo_writel(unsigned long value, unsigned long offset)
{
	writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
}

static inline unsigned long gizmo_readl(unsigned long offset)
{
	return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
}

static inline unsigned long pg_readl(unsigned long offset)
{
	return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
}

 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <xen/kernel.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/fiqdb.h>
#include <asm/termbits.h>
#include <asm/serial_reg.h>
#include <asm/arch/hardware.h>

#define UART_SHIFT 2
static void __iomem *uart_base = (void __iomem *)
	IO_TO_VIRT(TEGRA_DEBUG_UART_BASE);

static inline unsigned char uart_read(int offset)
{
	return readb(uart_base + (offset << UART_SHIFT));
}

static inline void uart_write(unsigned char val, int offset)
{
	writeb(val, uart_base + (offset << UART_SHIFT));
}

static void tegra_fiqdb_flush(void)
{
	while (!(uart_read(UART_LSR) & UART_LSR_TEMT))
		cpu_relax();

static inline u32 apb_readl(unsigned long offset)
{
    return readl(IO_TO_VIRT(offset));
}

#include <asm/io.h>
#include <asm/arch/hardware.h>

#define OSC_FREQ_DET			0x58
#define OSC_FREQ_DET_TRIG		(1<<31)

#define OSC_FREQ_DET_STATUS		0x5C
#define OSC_FREQ_DET_BUSY		(1<<31)
#define OSC_FREQ_DET_CNT_MASK		0xFFFF

#define clk_writel(value, reg) \
	__raw_writel(value, (u32)reg_clk_base + (reg))
#define clk_readl(reg) \
	__raw_readl((u32)reg_clk_base + (reg))

static void __iomem *reg_clk_base = (void __iomem *) IO_TO_VIRT(TEGRA_CLK_RESET_BASE);

unsigned long clk_measure_input_freq(void)
{
	u32 clock_autodetect;
	clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
	do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
	clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
	if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
		return 12000000;
	} else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
		return 13000000;
	} else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
		return 19200000;
	} else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
		return 26000000;