int flash_physical_protect_at_boot(enum flash_wp_range range)
{
	switch (range) {
	case FLASH_WP_NONE:
		/* Unlock UMA transactions */
		if (IS_BIT_SET(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK))
			CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
		/* Clear protection bits in status register */
		return flash_set_status_for_prot(0, 0);
	case FLASH_WP_RO:
		/* Unlock UMA transactions */
		if (IS_BIT_SET(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK))
			CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
		/* Protect read-only */
		return flash_write_prot_reg(
			    WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
			    WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE);
	case FLASH_WP_ALL:
		/* Protect all */
		/*
		 * Set UMA_LOCK bit for locking all UMA transaction.
		 * But we still can read directly from flash mapping address
		 */
		return flash_uma_lock(1);
	default:
		return EC_ERROR_INVAL;
	}
}

uint8_t get_input_index()
{
  uint8_t i = 0;
  uint8_t input = ~SWICH;
  for(i = 0; i < 8; i++)
  {
    if (input % 2)
    {
      if (debounce_counter >= 5 && IS_BIT_SET(input_flag, i))
      {
        return i;
      }
      else
      {
        if (input_flag && !IS_BIT_SET(input_flag, i))
        {
          input_flag = 0x00;
        }
        if (IS_BIT_SET(input_flag, i))
        {
          debounce_counter++;
        }
        else
        {
          SET_BIT(input_flag, i);
        }
        return 0xFF;
      }
    }
    input /= 2;
  }
  return 0xFF;
}

/**
 * SPI initial.
 *
 * @param none
 * @return none
 */
static void spi_init(void)
{
	int i;
	/* Enable clock for SPI peripheral */
	clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
			CGC_MODE_RUN | CGC_MODE_SLEEP);

	/* Disabling spi module */
	for (i = 0; i < spi_devices_used; i++)
		spi_enable(spi_devices[i].port, 0);

	/* Disabling spi irq */
	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIR);
	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIW);

	/* Setting clocking mode to normal mode */
	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCM);
	/* Setting 8bit mode transfer */
	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_MOD);
	/* Set core clock division factor in order to obtain the spi clock */
	spi_freq_changed();

	/* We emit zeros in idle (default behaivor) */
	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);

	CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
	CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
			NPCX_DEV_CTL4_SPI_SP_SEL));
	/* Cleaning junk data in the buffer */
	clear_databuf();
}

/* runqueue operations */
static inline void __add_to_runqueue(runqueue_t *runq, uthread_struct_t *u_elem)
{
	unsigned int uprio, ugroup;
	uthread_head_t *uhead;

	/* Find a position in the runq based on priority and group.
	 * Update the masks. */
	uprio = u_elem->uthread_priority;
	ugroup = u_elem->uthread_gid;

	/* Insert at the tail */
	uhead = &runq->prio_array[uprio].group[ugroup];
	TAILQ_INSERT_TAIL(uhead, u_elem, uthread_runq);

	/* Update information */
	if(!IS_BIT_SET(runq->prio_array[uprio].group_mask, ugroup))
		SET_BIT(runq->prio_array[uprio].group_mask, ugroup);

	runq->uthread_tot++;

	runq->uthread_prio_tot[uprio]++;
	if(!IS_BIT_SET(runq->uthread_mask, uprio))
		SET_BIT(runq->uthread_mask, uprio);

	runq->uthread_group_tot[ugroup]++;
	if(!IS_BIT_SET(runq->uthread_group_mask[ugroup], uprio))
		SET_BIT(runq->uthread_group_mask[ugroup], uprio);

	return;
}

void	Emulator::HandleInterupt()
{
  if (!mMasterIntFlag)
    return ;
  BYTE regIntEnable = mInterrupEnable;
  BYTE regIntReq = mIOPorts[0x0F];

  for (int i = 0; i < 5; i++)
    {
      if (IS_BIT_SET(regIntReq, i) && IS_BIT_SET(regIntEnable, i))
	{
	  Push(mPC);
	  switch (i)
	    {
	    case 0: mPC = 0x40; break;
	    case 1: mPC = 0x48; break;
	    case 2: mPC = 0x50; break;
	    case 3: mPC = 0x58; break;
	    case 4: mPC = 0x60; break;
	    }
	  RESET_BIT(mIOPorts[0x0F], i);
	  mMasterIntFlag = false;
	  mIsHalted = false;
	}
    }
}

int RCyc_I2C_WriteDeviceRegister(unsigned char Device, unsigned char Index, unsigned char Value)
{
	// write device address with R/W bit = 0 (writing)
	RCyc_I2C_SetDataCtrl(Device & 0xFE, (1 << bI2C_CTRL_START) | (1 << bI2C_CTRL_WRITE));
	
	// error, device does not answer
	if (IS_BIT_SET(IORD_I2C_STATUS(AdI2C), bI2C_STATUS_LRA))
	{
		IOWR_I2C_CTRL(AdI2C, (1 << bI2C_CTRL_STOP));
		return RCYC_I2C_ENODEV;
	}
	
	// write register address
	RCyc_I2C_SetDataCtrl(Index, (1 << bI2C_CTRL_WRITE));
	
	// error, wrong acknowledge
	if (IS_BIT_SET(IORD_I2C_STATUS(AdI2C), bI2C_STATUS_LRA))
	{
		IOWR_I2C_CTRL(AdI2C, (1 << bI2C_CTRL_STOP));
		return RCYC_I2C_EBADACK;
	}
	
	// write value
	RCyc_I2C_SetDataCtrl(Value, (1 << bI2C_CTRL_STOP) | (1 << bI2C_CTRL_WRITE));
	
	// error, wrong acknowledge
	if (IS_BIT_SET(IORD_I2C_STATUS(AdI2C), bI2C_STATUS_LRA))
	{
		// TODO : check in VHDL to see if this is requireds
		IOWR_I2C_CTRL(AdI2C, (1 << bI2C_CTRL_STOP));
		return RCYC_I2C_EBADACK;
	}
		
	return RCYC_I2C_SUCCESS;
}

BYTE	Emulator::GetJoypadStatus()
{
  BYTE joystatus = 0;

  joystatus = mIOPorts[0] & ~0xF;
  if (!IS_BIT_SET(joystatus, 4))
    {
      if (!IS_BIT_SET(mJoypadMask, Down))
	SET_BIT(joystatus, 3);
      if (!IS_BIT_SET(mJoypadMask, Up))
	SET_BIT(joystatus, 2);
      if (!IS_BIT_SET(mJoypadMask, Left))
	SET_BIT(joystatus, 1);
      if (!IS_BIT_SET(mJoypadMask, Right))
	SET_BIT(joystatus, 0);
    }

  if (!IS_BIT_SET(joystatus, 5))
    {
      if (!IS_BIT_SET(mJoypadMask, Start))
	SET_BIT(joystatus, 3);
      if (!IS_BIT_SET(mJoypadMask, Select))
	SET_BIT(joystatus, 2);
      if (!IS_BIT_SET(mJoypadMask, BUTTON_B))
	SET_BIT(joystatus, 1);
      if (!IS_BIT_SET(mJoypadMask, BUTTON_A))
	SET_BIT(joystatus, 0);
    }
  return joystatus;
}

int main(void)
{
        unsigned int *bitarray = NULL;
        unsigned int bitarray_size;
        unsigned int i, j, n;

        double s;

        if (sizeof(unsigned int) != BYTES_PER_INT) {
                fprintf(stderr, "size of 'unsigned int' is expected to be %d instead of %d\n", 
                        BYTES_PER_INT, 
                        sizeof(unsigned int));
                return 1;
        }

        /* this is how many 'unsigned int's needed to store PRIMES_UPPER_BOUND bits */
        bitarray_size = PRIMES_UPPER_BOUND / BITS_PER_INT 
                      + ((PRIMES_UPPER_BOUND % BITS_PER_INT) == 0 ? 0 : 1);

/*        printf("PRIMES_UPPER_BOUND=%d\n", PRIMES_UPPER_BOUND); */
/*        printf("BITS_PER_INT=%d\n", BITS_PER_INT); */
/*        printf("bitarray_size=%d\n", bitarray_size); */

        /* allocate bitarray and turn all the bits on */
        bitarray = (unsigned int*)malloc(sizeof(unsigned int)*bitarray_size);
        for (i = 0; i < bitarray_size; i++)
                bitarray[i] = ALL_ON;

        /* determine prime numbers by Sieve of Eratosthenes */
        for (i = 2; i <= PRIMES_UPPER_BOUND; i++) {
                if (! IS_BIT_SET(bitarray, i))
                        /* i is not a prime */
                        continue;
                /* i is prime: remove from the list all the numbers 
                 * divisible by i except itself
                 */
/*                printf("prime %6d\n", i); */
                for (n = 2; ; n++) {
                        j = i*n;
                        if (j >= PRIMES_UPPER_BOUND)
                                break;
                        UNSET_BIT(bitarray, j);
                }
        }

        /* compute sum of all the primes */
        s = 0;
        for (i = 2; i < PRIMES_UPPER_BOUND; i++)
                if (IS_BIT_SET(bitarray, i))
                        s += i;

        printf("%.0f\n", s);

        free(bitarray);
        return 0;
}

/**
 * Flush an SPI transaction and receive data from slave.
 *
 * @param   spi_device  device to talk to
 * @param   txdata  transfer data
 * @param   txlen   transfer length
 * @param   rxdata  receive data
 * @param   rxlen   receive length
 * @return  success
 * @notes   set master transaction mode in npcx chip
 */
int spi_transaction(const struct spi_device_t *spi_device,
		const uint8_t *txdata, int txlen,
		uint8_t *rxdata, int rxlen)
{
	int i = 0;
	enum gpio_signal gpio = spi_device->gpio_cs;

	/* Make sure CS# is a GPIO output mode. */
	gpio_set_flags(gpio, GPIO_OUTPUT);
	/* Make sure CS# is deselected */
	gpio_set_level(gpio, 1);
	/* Cleaning junk data in the buffer */
	clear_databuf();
	/* Assert CS# to start transaction */
	gpio_set_level(gpio, 0);
	CPRINTS("NPCX_SPI_DATA=%x", NPCX_SPI_DATA);
	CPRINTS("NPCX_SPI_CTL1=%x", NPCX_SPI_CTL1);
	CPRINTS("NPCX_SPI_STAT=%x", NPCX_SPI_STAT);
	/* Writing the data */
	for (i = 0; i < txlen; ++i) {
		/* Making sure we can write */
		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
			;
		/* Write the data */
		NPCX_SPI_DATA =  txdata[i];
		CPRINTS("txdata[i]=%x", txdata[i]);
		/* Waiting till reading is finished */
		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
			;
		/* Reading the (dummy) data */
		clear_databuf();
	}
	CPRINTS("write end");
	/* Reading the data */
	for (i = 0; i < rxlen; ++i) {
		/* Making sure we can write */
		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
			;
		/* Write the (dummy) data */
		NPCX_SPI_DATA =  0;
		/* Wait till reading is finished */
		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
			;
		/* Reading the data */
		rxdata[i] = (uint8_t)NPCX_SPI_DATA;
		CPRINTS("rxdata[i]=%x", rxdata[i]);
	}
	/* Deassert CS# (high) to end transaction */
	gpio_set_level(gpio, 1);

	return EC_SUCCESS;
}

PCHAR
FilterDriverOperation(UCHAR OperationType)
{
    if (IS_BIT_SET(OperationType, OP_LOAD))
        return "load";

    if (IS_BIT_SET(OperationType, OP_REGLOAD))
        return "regload";

    LOG(LOG_SS_LEARN, LOG_PRIORITY_DEBUG, ("FilterDriverOperation: invalid operation type %d\n", OperationType));

    return "load";
}

void Mapper4::SyncBanks()
{
	g_nesMainboard->GetSynchroniser()->Synchronise();

	Switch8kPrgBank( banks[7], 1 );
	Switch8kPrgBank( Get8kPrgBankCount() - 1, 3 );

	if ( IS_BIT_SET( bankSwapByte, 6 ) )
	{
		Switch8kPrgBank( Get8kPrgBankCount() - 2, 0 );
		Switch8kPrgBank( banks[6], 2 );
	}
	else
	{
		Switch8kPrgBank( banks[6], 0 );
		Switch8kPrgBank( Get8kPrgBankCount() - 2, 2 );
	}
/*
           0: Select 2 KB CHR bank at PPU $0000-$07FF (or $1000-$17FF);
           1: Select 2 KB CHR bank at PPU $0800-$0FFF (or $1800-$1FFF);
           2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF);
           3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF);
           4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF);
           5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF);
*/
	if ( IS_BIT_SET( bankSwapByte, 7 ) )
	{
		Switch1kChrBank( banks[2], 0 );
		Switch1kChrBank( banks[3], 1 );
		Switch1kChrBank( banks[4], 2 );
		Switch1kChrBank( banks[5], 3 );
		
		Switch1kChrBank( banks[0], 4 );
		Switch1kChrBank( banks[0] + 1, 5 );
		Switch1kChrBank( banks[1], 6 );
		Switch1kChrBank( banks[1] + 1, 7 );
	}
	else
	{
		Switch1kChrBank( banks[0], 0 );
		Switch1kChrBank( banks[0] + 1, 1 );
		Switch1kChrBank( banks[1], 2 );
		Switch1kChrBank( banks[1] + 1, 3 );

		Switch1kChrBank( banks[2], 4 );
		Switch1kChrBank( banks[3], 5 );
		Switch1kChrBank( banks[4], 6 );
		Switch1kChrBank( banks[5], 7 );
	}
}

uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
{
	uint8_t data_value;

	/* Disable interrupts */
	interrupt_disable();

	/* Lock host CFG module */
	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
	/* Enable Core-to-Host Modules Access */
	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
	/* Enable Core access to CFG module */
	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
	/* Verify Core read/write to host modules is not in progress */
	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD))
		;
	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSWR))
		;


	/* Specify the io_offset A0 = 0. the index register is accessed */
	NPCX_IHIOA = io_offset;
	/* Write the data. This starts the write access to the host module */
	NPCX_IHD = index_value;
	/* Wait while Core write operation is in progress */
	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSWR))
		;

	/* Specify the io_offset A0 = 1. the data register is accessed */
	NPCX_IHIOA = io_offset+1;
	/* Start a Core read from host module */
	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
	/* Wait while Core read operation is in progress */
	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD))
		;
	/* Read the data */
	data_value = NPCX_IHD;

	/* Disable Core access to CFG module */
	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
	/* Disable Core-to-Host Modules Access */
	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
	/* unlock host CFG  module */
	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);

	/* Enable interrupts */
	interrupt_enable();

	return data_value;
}

PCHAR
FilterOperation(UCHAR OperationType)
{
    if (IS_BIT_SET(OperationType, OP_READ_WRITE) &&
            (IS_BIT_SET(OperationType, OP_DELETE) || IS_BIT_SET(OperationType, OP_EXECUTE)))

        return "all";


    if (IS_BIT_SET(OperationType, OP_DELETE))
        return "delete";

    if (IS_BIT_SET(OperationType, OP_READ_WRITE))
        return "rw";

    if (IS_BIT_SET(OperationType, OP_READ))
        return "read";

    if (IS_BIT_SET(OperationType, OP_WRITE))
        return "write";

    if (IS_BIT_SET(OperationType, OP_EXECUTE))
        return "execute";


    //XXX what about when multiple bits are set? read + delete?
    LOG(LOG_SS_LEARN, LOG_PRIORITY_DEBUG, ("FilterOperation: invalid operation type %d\n", OperationType));


    return "all";
}

void lpc_port80_interrupt(void)
{
	/* Send port 80 data to UART continuously if FIFO is not empty */
	while (IS_BIT_SET(NPCX_DP80STS, 6))
		port_80_write(NPCX_DP80BUF);

	/* If FIFO is overflow */
	if (IS_BIT_SET(NPCX_DP80STS, 7)) {
		SET_BIT(NPCX_DP80STS, 7);
		CPRINTS("DP80 FIFO Overflow!");
	}

	/* Clear pending bit of host writing */
	SET_BIT(NPCX_DP80STS, 5);
}

/* HWTimer event handlers */
void __hw_clock_event_set(uint32_t deadline)
{
	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND);
	int32_t  evt_cnt_us;
	/* Is deadline min value? */
	if (evt_expired_us != 0 && evt_expired_us < deadline)
		return;

	/* mark min event value */
	evt_expired_us = deadline;
	evt_cnt_us = deadline - __hw_clock_source_read();
#if DEBUG_TMR
	evt_cnt_us_dbg = deadline - __hw_clock_source_read();
#endif
	/* Deadline is behind current timer */
	if (evt_cnt_us < 0)
		evt_cnt_us = 1;

	/* Event module disable */
	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);

	/*
	 * ITIM count down : event expired : Unit: 1/32768 sec
	 * It must exceed evt_expired_us for process_timers function
	 */
	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick);
	if (evt_cnt > TICK_EVT_MAX_CNT) {
		CPRINTS("Event overflow! 0x%08x, us is %d\r\n",
				evt_cnt, evt_cnt_us);
		evt_cnt = TICK_EVT_MAX_CNT;
	}

	/* Wait for module disable to take effect before updating count */
	while (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
		;

	NPCX_ITCNT16(ITIM_EVENT_NO) = MAX(evt_cnt, 1);

	/* Event module enable */
	SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);

	/* Wait for module enable */
	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
		;

	/* Enable interrupt of ITIM */
	task_enable_irq(ITIM16_INT(ITIM_EVENT_NO));
}

int flash_physical_read(int offset, int size, char *data)
{
	int dest_addr = offset;
	uint32_t idx;

	/* Disable tri-state */
	TRISTATE_FLASH(0);
	/* Chip Select down. */
	flash_cs_level(0);

	/* Set read address */
	flash_set_address(dest_addr);
	/* Start fast read - 1110 1001 - EXEC, WR, CMD, ADDR */
	flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);

	/* Burst read transaction */
	for (idx = 0; idx < size; idx++) {
		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
		NPCX_UMA_CTS  = MASK_RD_1BYTE;
		/* wait for UMA to complete */
		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
			;
		/* Get read transaction results*/
		data[idx] = NPCX_UMA_DB0;
	}

	/* Chip Select up */
	flash_cs_level(1);
	/* Enable tri-state */
	TRISTATE_FLASH(1);
	return EC_SUCCESS;
}

int flash_physical_is_erased(uint32_t offset, int size)
{
	int dest_addr = offset;
	uint32_t idx;
	uint8_t temp;

	/* Chip Select down. */
	flash_cs_level(0);

	/* Set read address */
	flash_set_address(dest_addr);
	/* Start fast read -1110 1001 - EXEC, WR, CMD, ADDR */
	flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);

	/* Burst read transaction */
	for (idx = 0; idx < size; idx++) {
		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
		NPCX_UMA_CTS  = MASK_RD_1BYTE;
		/* Wait for UMA to complete */
		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
			;
		/* Get read transaction results */
		temp = NPCX_UMA_DB0;
		if (temp != 0xFF)
			break;
	}

	/* Chip Select up */
	flash_cs_level(1);

	if (idx == size)
		return 1;
	else
		return 0;
}

unsigned char *interleave_uint32s(uint32_t *numbers, uint16_t num)
{
    uint8_t i;
    uint16_t j, bitmap_size;
    unsigned char *bitmap = NULL;

    assert(num < 16384);

    /* bitmap_size in bits (hence the `*8`) */
    bitmap_size = (sizeof(uint32_t) * num * 8);
    bitmap = (unsigned char *)calloc(bitmap_size / 8, sizeof(unsigned char));
    if (bitmap == NULL) {
        return NULL;
    }

    /* i is the bit offset within a number
     * j is the current number offset */
    for (i = 0; i * num < bitmap_size; i++) {
        for (j = 0; j < num; j++) {
            /* Start with the last number, as we built up the bitmap
             * from right to left */
            if (IS_BIT_SET(numbers[(num - 1) - j], i)) {
                set_bit_sized(bitmap, bitmap_size/8, (i * num) + j);
            }
        }
    }
    return bitmap;
}

static int flash_wait_ready(int timeout)
{
	uint8_t mask = SPI_FLASH_SR1_BUSY;

	if (timeout <= 0)
		return EC_ERROR_INVAL;

	/* Chip Select down. */
	flash_cs_level(0);
	/* Command for Read status register */
	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
	while (timeout > 0) {
		/* Read status register */
		NPCX_UMA_CTS  = MASK_RD_1BYTE;
		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
			;
		/* Busy bit is clear */
		if ((NPCX_UMA_DB0 & mask) == 0)
			break;
		if (--timeout > 0)
			msleep(1);
	}; /* Wait for Busy clear */

	/* Chip Select high. */
	flash_cs_level(1);

	if (timeout == 0)
		return EC_ERROR_TIMEOUT;

	return EC_SUCCESS;
}

void	Emulator::UpdateTimer(int nbCycles)
{
  mDIVCounter -= nbCycles;
  if (mDIVCounter <= 0)
    {
      mIOPorts[DIV]++;
      mDIVCounter = DIV_NBCYCLE_TO_UPDATE;
    }

  if (IS_BIT_SET(mIOPorts[TAC], 2)) // Clock on
    {
      mTIMACounter -= nbCycles;
      if (mTIMACounter <= 0)
	{
	  if (mIOPorts[TIMA] == 0xFF) // Overflow
	    {
	      mIOPorts[TIMA] = mIOPorts[TMA];
	      REQ_INT(TIMER);
	    }
	  else
	    mIOPorts[TIMA]++;
	  switch (mIOPorts[TAC] & 0x03) // 3 = 11
	    {
	    case 0: mTIMACounter = 1024; break; // 69905 / (4194Hz / 60)
	    case 1: mTIMACounter = 16; break; // 69905 / (268400Hz / 60)
	    case 2: mTIMACounter = 64; break; // 69905 / (65536Hz / 60)
	    case 3: mTIMACounter = 256; break; // 69905 / (16384Hz / 60)
	    }
	}
    }
}