本文整理汇总了C++中bus_space_map函数的典型用法代码示例。如果您正苦于以下问题:C++ bus_space_map函数的具体用法?C++ bus_space_map怎么用?C++ bus_space_map使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了bus_space_map函数的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: pxauart_match
static int
pxauart_match(device_t parent, cfdata_t cf, void *aux)
{
struct pxaip_attach_args *pxa = aux;
bus_space_tag_t bt = &pxa2x0_a4x_bs_tag; /* XXX: This sucks */
bus_space_handle_t bh;
struct pxa2x0_gpioconf *gpioconf;
u_int gpio;
int rv, i;
switch (pxa->pxa_addr) {
case PXA2X0_FFUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_FFUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_ffuart_gpioconf :
pxa27x_com_ffuart_gpioconf;
break;
case PXA2X0_STUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_STUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_stuart_gpioconf :
pxa27x_com_stuart_gpioconf;
break;
case PXA2X0_BTUART_BASE: /* XXX: Config file option ... */
if (pxa->pxa_intr != PXA2X0_INT_BTUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_btuart_gpioconf :
pxa27x_com_btuart_gpioconf;
break;
case PXA2X0_HWUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_HWUART)
return (0);
if (CPU_IS_PXA270)
return (0);
gpioconf = pxa25x_com_hwuart_gpioconf;
break;
default:
return (0);
}
for (i = 0; gpioconf[i].pin != -1; i++) {
gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
return (0);
}
pxa->pxa_size = 0x20;
if (com_is_console(bt, pxa->pxa_addr, NULL))
return (1);
if (bus_space_map(bt, pxa->pxa_addr, pxa->pxa_size, 0, &bh))
return (0);
/* Make sure the UART is enabled */
bus_space_write_1(bt, bh, com_ier, IER_EUART);
rv = comprobe1(bt, bh);
bus_space_unmap(bt, bh, pxa->pxa_size);
return (rv);
}
开发者ID:krytarowski,项目名称:netbsd-current-src-sys,代码行数:66,代码来源:pxa2x0_com.c
示例2: ae_attach
/*
* ae_attach:
*
* Attach an ae interface to the system.
*/
void
ae_attach(device_t parent, device_t self, void *aux)
{
const uint8_t *enaddr;
prop_data_t ea;
struct ae_softc *sc = device_private(self);
struct arbus_attach_args *aa = aux;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
int i, error;
sc->sc_dev = self;
callout_init(&sc->sc_tick_callout, 0);
printf(": Atheros AR531X 10/100 Ethernet\n");
/*
* Try to get MAC address.
*/
ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address");
if (ea == NULL) {
printf("%s: unable to get mac-addr property\n",
device_xname(sc->sc_dev));
return;
}
KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
enaddr = prop_data_data_nocopy(ea);
/* Announce ourselves. */
printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev),
ether_sprintf(enaddr));
sc->sc_cirq = aa->aa_cirq;
sc->sc_mirq = aa->aa_mirq;
sc->sc_st = aa->aa_bst;
sc->sc_dmat = aa->aa_dmat;
SIMPLEQ_INIT(&sc->sc_txfreeq);
SIMPLEQ_INIT(&sc->sc_txdirtyq);
/*
* Map registers.
*/
sc->sc_size = aa->aa_size;
if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0,
&sc->sc_sh)) != 0) {
printf("%s: unable to map registers, error = %d\n",
device_xname(sc->sc_dev), error);
goto fail_0;
}
/*
* Allocate the control data structures, and create and load the
* DMA map for it.
*/
if ((error = bus_dmamem_alloc(sc->sc_dmat,
sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
1, &sc->sc_cdnseg, 0)) != 0) {
printf("%s: unable to allocate control data, error = %d\n",
device_xname(sc->sc_dev), error);
goto fail_1;
}
if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg,
sizeof(struct ae_control_data), (void **)&sc->sc_control_data,
BUS_DMA_COHERENT)) != 0) {
printf("%s: unable to map control data, error = %d\n",
device_xname(sc->sc_dev), error);
goto fail_2;
}
if ((error = bus_dmamap_create(sc->sc_dmat,
sizeof(struct ae_control_data), 1,
sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
printf("%s: unable to create control data DMA map, "
"error = %d\n", device_xname(sc->sc_dev), error);
goto fail_3;
}
if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
sc->sc_control_data, sizeof(struct ae_control_data), NULL,
0)) != 0) {
printf("%s: unable to load control data DMA map, error = %d\n",
device_xname(sc->sc_dev), error);
goto fail_4;
}
/*
* Create the transmit buffer DMA maps.
*/
for (i = 0; i < AE_TXQUEUELEN; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
AE_NTXSEGS, MCLBYTES, 0, 0,
&sc->sc_txsoft[i].txs_dmamap)) != 0) {
//.........这里部分代码省略.........
开发者ID:krytarowski,项目名称:netbsd-current-src-sys,代码行数:101,代码来源:if_ae.c
示例3: fdc_isa_probe
static int
fdc_isa_probe(device_t parent, cfdata_t match, void *aux)
{
struct isa_attach_args *ia = aux;
bus_space_tag_t iot;
bus_space_handle_t ioh, ctl_ioh, base_ioh;
int rv, iobase;
iot = ia->ia_iot;
rv = 0;
if (ia->ia_nio < 1)
return (0);
if (ia->ia_nirq < 1)
return (0);
if (ia->ia_ndrq < 1)
return (0);
if (ISA_DIRECT_CONFIG(ia))
return (0);
/* Disallow wildcarded I/O addresses. */
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
return (0);
/* Don't allow wildcarded IRQ/DRQ. */
if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
return (0);
if (ia->ia_drq[0].ir_drq == ISA_UNKNOWN_DRQ)
return (0);
/* Map the I/O space. */
iobase = ia->ia_io[0].ir_addr;
if (bus_space_map(iot, iobase, 6 /* FDC_NPORT */, 0, &base_ioh))
return (0);
if (bus_space_subregion(iot, base_ioh, 2, 4, &ioh)) {
bus_space_unmap(iot, base_ioh, 6);
return (0);
}
if (bus_space_map(iot, iobase + fdctl + 2, 1, 0, &ctl_ioh)) {
bus_space_unmap(iot, base_ioh, 6);
return (0);
}
/* Not needed for the rest of the probe. */
bus_space_unmap(iot, ctl_ioh, 1);
/* reset */
bus_space_write_1(iot, ioh, fdout, 0);
delay(100);
bus_space_write_1(iot, ioh, fdout, FDO_FRST);
/* see if it can handle a command */
if (out_fdc(iot, ioh, NE7CMD_SPECIFY) < 0)
goto out;
out_fdc(iot, ioh, 0xdf);
out_fdc(iot, ioh, 2);
rv = 1;
ia->ia_nio = 1;
ia->ia_io[0].ir_size = FDC_NPORT;
ia->ia_nirq = 1;
ia->ia_ndrq = 1;
ia->ia_niomem = 0;
out:
bus_space_unmap(iot, base_ioh, 6 /* FDC_NPORT */);
return (rv);
}
开发者ID:eyberg,项目名称:rumpkernel-netbsd-src,代码行数:74,代码来源:fdc_isa.c
示例4: yds_configure_legacy
/*
* This routine is called after all the ISA devices are configured,
* to avoid conflict.
*/
static void
yds_configure_legacy(device_t self)
#define FLEXIBLE (sc->sc_flags & YDS_CAP_LEGACY_FLEXIBLE)
#define SELECTABLE (sc->sc_flags & YDS_CAP_LEGACY_SELECTABLE)
{
static const bus_addr_t opl_addrs[] = {0x388, 0x398, 0x3A0, 0x3A8};
static const bus_addr_t mpu_addrs[] = {0x330, 0x300, 0x332, 0x334};
struct yds_softc *sc;
pcireg_t reg;
device_t dev;
int i;
sc = device_private(self);
if (!FLEXIBLE && !SELECTABLE)
return;
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY);
reg &= ~0x8133c03f; /* these bits are out of interest */
reg |= ((YDS_PCI_EX_LEGACY_IMOD) |
(YDS_PCI_LEGACY_FMEN |
YDS_PCI_LEGACY_MEN /*| YDS_PCI_LEGACY_MIEN*/));
reg |= YDS_PCI_EX_LEGACY_SMOD_DISABLE;
if (FLEXIBLE) {
pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);
delay(100*1000);
}
/* Look for OPL */
dev = 0;
for (i = 0; i < sizeof(opl_addrs) / sizeof(bus_addr_t); i++) {
if (SELECTABLE) {
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
YDS_PCI_LEGACY, reg | (i << (0+16)));
delay(100*1000); /* wait 100ms */
} else
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
YDS_PCI_FM_BA, opl_addrs[i]);
if (bus_space_map(sc->sc_opl_iot,
opl_addrs[i], 4, 0, &sc->sc_opl_ioh) == 0) {
struct audio_attach_args aa;
aa.type = AUDIODEV_TYPE_OPL;
aa.hwif = aa.hdl = NULL;
dev = config_found(self, &aa, audioprint);
if (dev == 0)
bus_space_unmap(sc->sc_opl_iot,
sc->sc_opl_ioh, 4);
else {
if (SELECTABLE)
reg |= (i << (0+16));
break;
}
}
}
if (dev == 0) {
reg &= ~YDS_PCI_LEGACY_FMEN;
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
YDS_PCI_LEGACY, reg);
} else {
/* Max. volume */
YWRITE4(sc, YDS_LEGACY_OUT_VOLUME, 0x3fff3fff);
YWRITE4(sc, YDS_LEGACY_REC_VOLUME, 0x3fff3fff);
}
/* Look for MPU */
dev = NULL;
for (i = 0; i < sizeof(mpu_addrs) / sizeof(bus_addr_t); i++) {
if (SELECTABLE)
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
YDS_PCI_LEGACY, reg | (i << (4+16)));
else
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
YDS_PCI_MPU_BA, mpu_addrs[i]);
if (bus_space_map(sc->sc_mpu_iot,
mpu_addrs[i], 2, 0, &sc->sc_mpu_ioh) == 0) {
struct audio_attach_args aa;
aa.type = AUDIODEV_TYPE_MPU;
aa.hwif = aa.hdl = NULL;
dev = config_found(self, &aa, audioprint);
if (dev == 0)
bus_space_unmap(sc->sc_mpu_iot,
sc->sc_mpu_ioh, 2);
else {
if (SELECTABLE)
reg |= (i << (4+16));
break;
}
}
}
if (dev == 0) {
reg &= ~(YDS_PCI_LEGACY_MEN | YDS_PCI_LEGACY_MIEN);
pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);
}
sc->sc_mpu = dev;
}
开发者ID:ryoon,项目名称:netbsd-xhci,代码行数:100,代码来源:yds.c
示例5: ohci_aubus_attach
void
ohci_aubus_attach(struct device *parent, struct device *self, void *aux)
{
ohci_softc_t *sc = (ohci_softc_t *)self;
void *ih;
usbd_status r;
uint32_t x, tmp;
struct aubus_attach_args *aa = aux;
r = 0;
sc->sc_size = USBH_SIZE;
sc->iot = aa->aa_st;
sc->sc_bus.dmatag = (bus_dma_tag_t)aa->aa_dt;
if (bus_space_map(sc->iot, USBH_BASE, USBH_SIZE, 0, &sc->ioh)) {
printf("%s: Unable to map USBH registers\n",
sc->sc_bus.bdev.dv_xname);
return;
}
/*
* Enable the USB Host controller here.
* As per 7.2 in the Au1500 manual:
*
* (1) Set CE bit to enable clocks.
* (2) Set E to enable OHCI
* (3) Clear HCFS in OHCI_CONTROL.
* (4) Wait for RD bit to be set.
*/
x = bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
x |= UE_CE;
bus_space_write_4(sc->iot, sc->ioh, USBH_ENABLE, x);
delay(10);
x |= UE_E;
#ifdef __MIPSEB__
x |= UE_BE;
#endif
bus_space_write_4(sc->iot, sc->ioh, USBH_ENABLE, x);
delay(10);
x = bus_space_read_4(sc->iot, sc->ioh, OHCI_CONTROL);
x &= ~(OHCI_HCFS_MASK);
bus_space_write_4(sc->iot, sc->ioh, OHCI_CONTROL, x);
delay(10);
/* Need to read USBH_ENABLE twice in succession according to
* au1500 Errata #7.
*/
for (x = 100; x; x--) {
bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
tmp = bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
if (tmp&UE_RD)
break;
delay(1000);
}
printf(": Au1X00 OHCI\n");
/* Disable OHCI interrupts */
bus_space_write_4(sc->iot, sc->ioh, OHCI_INTERRUPT_DISABLE,
OHCI_ALL_INTRS);
/* hook interrupt */
ih = au_intr_establish(aa->aa_irq[0], 0, IPL_USB, IST_LEVEL_LOW,
ohci_intr, sc);
if (ih == NULL) {
printf("%s: couldn't establish interrupt\n",
sc->sc_bus.bdev.dv_xname);
}
if (x)
r = ohci_init(sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n",
sc->sc_bus.bdev.dv_xname, r);
au_intr_disestablish(ih);
return;
}
/* Attach USB device */
sc->sc_child = config_found((void *)sc, &sc->sc_bus, usbctlprint);
}
开发者ID:MarginC,项目名称:kame,代码行数:79,代码来源:ohci_aubus.c
示例6: macfb_obio_attach
void
macfb_obio_attach(struct device *parent, struct device *self, void *aux)
{
struct obio_attach_args *oa = (struct obio_attach_args *) aux;
struct macfb_softc *sc = (struct macfb_softc *)self;
u_long length;
u_int32_t vbase1, vbase2;
struct macfb_devconfig *dc;
sc->card_id = 0;
sc->sc_tag = oa->oa_tag;
dc = malloc(sizeof(*dc), M_DEVBUF, M_WAITOK);
bzero(dc, sizeof(*dc));
switch (current_mac_model->class) {
case MACH_CLASSQ2:
if (current_mac_model->machineid != MACH_MACLC575) {
sc->sc_basepa = VALKYRIE_BASE;
length = 0x00100000; /* 1MB */
if (sc->sc_basepa <= mac68k_vidphys &&
mac68k_vidphys < (sc->sc_basepa + length))
sc->sc_fbofs = mac68k_vidphys - sc->sc_basepa;
else
sc->sc_fbofs = 0;
#ifdef DEBUG
printf(" @ %lx", sc->sc_basepa + sc->sc_fbofs);
#endif
if (bus_space_map(sc->sc_tag, VALKYRIE_CONTROL_BASE,
0x40, 0, &sc->sc_regh) != 0) {
printf(": can't map Valkyrie registers\n");
free(dc, M_DEVBUF);
return;
}
/* Disable interrupts */
bus_space_write_1(sc->sc_tag, sc->sc_regh, 0x18, 0x1);
bus_space_unmap(sc->sc_tag, sc->sc_regh, 0x40);
printf(": Valkyrie\n");
break;
}
/*
* Note: the only system in this class that does not have
* the Valkyrie chip -- at least, that we know of -- is
* the Performa/LC 57x series. This system has a version
* of the DAFB controller, instead.
*
* If this assumption proves false, we'll have to be more
* intelligent here.
*/
/*FALLTHROUGH*/
case MACH_CLASSQ:
if (bus_space_map(sc->sc_tag, DAFB_CONTROL_BASE, 0x120, 0,
&sc->sc_regh)) {
printf(": can't map DAFB registers\n");
free(dc, M_DEVBUF);
return;
}
sc->sc_basepa = DAFB_BASE;
length = 0x00100000; /* 1MB */
/* Compute the current frame buffer offset */
vbase1 = bus_space_read_4(sc->sc_tag, sc->sc_regh, 0x0) & 0xfff;
/*
* XXX The following exists because the DAFB v7 in these
* systems doesn't return reasonable values to use for fbofs.
* Ken'ichi Ishizaka gets credit for this hack. (sar 19990426)
* (Does this get us the correct result for _all_ DAFB-
* equipped systems and monitor combinations? It seems
* possible, if not likely...)
*/
switch (current_mac_model->machineid) {
case MACH_MACLC475:
case MACH_MACLC475_33:
case MACH_MACLC575:
case MACH_MACQ605:
case MACH_MACQ605_33:
vbase1 &= 0x3f;
break;
}
vbase2 = bus_space_read_4(sc->sc_tag, sc->sc_regh, 0x4) & 0xf;
sc->sc_fbofs = (vbase1 << 9) | (vbase2 << 5);
#ifdef DEBUG
printf(" @ %lx", sc->sc_basepa + sc->sc_fbofs);
#endif
/* Disable interrupts */
bus_space_write_4(sc->sc_tag, sc->sc_regh, 0x104, 0);
/* Clear any pending interrupts */
bus_space_write_4(sc->sc_tag, sc->sc_regh, 0x10C, 0);
bus_space_write_4(sc->sc_tag, sc->sc_regh, 0x110, 0);
bus_space_write_4(sc->sc_tag, sc->sc_regh, 0x114, 0);
//.........这里部分代码省略.........
开发者ID:avsm,项目名称:openbsd-xen-sys,代码行数:101,代码来源:grf_iv.c
示例7: asc_vsbus_attach
/*
* Attach this instance, and then all the sub-devices
*/
static void
asc_vsbus_attach(struct device *parent, struct device *self, void *aux)
{
struct vsbus_attach_args *va = aux;
struct asc_vsbus_softc *asc = (void *)self;
struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
int error;
asc_attached = 1;
/*
* Set up glue for MI code early; we use some of it here.
*/
sc->sc_glue = &asc_vsbus_glue;
asc->sc_bst = va->va_iot;
asc->sc_dmat = va->va_dmat;
error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR,
ASC_REG_END, 0, &asc->sc_bsh);
if (error) {
printf(": failed to map registers: error=%d\n", error);
return;
}
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR,
ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh);
if (error) {
printf(": failed to map ncr registers: error=%d\n", error);
return;
}
if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) {
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh,
ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh);
if (error) {
printf(": failed to map adr register: error=%d\n",
error);
return;
}
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh,
ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh);
if (error) {
printf(": failed to map dir register: error=%d\n",
error);
return;
}
} else {
/* This is a gross and disgusting kludge but it'll
* save a bunch of ugly code. Unlike the VS4000/60,
* the SCSI Address and direction registers are not
* near the SCSI NCR registers and are inside the
* block of general VAXstation registers. So we grab
* them from there and knowing the internals of the
* bus_space implementation, we cast to bus_space_handles.
*/
struct vsbus_softc *vsc = (struct vsbus_softc *) parent;
asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR);
asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR);
#if 0
printf("\n%s: adrh=0x%08lx dirh=0x%08lx", self->dv_xname,
asc->sc_adrh, asc->sc_dirh);
ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS;
#endif
}
error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1,
ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap);
switch (vax_boardtype) {
#if defined(VAX46)
case VAX_BTYP_46:
sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7;
break;
#endif
default:
sc->sc_id = 6; /* XXX need to get this from VMB */
break;
}
sc->sc_freq = ASC_FREQUENCY;
/* gimme MHz */
sc->sc_freq /= 1000000;
scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr,
&asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt);
asc->sc_cvec = va->va_cvec;
evcount_attach(&asc->sc_intrcnt, self->dv_xname,
(void *)&asc->sc_cvec, &evcount_intr);
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* Set up static configuration info.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
//.........这里部分代码省略.........
开发者ID:avsm,项目名称:openbsd-xen-sys,代码行数:101,代码来源:asc_vsbus.c
示例8: acpiec_getcrs
int
acpiec_getcrs(struct acpiec_softc *sc, struct acpi_attach_args *aa)
{
struct aml_value res;
bus_size_t ec_sc, ec_data;
int dtype, ctype;
char *buf;
int size, ret;
int64_t gpe;
struct acpi_ecdt *ecdt = aa->aaa_table;
extern struct aml_node aml_root;
/* Check if this is ECDT initialization */
if (ecdt) {
/* Get GPE, Data and Control segments */
sc->sc_gpe = ecdt->gpe_bit;
ctype = ecdt->ec_control.address_space_id;
ec_sc = ecdt->ec_control.address;
dtype = ecdt->ec_data.address_space_id;
ec_data = ecdt->ec_data.address;
/* Get devnode from header */
sc->sc_devnode = aml_searchname(&aml_root, ecdt->ec_id);
goto ecdtdone;
}
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "_GPE", 0, NULL, &gpe)) {
dnprintf(10, "%s: no _GPE\n", DEVNAME(sc));
return (1);
}
sc->sc_gpe = gpe;
if (aml_evalname(sc->sc_acpi, sc->sc_devnode, "_CRS", 0, NULL, &res)) {
dnprintf(10, "%s: no _CRS\n", DEVNAME(sc));
return (1);
}
/* Parse CRS to get control and data registers */
if (res.type != AML_OBJTYPE_BUFFER) {
dnprintf(10, "%s: unknown _CRS type %d\n",
DEVNAME(sc), res.type);
aml_freevalue(&res);
return (1);
}
size = res.length;
buf = res.v_buffer;
ret = acpiec_getregister(buf, size, &dtype, &ec_data);
if (ret <= 0) {
dnprintf(10, "%s: failed to read DATA from _CRS\n",
DEVNAME(sc));
aml_freevalue(&res);
return (1);
}
buf += ret;
size -= ret;
ret = acpiec_getregister(buf, size, &ctype, &ec_sc);
if (ret <= 0) {
dnprintf(10, "%s: failed to read S/C from _CRS\n",
DEVNAME(sc));
aml_freevalue(&res);
return (1);
}
buf += ret;
size -= ret;
if (size != 2 || *buf != RES_TYPE_ENDTAG) {
dnprintf(10, "%s: no _CRS end tag\n", DEVNAME(sc));
aml_freevalue(&res);
return (1);
}
aml_freevalue(&res);
/* XXX: todo - validate _CRS checksum? */
ecdtdone:
dnprintf(10, "%s: Data: 0x%x, S/C: 0x%x\n",
DEVNAME(sc), ec_data, ec_sc);
if (ctype == GAS_SYSTEM_IOSPACE)
sc->sc_cmd_bt = aa->aaa_iot;
else
sc->sc_cmd_bt = aa->aaa_memt;
if (bus_space_map(sc->sc_cmd_bt, ec_sc, 1, 0, &sc->sc_cmd_bh)) {
dnprintf(10, "%s: failed to map S/C reg.\n", DEVNAME(sc));
return (1);
}
if (dtype == GAS_SYSTEM_IOSPACE)
sc->sc_data_bt = aa->aaa_iot;
//.........这里部分代码省略.........
开发者ID:alenichev,项目名称:openbsd-kernel,代码行数:101,代码来源:acpiec.c
示例9: gtmpsc_hackinit
/*
* gtmpsc_hackinit - hacks required to supprt GTMPSC console
*/
STATIC int
gtmpsc_hackinit(struct gtmpsc_softc *sc, bus_space_tag_t iot,
bus_dma_tag_t dmat, bus_addr_t base, int unit, int brg,
int baudrate, tcflag_t tcflag)
{
gtmpsc_poll_sdma_t *cn_dmapage =
(gtmpsc_poll_sdma_t *)gtmpsc_cn_dmapage;
int error;
DPRINTF(("hackinit\n"));
memset(sc, 0, sizeof(struct gtmpsc_softc));
error = bus_space_map(iot, base + GTMPSC_BASE(unit), GTMPSC_SIZE, 0,
&sc->sc_mpsch);
if (error != 0)
goto fail0;
error = bus_space_map(iot, base + GTSDMA_BASE(unit), GTSDMA_SIZE, 0,
&sc->sc_sdmah);
if (error != 0)
goto fail1;
error = bus_dmamap_create(dmat, sizeof(gtmpsc_polltx_t), 1,
sizeof(gtmpsc_polltx_t), 0, BUS_DMA_NOWAIT, &sc->sc_txdma_map);
if (error != 0)
goto fail2;
error = bus_dmamap_load(dmat, sc->sc_txdma_map, cn_dmapage->tx,
sizeof(gtmpsc_polltx_t), NULL,
BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE);
if (error != 0)
goto fail3;
error = bus_dmamap_create(dmat, sizeof(gtmpsc_pollrx_t), 1,
sizeof(gtmpsc_pollrx_t), 0, BUS_DMA_NOWAIT,
&sc->sc_rxdma_map);
if (error != 0)
goto fail4;
error = bus_dmamap_load(dmat, sc->sc_rxdma_map, cn_dmapage->rx,
sizeof(gtmpsc_pollrx_t), NULL,
BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE);
if (error != 0)
goto fail5;
sc->sc_iot = iot;
sc->sc_dmat = dmat;
sc->sc_poll_sdmapage = cn_dmapage;
sc->sc_brg = brg;
sc->sc_baudrate = baudrate;
sc->sc_cflag = tcflag;
gtmpsc_txdesc_init(sc);
gtmpsc_rxdesc_init(sc);
return 0;
fail5:
bus_dmamap_destroy(dmat, sc->sc_rxdma_map);
fail4:
bus_dmamap_unload(dmat, sc->sc_txdma_map);
fail3:
bus_dmamap_destroy(dmat, sc->sc_txdma_map);
fail2:
bus_space_unmap(iot, sc->sc_sdmah, GTSDMA_SIZE);
fail1:
bus_space_unmap(iot, sc->sc_mpsch, GTMPSC_SIZE);
fail0:
return error;
}
开发者ID:ryo,项目名称:netbsd-src,代码行数:69,代码来源:gtmpsc.c
示例10: piixpm_attach
static void
piixpm_attach(device_t parent, device_t self, void *aux)
{
struct piixpm_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct i2cbus_attach_args iba;
pcireg_t base, conf;
pcireg_t pmmisc;
pci_intr_handle_t ih;
const char *intrstr = NULL;
int i, numbusses = 1;
sc->sc_dev = self;
sc->sc_iot = pa->pa_iot;
sc->sc_id = pa->pa_id;
sc->sc_pc = pa->pa_pc;
sc->sc_pcitag = pa->pa_tag;
pci_aprint_devinfo(pa, NULL);
if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
/* Read configuration */
conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
goto nopowermanagement;
/* check whether I/O access to PM regs is enabled */
pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC);
if (!(pmmisc & 1))
goto nopowermanagement;
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE);
if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) {
aprint_error_dev(self, "can't map power management I/O space\n");
goto nopowermanagement;
}
/*
* Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
* PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
* in the "Specification update" (document #297738).
*/
acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
PIIX_PM_PMTMR,
(PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
nopowermanagement:
/* SB800 rev 0x40+ needs special initialization */
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB &&
PCI_REVISION(pa->pa_class) >= 0x40) {
if (piixpm_sb800_init(sc) == 0) {
numbusses = 4;
goto attach_i2c;
}
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(self, "can't map smbus I/O space\n");
return;
}
sc->sc_poll = 1;
aprint_normal_dev(self, "");
if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
/* No PCI IRQ */
aprint_normal("interrupting at SMI, ");
} else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
/* Install interrupt handler */
if (pci_intr_map(pa, &ih) == 0) {
intrstr = pci_intr_string(pa->pa_pc, ih);
sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
piixpm_intr, sc);
if (sc->sc_smb_ih != NULL) {
aprint_normal("interrupting at %s", intrstr);
sc->sc_poll = 0;
}
}
}
if (sc->sc_poll)
aprint_normal("polling");
//.........这里部分代码省略.........
开发者ID:RyanLucchese,项目名称:rumpkernel-netbsd-src,代码行数:101,代码来源:piixpm.c
示例11: ixp425_attach
void
ixp425_attach(device_t self)
{
struct ixp425_softc *sc = device_private(self);
#if NPCI > 0
struct pcibus_attach_args pba;
#endif
sc->sc_dev = self;
sc->sc_iot = &ixp425_bs_tag;
ixp425_softc = sc;
printf("\n");
/*
* Mapping for GPIO Registers
*/
if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
0, &sc->sc_gpio_ioh))
panic("%s: unable to map GPIO registers", device_xname(self));
if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
0, &sc->sc_exp_ioh))
panic("%s: unable to map Expansion Bus registers",
device_xname(self));
#if NPCI > 0
/*
* Mapping for PCI CSR
*/
if (bus_space_map(sc->sc_iot, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
0, &sc->sc_pci_ioh))
panic("%s: unable to map PCI registers", device_xname(self));
/*
* Invoke the board-specific PCI initialization code
*/
ixp425_md_pci_init(sc);
/*
* Generic initialization of the PCI chipset.
*/
ixp425_pci_init(sc);
/*
* Initialize the DMA tags.
*/
ixp425_pci_dma_init(sc);
/*
* Attach the PCI bus.
*/
pba.pba_pc = &sc->ia_pci_chipset;
pba.pba_iot = &sc->sc_pci_iot;
pba.pba_memt = &sc->sc_pci_memt;
pba.pba_dmat = &sc->ia_pci_dmat;
pba.pba_bus = 0; /* bus number = 0 */
pba.pba_bridgetag = NULL;
pba.pba_intrswiz = 0; /* XXX */
pba.pba_intrtag = 0;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
PCI_FLAGS_MWI_OKAY;
(void) config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
开发者ID:krytarowski,项目名称:netbsd-current-src-sys,代码行数:67,代码来源:ixp425.c
示例12: nouveau_fifo_channel_create_
int
nouveau_fifo_channel_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int bar, u32 addr, u32 size, u32 pushbuf,
u64 engmask, int len, void **ptr)
{
struct nouveau_device *device = nv_device(engine);
struct nouveau_fifo *priv = (void *)engine;
struct nouveau_fifo_chan *chan;
struct nouveau_dmaeng *dmaeng;
unsigned long flags;
int ret;
/* create base object class */
ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
engmask, len, ptr);
chan = *ptr;
if (ret)
return ret;
/* validate dma object representing push buffer */
chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
if (!chan->pushdma)
return -ENOENT;
dmaeng = (void *)chan->pushdma->base.engine;
switch (chan->pushdma->base.oclass->handle) {
case NV_DMA_FROM_MEMORY_CLASS:
case NV_DMA_IN_MEMORY_CLASS:
break;
default:
return -EINVAL;
}
ret = dmaeng->bind(dmaeng, parent, chan->pushdma, &chan->pushgpu);
if (ret)
return ret;
/* find a free fifo channel */
spin_lock_irqsave(&priv->lock, flags);
for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) {
if (!priv->channel[chan->chid]) {
priv->channel[chan->chid] = nv_object(chan);
break;
}
}
spin_unlock_irqrestore(&priv->lock, flags);
if (chan->chid == priv->max) {
nv_error(priv, "no free channels\n");
return -ENOSPC;
}
/* map fifo control registers */
#ifdef __NetBSD__
chan->bst = nv_device_resource_tag(device, bar);
/* XXX errno NetBSD->Linux */
ret = -bus_space_map(chan->bst, nv_device_resource_start(device, bar) +
addr + (chan->chid * size), size, 0, &chan->bsh);
if (ret)
return ret;
chan->mapped = true;
#else
chan->user = ioremap(nv_device_resource_start(device, bar) + addr +
(chan->chid * size), size);
if (!chan->user)
return -EFAULT;
#endif
nouveau_event_trigger(priv->cevent, 0);
chan->size = size;
return 0;
}
开发者ID:ycui1984,项目名称:netbsd-src,代码行数:75,代码来源:nouveau_engine_fifo_base.c
示例13: pchbattach
void
pchbattach(struct device *parent, struct device *self, void *aux)
{
struct pchb_softc *sc = (struct pchb_softc *)self;
struct pci_attach_args *pa = aux;
int has_agp = 0, i, r;
switch (PCI_VENDOR(pa->pa_id)) {
case PCI_VENDOR_AMD:
printf("\n");
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_AMD_AMD64_0F_HT:
case PCI_PRODUCT_AMD_AMD64_10_HT:
case PCI_PRODUCT_AMD_AMD64_11_HT:
for (i = 0; i < AMD64HT_NUM_LDT; i++)
pchb_amd64ht_attach(self, pa, i);
break;
}
break;
case PCI_VENDOR_INTEL:
switch (PCI_PRODUCT(pa->pa_id)) {
/*
* As for Intel AGP, the host bridge is either in GFX mode
* (internal graphics) or in AGP mode. In GFX mode, we pretend
* to have AGP because the graphics memory access is very
* similar and the AGP GATT code will deal with this. In the
* latter case, the pci_get_capability(PCI_CAP_AGP) test below
* will fire, so we do no harm by already setting the flag.
*/
/* AGP only */
case PCI_PRODUCT_INTEL_82915GM_HB:
case PCI_PRODUCT_INTEL_82945GM_HB:
case PCI_PRODUCT_INTEL_82945GME_HB:
case PCI_PRODUCT_INTEL_82G965_HB:
case PCI_PRODUCT_INTEL_82Q965_HB:
case PCI_PRODUCT_INTEL_82GM965_HB:
case PCI_PRODUCT_INTEL_82G33_HB:
case PCI_PRODUCT_INTEL_82G35_HB:
has_agp = 1;
break;
/* AGP + RNG */
case PCI_PRODUCT_INTEL_82915G_HB:
case PCI_PRODUCT_INTEL_82945G_HB:
has_agp = 1;
/* FALLTHROUGH */
case PCI_PRODUCT_INTEL_82925X_HB:
case PCI_PRODUCT_INTEL_82955X_HB:
sc->sc_bt = pa->pa_memt;
if (bus_space_map(sc->sc_bt, I82802_IOBASE,
I82802_IOSIZE, 0, &sc->sc_bh))
break;
/* probe and init rng */
if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST) & I82802_RNG_HWST_PRESENT))
break;
/* enable RNG */
bus_space_write_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST,
bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);
/* see if we can read anything */
for (i = 1000; i-- &&
!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV); )
DELAY(10);
if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV))
break;
r = bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_DATA);
timeout_set(&sc->sc_rng_to, pchb_rnd, sc);
sc->sc_rng_i = 4;
pchb_rnd(sc);
break;
}
printf("\n");
break;
default:
printf("\n");
break;
}
#if NAGP > 0
/*
* If we haven't detected AGP yet (via a product ID),
* then check for AGP capability on the device.
*/
if (has_agp ||
pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
NULL, NULL) != 0) {
//.........这里部分代码省略.........
开发者ID:repos-holder,项目名称:openbsd-patches,代码行数:101,代码来源:pchb.c
示例14: elprobe
/*
* Probe routine.
*
* See if the card is there and at the right place.
* (XXX - cgd -- needs help)
*/
int
elprobe(device_t parent, cfdata_t match, void *aux)
{
struct isa_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
int iobase;
u_int8_t station_addr[ETHER_ADDR_LEN];
u_int8_t i;
int rval;
rval = 0;
if (ia->ia_nio < 1)
return (0);
if (ia->ia_nirq < 1)
return (0);
if (ISA_DIRECT_CONFIG(ia))
return (0);
iobase = ia->ia_io[0].ir_addr;
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
return (0);
if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
return (0);
/* First check the base. */
if (iobase < 0x200 || iobase > 0x3f0)
return 0;
/* Map i/o space. */
if (bus_space_map(iot, iobase, 16, 0, &ioh))
return 0;
/*
* Now attempt to grab the station address from the PROM and see if it
* contains the 3com vendor code.
*/
DPRINTF(("Probing 3c501 at 0x%x...\n", iobase));
/* Reset the board. */
DPRINTF(("Resetting board...\n"));
bus_space_write_1(iot, ioh, EL_AC, EL_AC_RESET);
delay(5);
bus_space_write_1(iot, ioh, EL_AC, 0);
/* Now read the address. */
DPRINTF(("Reading station address...\n"));
for (i = 0; i < ETHER_ADDR_LEN; i++) {
bus_space_write_1(iot, ioh, EL_GPBL, i);
station_addr[i] = bus_space_read_1(iot, ioh, EL_EAW);
}
DPRINTF(("Address is %s\n", ether_sprintf(station_addr)));
/*
* If the vendor code is ok, return a 1. We'll assume that whoever
* configured this system is right about the IRQ.
*/
if (station_addr[0] != 0x02 || station_addr[1] != 0x60 ||
station_addr[2] != 0x8c) {
DPRINTF(("Bad vendor code.\n"));
goto out;
}
DPRINTF(("Vendor code ok.\n"));
ia->ia_nio = 1;
ia->ia_io[0].ir_size = 16;
ia->ia_nirq = 1;
ia->ia_niomem = 0;
ia->ia_ndrq = 0;
rval = 1;
out:
bus_space_unmap(iot, ioh, 16);
return rval;
}
开发者ID:ycui1984,项目名称:netbsd-src,代码行数:87,代码来源:if_el.c
示例15: platform_mp_start_ap
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t src;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
panic("Couldn't map the system reset controller (SRC)\n");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/*
* Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
val | SCU_DIAG_DISABLE_MIGBIT);
/*
* Enable the SCU, then clean the cache on this core. After these two
* operations the cache tag ram in the SCU is coherent with the contents
* of the cache on this core. The other cores aren't running yet so
* their caches can't contain valid data yet, but we've initialized
* their SCU tag ram above, so they will be coherent from startup.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
cpu_idcache_wbinv_all();
/*
* For each AP core, set the entry point address and argument registers,
* and set the core-enable and core-reset bits in the control register.
*/
val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
for (i=1; i < mp_ncpus; i++) {
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
pmap_kextract((vm_offset_t)mpentry));
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0);
val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
}
bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
}
开发者ID:hbsciw,项目名称:freebsd,代码行数:63,代码来源:imx6_mp.c
示例16: elattach
/*
* Attach the interface to the kernel data structures. By the time this is
* called, we know that the card exists at the given I/O address. We still
* assume that the IRQ given is correct.
*/
void
elattach(device_t parent, device_t self, void *aux)
{
struct el_softc *sc = device_private(self);
struct isa_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
u_int8_t myaddr[ETHER_ADDR_LEN];
u_int8_t i;
sc->sc_dev = self;
printf("\n");
DPRINTF(("Attaching %s...\n", device_xname(sc->sc_dev)));
/* Map i/o space. */
if (bus_space_map(iot, ia->ia_io[0].ir_addr, 16, 0, &ioh)) {
aprint_error_dev(self, "can't map i/o space\n");
return;
}
sc->sc_iot = iot;
sc->sc_ioh = ioh;
/* Reset the board. */
bus_space_write_1(iot, ioh, EL_AC, EL_AC_RESET);
delay(5);
bus_space_write_1(iot, ioh, EL_AC, 0);
/* Now read the address. */
for (i = 0; i < ETHER_ADDR_LEN; i++) {
bus_space_write_1(iot, ioh, EL_GPBL, i);
myaddr[i] = bus_space_read_1(iot, ioh, EL_EAW);
}
/* Stop the board. */
elstop(sc);
/* Initialize ifnet structure. */
strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_start = elstart;
ifp->if_ioctl = elioctl;
ifp->if_watchdog = elwatchdog;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS;
IFQ_SET_READY(&ifp->if_snd);
/* Now we can attach the interface. */
DPRINTF(("Attaching interface...\n"));
if_attach(ifp);
ether_ifattach(ifp, myaddr);
/* Print out some information for the user. */
printf("%s: address %s\n", device_xname(self), ether_sprintf(myaddr));
sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
IST_EDGE, IPL_NET, elintr, sc);
DPRINTF(("Attaching to random...\n"));
rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
RND_TYPE_NET, RND_FLAG_DEFAULT);
DPRINTF(("elattach() finished.\n"));
}
开发者ID:ycui1984,项目名称:netbsd-src,代码行数:71,代码来源:if_el.c
示例17: imxpcibr_attach
void
imxpcibr_attach(struct device *parent, struct device *self, void *args)
{
struct armv7_attach_args *aa = args;
struct imxpcibr_softc *sc = (struct imxpcibr_softc *) self;
struct pcibus_attach_args pba;
sc->sc_iot = aa->aa_iot;
sc->sc_dma_tag = aa->aa_dmat;
if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
panic("imxpcibr_attach: bus_space_map failed!");
printf("\n");
return;
imxiomuxc_enable_pcie();
imxiomuxc_pcie_test_powerdown(0);
clk_enable(clk_get("pcie_axi"));
clk_enable(clk_get("pcie_ref_125m"));
imxiomuxc_pcie_test_powerdown(1);
HSET4(sc, PCIE_RC_COMMAND, PCIE_RC_COMMAND_IO_SPACE |
PCIE_RC_COMMAND_MEMORY_SPACE | PCIE_RC_COMMAND_BUS_MASTER);
HSET4(sc, PCIE_RC_REVID, PCI_CLASS_BRIDGE_PCI << 16);
snprintf(sc->sc_ioex_name, sizeof(sc->sc_ioex_name),
"%s pciio", sc->sc_dev.dv_xname);
sc->sc_ioex = extent_create(sc->sc_ioex_name, 0x00000000, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
snprintf(sc->sc_memex_name, sizeof(sc->sc_memex_name),
"%s pcimem", sc->sc_dev.dv_xname);
sc->sc_memex = extent_create(sc->sc_memex_name, 0x00000000, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
sc->sc_pc.pc_conf_v = sc;
sc->sc_pc.pc_attach_hook = imxpcibr_attach_hook;
sc->sc_pc.pc_bus_maxdevs = imxpcibr_bus_maxdevs;
sc->sc_pc.pc_make_tag = imxpcibr_make_tag;
sc->sc_pc.pc_decompose_tag = imxpcibr_decompose_tag;
sc->sc_pc.pc_conf_size = imxpcibr_conf_size;
sc->sc_pc.pc_conf_read = imxpcibr_conf_read;
sc->sc_pc.pc_conf_write = imxpcibr_conf_write;
sc->sc_pc.pc_intr_v = sc;
sc->sc_pc.pc_intr_map = imxpcibr_intr_map;
sc->sc_pc.pc_intr_string = imxpcibr_intr_string;
sc->sc_pc.pc_intr_establish = imxpcibr_intr_establish;
sc->sc_pc.pc_intr_disestablish = imxpcibr_intr_disestablish;
bzero(&pba, sizeof(pba));
pba.pba_dmat = sc->sc_dma_tag;
pba.pba_busname = "pci";
pba.pba_iot = sc->sc_iot;
pba.pba_memt = sc->sc_iot;
pb
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