本文整理汇总了C++中clk_prepare_enable函数的典型用法代码示例。如果您正苦于以下问题:C++ clk_prepare_enable函数的具体用法?C++ clk_prepare_enable怎么用?C++ clk_prepare_enable使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了clk_prepare_enable函数的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: exynos_cpufreq_cluster1_init
int __init exynos_cpufreq_cluster1_init(struct exynos_dvfs_info *info)
{
unsigned long rate;
struct device_node *pmic_node;
int ret, tmp;
set_volt_table_CA57();
mout_atlas_pll = clk_get(NULL, "mout_atlas_pll");
if (IS_ERR(mout_atlas_pll)) {
pr_err("failed get mout_atlas_pll clk\n");
goto err_mout_atlas_pll;
}
mout_atlas = clk_get(NULL, "mout_atlas");
if (IS_ERR(mout_atlas)) {
pr_err("failed get mout_atlas clk\n");
goto err_mout_atlas;
}
if (clk_set_parent(mout_atlas, mout_atlas_pll)) {
pr_err("Unable to set parent %s of clock %s.\n",
mout_atlas_pll->name, mout_atlas->name);
goto err_clk_set_parent_atlas;
}
mout_bus0_pll_atlas = clk_get(NULL, "mout_bus0_pll_atlas");
if (IS_ERR(mout_bus0_pll_atlas)) {
pr_err("failed get mout_bus0_pll_atlas clk\n");
goto err_mout_bus0_pll_atlas;
}
if (clk_prepare_enable(mout_atlas_pll) || clk_prepare_enable(mout_atlas)) {
pr_err("Unable to enable Atlas clocks \n");
goto err_clk_prepare_enable;
}
rate = clk_get_rate(mout_bus0_pll_atlas) / 1000;
info->mpll_freq_khz = rate;
info->pll_safe_idx = L17;
info->max_support_idx = max_support_idx_CA57;
info->min_support_idx = min_support_idx_CA57;
/* booting frequency is 1.7GHz */
info->boot_cpu_min_qos = exynos7420_freq_table_CA57[L8].frequency;
info->boot_cpu_max_qos = exynos7420_freq_table_CA57[L8].frequency;
info->bus_table = exynos7420_bus_table_CA57;
info->cpu_clk = mout_atlas_pll;
/* reboot limit frequency is 800MHz */
info->reboot_limit_freq = exynos7420_freq_table_CA57[L17].frequency;
info->volt_table = exynos7420_volt_table_CA57;
info->abb_table = NULL; //exynos7420_abb_table_CA57;
info->freq_table = exynos7420_freq_table_CA57;
info->set_freq = exynos7420_set_frequency_CA57;
info->need_apll_change = exynos7420_pms_change_CA57;
info->is_alive = exynos7420_is_alive_CA57;
info->set_ema = exynos7420_set_ema_CA57;
pmic_node = of_find_compatible_node(NULL, NULL, "samsung,s2mps15-pmic");
if (!pmic_node) {
pr_err("%s: faile to get pmic dt_node\n", __func__);
} else {
ret = of_property_read_u32(pmic_node, "smpl_warn_en", &en_smpl_warn);
if (ret)
pr_err("%s: faile to get Property of smpl_warn_en\n", __func__);
}
if (en_smpl_warn) {
info->check_smpl = exynos7420_check_smpl_CA57;
/* ATLAS_RATIO_SMPL */
tmp = __raw_readl(EXYNOS7420_ATLAS_SMPL_CTRL0);
tmp &= 0x7F;
tmp |= 0x44;
__raw_writel(tmp, EXYNOS7420_ATLAS_SMPL_CTRL0);
pr_info("%s SMPL_WARN ENABLE (DIV:%d) ", __func__, tmp&0x3F);
exynos_cpufreq_smpl_warn_register_notifier(&exynos7420_cpufreq_smpl_warn_notifier);
}
return 0;
err_clk_prepare_enable:
err_mout_bus0_pll_atlas:
err_clk_set_parent_atlas:
clk_put(mout_atlas);
err_mout_atlas:
clk_put(mout_atlas_pll);
err_mout_atlas_pll:
pr_debug("%s: failed initialization\n", __func__);
return -EINVAL;
}
开发者ID:ColinIanKing,项目名称:m576,代码行数:97,代码来源:exynos7420-atlas-cpufreq.c
示例2: sdhci_tegra_probe
static int sdhci_tegra_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
const struct sdhci_tegra_soc_data *soc_data;
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_tegra *tegra_host;
struct clk *clk;
int rc;
match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
if (!match)
return -EINVAL;
soc_data = match->data;
host = sdhci_pltfm_init(pdev, soc_data->pdata);
if (IS_ERR(host))
return PTR_ERR(host);
pltfm_host = sdhci_priv(host);
tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
if (!tegra_host) {
dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
rc = -ENOMEM;
goto err_alloc_tegra_host;
}
tegra_host->soc_data = soc_data;
pltfm_host->priv = tegra_host;
sdhci_tegra_parse_dt(&pdev->dev, tegra_host);
if (gpio_is_valid(tegra_host->power_gpio)) {
rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
if (rc) {
dev_err(mmc_dev(host->mmc),
"failed to allocate power gpio\n");
goto err_power_req;
}
gpio_direction_output(tegra_host->power_gpio, 1);
}
if (gpio_is_valid(tegra_host->cd_gpio)) {
rc = gpio_request(tegra_host->cd_gpio, "sdhci_cd");
if (rc) {
dev_err(mmc_dev(host->mmc),
"failed to allocate cd gpio\n");
goto err_cd_req;
}
gpio_direction_input(tegra_host->cd_gpio);
rc = request_irq(gpio_to_irq(tegra_host->cd_gpio),
carddetect_irq,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
mmc_hostname(host->mmc), host);
if (rc) {
dev_err(mmc_dev(host->mmc), "request irq error\n");
goto err_cd_irq_req;
}
}
if (gpio_is_valid(tegra_host->wp_gpio)) {
rc = gpio_request(tegra_host->wp_gpio, "sdhci_wp");
if (rc) {
dev_err(mmc_dev(host->mmc),
"failed to allocate wp gpio\n");
goto err_wp_req;
}
gpio_direction_input(tegra_host->wp_gpio);
}
clk = clk_get(mmc_dev(host->mmc), NULL);
if (IS_ERR(clk)) {
dev_err(mmc_dev(host->mmc), "clk err\n");
rc = PTR_ERR(clk);
goto err_clk_get;
}
clk_prepare_enable(clk);
pltfm_host->clk = clk;
if (tegra_host->is_8bit)
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
rc = sdhci_add_host(host);
if (rc)
goto err_add_host;
return 0;
err_add_host:
clk_disable_unprepare(pltfm_host->clk);
clk_put(pltfm_host->clk);
err_clk_get:
if (gpio_is_valid(tegra_host->wp_gpio))
gpio_free(tegra_host->wp_gpio);
err_wp_req:
if (gpio_is_valid(tegra_host->cd_gpio))
free_irq(gpio_to_irq(tegra_host->cd_gpio), host);
err_cd_irq_req:
//.........这里部分代码省略.........
开发者ID:AiWinters,项目名称:linux,代码行数:101,代码来源:sdhci-tegra.c
示例3: vpbe_initialize
/**
* vpbe_initialize() - Initialize the vpbe display controller
* @vpbe_dev - vpbe device ptr
*
* Master frame buffer device drivers calls this to initialize vpbe
* display controller. This will then registers v4l2 device and the sub
* devices and sets a current encoder sub device for display. v4l2 display
* device driver is the master and frame buffer display device driver is
* the slave. Frame buffer display driver checks the initialized during
* probe and exit if not initialized. Returns status.
*/
static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
{
struct encoder_config_info *enc_info;
struct amp_config_info *amp_info;
struct v4l2_subdev **enc_subdev;
struct osd_state *osd_device;
struct i2c_adapter *i2c_adap;
int num_encoders;
int ret = 0;
int err;
int i;
/*
* v4l2 abd FBDev frame buffer devices will get the vpbe_dev pointer
* from the platform device by iteration of platform drivers and
* matching with device name
*/
if (NULL == vpbe_dev || NULL == dev) {
printk(KERN_ERR "Null device pointers.\n");
return -ENODEV;
}
if (vpbe_dev->initialized)
return 0;
mutex_lock(&vpbe_dev->lock);
if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
/* We have dac clock available for platform */
vpbe_dev->dac_clk = clk_get(vpbe_dev->pdev, "vpss_dac");
if (IS_ERR(vpbe_dev->dac_clk)) {
ret = PTR_ERR(vpbe_dev->dac_clk);
goto fail_mutex_unlock;
}
if (clk_prepare_enable(vpbe_dev->dac_clk)) {
ret = -ENODEV;
goto fail_mutex_unlock;
}
}
/* first enable vpss clocks */
vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
/* First register a v4l2 device */
ret = v4l2_device_register(dev, &vpbe_dev->v4l2_dev);
if (ret) {
v4l2_err(dev->driver,
"Unable to register v4l2 device.\n");
goto fail_clk_put;
}
v4l2_info(&vpbe_dev->v4l2_dev, "vpbe v4l2 device registered\n");
err = bus_for_each_dev(&platform_bus_type, NULL, vpbe_dev,
platform_device_get);
if (err < 0) {
ret = err;
goto fail_dev_unregister;
}
vpbe_dev->venc = venc_sub_dev_init(&vpbe_dev->v4l2_dev,
vpbe_dev->cfg->venc.module_name);
/* register venc sub device */
if (vpbe_dev->venc == NULL) {
v4l2_err(&vpbe_dev->v4l2_dev,
"vpbe unable to init venc sub device\n");
ret = -ENODEV;
goto fail_dev_unregister;
}
/* initialize osd device */
osd_device = vpbe_dev->osd_device;
if (NULL != osd_device->ops.initialize) {
err = osd_device->ops.initialize(osd_device);
if (err) {
v4l2_err(&vpbe_dev->v4l2_dev,
"unable to initialize the OSD device");
err = -ENOMEM;
goto fail_dev_unregister;
}
}
/*
* Register any external encoders that are configured. At index 0 we
* store venc sd index.
*/
num_encoders = vpbe_dev->cfg->num_ext_encoders + 1;
vpbe_dev->encoders = kmalloc(
sizeof(struct v4l2_subdev *)*num_encoders,
GFP_KERNEL);
//.........这里部分代码省略.........
开发者ID:mikuhatsune001,项目名称:linux2.6.32,代码行数:101,代码来源:vpbe.c
示例4: s5p_mfc_power_off
int s5p_mfc_power_off(struct s5p_mfc_dev *dev)
{
#if defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
struct clk *clk_child = NULL;
struct clk *clk_parent = NULL;
#endif
#if defined(CONFIG_SOC_EXYNOS5430)
struct clk *clk_fout_mphy_pll = NULL;
#endif
#if defined(CONFIG_SOC_EXYNOS5433)
struct clk *clk_old_parent = NULL;
#endif
int ret;
MFC_TRACE_DEV("++ Power off\n");
#if defined(CONFIG_SOC_EXYNOS5422)
bts_initialize("pd-mfc", false);
#endif
#if defined(CONFIG_SOC_EXYNOS5430)
if (dev->id == 0) {
clk_fout_mphy_pll = clk_get(dev->device, "fout_mphy_pll");
if (IS_ERR(clk_fout_mphy_pll)) {
pr_err("failed to get %s clock\n", __clk_get_name(clk_fout_mphy_pll));
return PTR_ERR(clk_fout_mphy_pll);
}
clk_child = clk_get(dev->device, "mout_mphy_pll");
if (IS_ERR(clk_child)) {
clk_put(clk_fout_mphy_pll);
pr_err("failed to get %s clock\n", __clk_get_name(clk_child));
return PTR_ERR(clk_child);
}
clk_parent = clk_get(dev->device, "fin_pll");
if (IS_ERR(clk_parent)) {
clk_put(clk_child);
clk_put(clk_fout_mphy_pll);
pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));
return PTR_ERR(clk_parent);
}
/* 1. Set parent as OSC */
clk_set_parent(clk_child, clk_parent);
/* 2. Disable MPHY_PLL */
clk_disable_unprepare(clk_fout_mphy_pll);
}
#endif
#if defined(CONFIG_SOC_EXYNOS5433)
clk_old_parent = clk_get(dev->device, "aclk_mfc_400");
if (IS_ERR(clk_old_parent)) {
pr_err("failed to get %s clock\n", __clk_get_name(clk_old_parent));
return PTR_ERR(clk_old_parent);
}
clk_child = clk_get(dev->device, "mout_aclk_mfc_400_user");
if (IS_ERR(clk_child)) {
clk_put(clk_old_parent);
pr_err("failed to get %s clock\n", __clk_get_name(clk_child));
return PTR_ERR(clk_child);
}
clk_parent = clk_get(dev->device, "oscclk");
if (IS_ERR(clk_parent)) {
clk_put(clk_child);
clk_put(clk_old_parent);
pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));
return PTR_ERR(clk_parent);
}
/* before set mux register, all source clock have to enabled */
clk_prepare_enable(clk_parent);
if (clk_set_parent(clk_child, clk_parent)) {
pr_err("Unable to set parent %s of clock %s \n",
__clk_get_name(clk_parent), __clk_get_name(clk_child));
}
clk_disable_unprepare(clk_parent);
clk_disable_unprepare(clk_old_parent);
clk_put(clk_child);
clk_put(clk_parent);
clk_put(clk_old_parent);
/* expected mfc related ref clock value be set 0 */
#endif
atomic_set(&dev->pm.power, 0);
ret = pm_runtime_put_sync(dev->pm.device);
MFC_TRACE_DEV("-- Power off: ret(%d)\n", ret);
return ret;
}
开发者ID:bynarie,项目名称:android_kernel_samsung_gts210wifi,代码行数:90,代码来源:s5p_mfc_pm.c
示例5: img_spdif_out_probe
static int img_spdif_out_probe(struct platform_device *pdev)
{
struct img_spdif_out *spdif;
struct resource *res;
void __iomem *base;
int ret;
struct device *dev = &pdev->dev;
spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
if (!spdif)
return -ENOMEM;
platform_set_drvdata(pdev, spdif);
spdif->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
spdif->base = base;
spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
if (IS_ERR(spdif->rst)) {
if (PTR_ERR(spdif->rst) != -EPROBE_DEFER)
dev_err(&pdev->dev, "No top level reset found\n");
return PTR_ERR(spdif->rst);
}
spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
if (IS_ERR(spdif->clk_sys)) {
if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
dev_err(dev, "Failed to acquire clock 'sys'\n");
return PTR_ERR(spdif->clk_sys);
}
spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(spdif->clk_ref)) {
if (PTR_ERR(spdif->clk_ref) != -EPROBE_DEFER)
dev_err(dev, "Failed to acquire clock 'ref'\n");
return PTR_ERR(spdif->clk_ref);
}
ret = clk_prepare_enable(spdif->clk_sys);
if (ret)
return ret;
img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
IMG_SPDIF_OUT_CTL);
img_spdif_out_reset(spdif);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_spdif_out_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
spin_lock_init(&spdif->lock);
spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
spdif->dma_data.addr_width = 4;
spdif->dma_data.maxburst = 4;
ret = devm_snd_soc_register_component(&pdev->dev,
&img_spdif_out_component,
&img_spdif_out_dai, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
dev_dbg(&pdev->dev, "Probe successful\n");
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
img_spdif_out_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(spdif->clk_sys);
return ret;
}
开发者ID:mkrufky,项目名称:linux,代码行数:89,代码来源:img-spdif-out.c
示例6: emac_probe
/* Search EMAC board, allocate space and register it
*/
static int emac_probe(struct vmm_device *pdev,
const struct vmm_devtree_nodeid *devid)
{
struct device_node *np = pdev->node;
struct emac_board_info *db;
struct net_device *ndev;
int ret = 0;
const char *mac_addr;
virtual_addr_t reg_addr;
ndev = alloc_etherdev(sizeof(struct emac_board_info));
if (!ndev) {
dev_err(pdev, "%s: could not allocate device.\n", __func__);
return -ENOMEM;
}
strlcpy(ndev->name, pdev->name, sizeof(ndev->name));
SET_NETDEV_DEV(ndev, pdev);
db = netdev_priv(ndev);
memset(db, 0, sizeof(*db));
db->ndev = ndev;
db->pdev = pdev;
spin_lock_init(&db->lock);
if ((ret = vmm_devtree_request_regmap(np, ®_addr, 0,
"Sun4i EMAC"))) {
vmm_printf("%s: Failed to ioreamp\n", __func__);
return -ENOMEM;
}
db->membase = (void *) reg_addr;
/* fill in parameters for net-dev structure */
ndev->base_addr = (unsigned long)db->membase;
ret = vmm_devtree_irq_get(np, &ndev->irq, 0);
if (ret) {
vmm_printf("%s: No irq resource\n", __func__);
goto out;
}
db->clk = clk_get(pdev, NULL);
if (IS_ERR(db->clk))
goto out;
clk_prepare_enable(db->clk);
db->phy_node = vmm_devtree_parse_phandle(np, "phy", 0);
if (!db->phy_node) {
dev_err(pdev, "%s: no associated PHY\n", __func__);
ret = -ENODEV;
goto out;
}
/* Read MAC-address from DT */
mac_addr = of_get_mac_address(np);
if (mac_addr)
memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
/* Check if the MAC address is valid, if not get a random one */
if (!is_valid_ether_addr(ndev->dev_addr)) {
eth_hw_addr_random(ndev);
dev_info(pdev, "using random MAC address: ");
print_mac_address_fmt(ndev->dev_addr);
}
db->emacrx_completed_flag = 1;
emac_powerup(ndev);
emac_reset(db);
ether_setup(ndev);
ndev->netdev_ops = &emac_netdev_ops;
ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
ndev->ethtool_ops = &emac_ethtool_ops;
platform_set_drvdata(pdev, ndev);
/* Carrier starts down, phylib will bring it up */
netif_carrier_off(ndev);
ret = register_netdev(ndev);
if (ret) {
dev_err(pdev, "%s: Registering netdev failed!\n", __func__);
ret = -ENODEV;
goto out;
}
dev_info(pdev, "%s: at %p, IRQ %d MAC: ",
ndev->name, db->membase, ndev->irq);
print_mac_address_fmt(ndev->dev_addr);
return 0;
//.........这里部分代码省略.........
开发者ID:MaiDaftedar,项目名称:xvisor-next,代码行数:101,代码来源:sun4i-emac.c
示例7: set_high_bus_freq
/*
* Set the DDR to either 528MHz or 400MHz for iMX6qd
* or 400MHz for iMX6dl.
*/
static int set_high_bus_freq(int high_bus_freq)
{
struct clk *periph_clk_parent;
if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
cancel_delayed_work_sync(&low_bus_freq_handler);
if (busfreq_suspended)
return 0;
if (cpu_is_imx6q())
periph_clk_parent = pll2_bus;
else
periph_clk_parent = pll2_400;
if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
return 0;
if (high_bus_freq_mode)
return 0;
/* medium bus freq is only supported for MX6DQ */
if (med_bus_freq_mode && !high_bus_freq)
return 0;
if (low_bus_freq_mode || ultra_low_bus_freq_mode)
busfreq_notify(LOW_BUSFREQ_EXIT);
if (cpu_is_imx6())
clk_prepare_enable(pll3);
if (cpu_is_imx7d())
exit_lpm_imx7d();
else if (cpu_is_imx6sl())
exit_lpm_imx6sl();
else if (cpu_is_imx6sx() || cpu_is_imx6ul())
exit_lpm_imx6_up();
else {
if (high_bus_freq) {
clk_prepare_enable(pll2_400);
update_ddr_freq_imx_smp(ddr_normal_rate);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, pll3);
imx_clk_set_parent(periph_pre_clk, periph_clk_parent);
imx_clk_set_parent(periph_clk, periph_pre_clk);
if (cpu_is_imx6dl()) {
/* Set axi to pll3_pfd1_540m */
imx_clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m);
imx_clk_set_parent(axi_sel_clk, axi_alt_sel_clk);
}
clk_disable_unprepare(pll2_400);
} else {
update_ddr_freq_imx_smp(ddr_med_rate);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, pll3);
imx_clk_set_parent(periph_pre_clk, pll2_400);
imx_clk_set_parent(periph_clk, periph_pre_clk);
}
if (audio_bus_freq_mode)
clk_disable_unprepare(pll2_400);
}
high_bus_freq_mode = 1;
med_bus_freq_mode = 0;
low_bus_freq_mode = 0;
audio_bus_freq_mode = 0;
cur_bus_freq_mode = BUS_FREQ_HIGH;
if (cpu_is_imx6())
clk_disable_unprepare(pll3);
if (high_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
if (med_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
return 0;
}
开发者ID:FEDEVEL,项目名称:openrex-linux-3.14,代码行数:85,代码来源:busfreq-imx.c
示例8: dspi_probe
static int dspi_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct spi_master *master;
struct fsl_dspi *dspi;
struct resource *res;
int ret = 0, cs_num, bus_num;
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
if (!master)
return -ENOMEM;
dspi = spi_master_get_devdata(master);
dspi->pdev = pdev;
dspi->bitbang.master = master;
dspi->bitbang.chipselect = dspi_chipselect;
dspi->bitbang.setup_transfer = dspi_setup_transfer;
dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
dspi->bitbang.master->setup = dspi_setup;
dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_CPOL | SPI_CPHA;
master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
SPI_BPW_MASK(16);
ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
if (ret < 0) {
dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
goto out_master_put;
}
master->num_chipselect = cs_num;
ret = of_property_read_u32(np, "bus-num", &bus_num);
if (ret < 0) {
dev_err(&pdev->dev, "can't get bus-num\n");
goto out_master_put;
}
master->bus_num = bus_num;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dspi->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dspi->base)) {
ret = PTR_ERR(dspi->base);
goto out_master_put;
}
dspi->irq = platform_get_irq(pdev, 0);
if (dspi->irq < 0) {
dev_err(&pdev->dev, "can't get platform irq\n");
ret = dspi->irq;
goto out_master_put;
}
ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
pdev->name, dspi);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
goto out_master_put;
}
dspi->clk = devm_clk_get(&pdev->dev, "dspi");
if (IS_ERR(dspi->clk)) {
ret = PTR_ERR(dspi->clk);
dev_err(&pdev->dev, "unable to get clock\n");
goto out_master_put;
}
clk_prepare_enable(dspi->clk);
init_waitqueue_head(&dspi->waitq);
platform_set_drvdata(pdev, master);
ret = spi_bitbang_start(&dspi->bitbang);
if (ret != 0) {
dev_err(&pdev->dev, "Problem registering DSPI master\n");
goto out_clk_put;
}
pr_info(KERN_INFO "Freescale DSPI master initialized\n");
return ret;
out_clk_put:
clk_disable_unprepare(dspi->clk);
out_master_put:
spi_master_put(master);
return ret;
}
开发者ID:IDM350,项目名称:linux,代码行数:87,代码来源:spi-fsl-dspi.c
示例9: dw_mipi_dsi_phy_init
static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
{
int ret, testdin, vco, val;
vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
testdin = max_mbps_to_testdin(dsi->lane_mbps);
if (testdin < 0) {
DRM_DEV_ERROR(dsi->dev,
"failed to get testdin for %dmbps lane clock\n",
dsi->lane_mbps);
return testdin;
}
/* Start by clearing PHY state */
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
ret = clk_prepare_enable(dsi->phy_cfg_clk);
if (ret) {
DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
return ret;
}
dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
VCO_RANGE_CON_SEL(vco) |
VCO_IN_CAP_CON_LOW |
REF_BIAS_CUR_SEL);
dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
LPF_RESISTORS_20_KOHM);
dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
LOW_PROGRAM_EN);
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
HIGH_PROGRAM_EN);
dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
BIASEXTR_SEL(BIASEXTR_127_7));
dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
BANDGAP_SEL(BANDGAP_96_10));
dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
BIAS_BLOCK_ON | BANDGAP_ON);
dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
SETRD_MAX | TER_RESISTORS_ON);
dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
SETRD_MAX | POWER_MANAGE |
TER_RESISTORS_ON);
dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
dw_mipi_dsi_phy_write(dsi, 0x71,
THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
dw_mipi_dsi_phy_write(dsi, 0x72,
THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
dw_mipi_dsi_phy_write(dsi, 0x73,
THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));
dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
goto phy_init_end;
}
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & STOP_STATE_CLK_LANE, 1000,
PHY_STATUS_TIMEOUT_US);
if (ret < 0)
DRM_DEV_ERROR(dsi->dev,
"failed to wait for phy clk lane stop state\n");
phy_init_end:
clk_disable_unprepare(dsi->phy_cfg_clk);
return ret;
}
开发者ID:Lyude,项目名称:linux,代码行数:95,代码来源:dw-mipi-dsi.c
示例10: ingenic_uart_probe
static int ingenic_uart_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {};
struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
struct ingenic_uart_data *data;
const struct ingenic_uart_config *cdata;
const struct of_device_id *match;
int err, line;
match = of_match_device(of_match, &pdev->dev);
if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n");
return -ENODEV;
}
cdata = match->data;
if (!regs || !irq) {
dev_err(&pdev->dev, "no registers/irq defined\n");
return -EINVAL;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
spin_lock_init(&uart.port.lock);
uart.port.type = PORT_16550A;
uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
uart.port.iotype = UPIO_MEM;
uart.port.mapbase = regs->start;
uart.port.regshift = 2;
uart.port.serial_out = ingenic_uart_serial_out;
uart.port.serial_in = ingenic_uart_serial_in;
uart.port.irq = irq->start;
uart.port.dev = &pdev->dev;
uart.port.fifosize = cdata->fifosize;
uart.tx_loadsz = cdata->tx_loadsz;
uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
/* Check for a fixed line number */
line = of_alias_get_id(pdev->dev.of_node, "serial");
if (line >= 0)
uart.port.line = line;
uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
resource_size(regs));
if (!uart.port.membase)
return -ENOMEM;
data->clk_module = devm_clk_get(&pdev->dev, "module");
if (IS_ERR(data->clk_module)) {
err = PTR_ERR(data->clk_module);
if (err != -EPROBE_DEFER)
dev_err(&pdev->dev,
"unable to get module clock: %d\n", err);
return err;
}
data->clk_baud = devm_clk_get(&pdev->dev, "baud");
if (IS_ERR(data->clk_baud)) {
err = PTR_ERR(data->clk_baud);
if (err != -EPROBE_DEFER)
dev_err(&pdev->dev,
"unable to get baud clock: %d\n", err);
return err;
}
err = clk_prepare_enable(data->clk_module);
if (err) {
dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
goto out;
}
err = clk_prepare_enable(data->clk_baud);
if (err) {
dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
goto out_disable_moduleclk;
}
uart.port.uartclk = clk_get_rate(data->clk_baud);
data->line = serial8250_register_8250_port(&uart);
if (data->line < 0) {
err = data->line;
goto out_disable_baudclk;
}
platform_set_drvdata(pdev, data);
return 0;
out_disable_baudclk:
clk_disable_unprepare(data->clk_baud);
out_disable_moduleclk:
clk_disable_unprepare(data->clk_module);
out:
return err;
}
开发者ID:AlexShiLucky,项目名称:linux,代码行数:97,代码来源:8250_ingenic.c
示例11: spi_qup_probe
static int spi_qup_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct clk *iclk, *cclk;
struct spi_qup *controller;
struct resource *res;
struct device *dev;
void __iomem *base;
u32 max_freq, iomode, num_cs;
int ret, irq, size;
dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
cclk = devm_clk_get(dev, "core");
if (IS_ERR(cclk))
return PTR_ERR(cclk);
iclk = devm_clk_get(dev, "iface");
if (IS_ERR(iclk))
return PTR_ERR(iclk);
/* This is optional parameter */
if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
max_freq = SPI_MAX_RATE;
if (!max_freq || max_freq > SPI_MAX_RATE) {
dev_err(dev, "invalid clock frequency %d\n", max_freq);
return -ENXIO;
}
ret = clk_prepare_enable(cclk);
if (ret) {
dev_err(dev, "cannot enable core clock\n");
return ret;
}
ret = clk_prepare_enable(iclk);
if (ret) {
clk_disable_unprepare(cclk);
dev_err(dev, "cannot enable iface clock\n");
return ret;
}
master = spi_alloc_master(dev, sizeof(struct spi_qup));
if (!master) {
clk_disable_unprepare(cclk);
clk_disable_unprepare(iclk);
dev_err(dev, "cannot allocate master\n");
return -ENOMEM;
}
/* use num-cs unless not present or out of range */
if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
num_cs > SPI_NUM_CHIPSELECTS)
master->num_chipselect = SPI_NUM_CHIPSELECTS;
else
master->num_chipselect = num_cs;
master->bus_num = pdev->id;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
master->max_speed_hz = max_freq;
master->transfer_one = spi_qup_transfer_one;
master->dev.of_node = pdev->dev.of_node;
master->auto_runtime_pm = true;
master->dma_alignment = dma_get_cache_alignment();
master->max_dma_len = SPI_MAX_DMA_XFER;
platform_set_drvdata(pdev, master);
controller = spi_master_get_devdata(master);
controller->dev = dev;
controller->base = base;
controller->iclk = iclk;
controller->cclk = cclk;
controller->irq = irq;
ret = spi_qup_init_dma(master, res->start);
if (ret == -EPROBE_DEFER)
goto error;
else if (!ret)
master->can_dma = spi_qup_can_dma;
/* set v1 flag if device is version 1 */
if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
controller->qup_v1 = 1;
spin_lock_init(&controller->lock);
init_completion(&controller->done);
iomode = readl_relaxed(base + QUP_IO_M_MODES);
//.........这里部分代码省略.........
开发者ID:513855417,项目名称:linux,代码行数:101,代码来源:spi-qup.c
示例12: sdhci_pxav3_probe
static int sdhci_pxav3_probe(struct platform_device *pdev)
{
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
struct sdhci_host *host = NULL;
struct sdhci_pxa *pxa = NULL;
const struct of_device_id *match;
int ret;
struct clk *clk;
pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
if (!pxa)
return -ENOMEM;
host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
if (IS_ERR(host))
return PTR_ERR(host);
/* enable 1/8V DDR capable */
host->mmc->caps |= MMC_CAP_1_8V_DDR;
if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
ret = armada_38x_quirks(pdev, host);
if (ret < 0)
goto err_clk_get;
ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
if (ret < 0)
goto err_mbus_win;
}
pltfm_host = sdhci_priv(host);
pltfm_host->priv = pxa;
clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk)) {
dev_err(dev, "failed to get io clock\n");
ret = PTR_ERR(clk);
goto err_clk_get;
}
pltfm_host->clk = clk;
clk_prepare_enable(clk);
match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
if (match) {
ret = mmc_of_parse(host->mmc);
if (ret)
goto err_of_parse;
sdhci_get_of_property(pdev);
pdata = pxav3_get_mmc_pdata(dev);
} else if (pdata) {
/* on-chip device */
if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
host->mmc->caps |= MMC_CAP_NONREMOVABLE;
/* If slot design supports 8 bit data, indicate this to MMC. */
if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
if (pdata->quirks)
host->quirks |= pdata->quirks;
if (pdata->quirks2)
host->quirks2 |= pdata->quirks2;
if (pdata->host_caps)
host->mmc->caps |= pdata->host_caps;
if (pdata->host_caps2)
host->mmc->caps2 |= pdata->host_caps2;
if (pdata->pm_caps)
host->mmc->pm_caps |= pdata->pm_caps;
if (gpio_is_valid(pdata->ext_cd_gpio)) {
ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
0);
if (ret) {
dev_err(mmc_dev(host->mmc),
"failed to allocate card detect gpio\n");
goto err_cd_req;
}
}
}
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
pm_suspend_ignore_children(&pdev->dev, 1);
ret = sdhci_add_host(host);
if (ret) {
dev_err(&pdev->dev, "failed to add host\n");
goto err_add_host;
}
platform_set_drvdata(pdev, host);
if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
//.........这里部分代码省略.........
开发者ID:GAXUSXX,项目名称:G935FGaXusKernel2,代码行数:101,代码来源:sdhci-pxav3.c
示例13: msm8660_startup
static int msm8660_startup(struct snd_pcm_substream *substream)
{
int ret = 0;
pr_info("[%s:%s]\n", __MM_FILE__, __func__); //
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rx_osr_clk = clk_get(NULL, "i2s_spkr_osr_clk");
if (IS_ERR(rx_osr_clk)) {
pr_debug("Failed to get i2s_spkr_osr_clk\n");
return PTR_ERR(rx_osr_clk);
}
/* Master clock OSR 256 */
/* Initially set to Lowest sample rate Needed */
clk_set_rate(rx_osr_clk, 8000 * 256);
ret = clk_prepare_enable(rx_osr_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_spkr_osr_clk\n");
clk_put(rx_osr_clk);
return ret;
}
rx_bit_clk = clk_get(NULL, "i2s_spkr_bit_clk");
if (IS_ERR(rx_bit_clk)) {
pr_debug("Failed to get i2s_spkr_bit_clk\n");
clk_disable_unprepare(rx_osr_clk);
clk_put(rx_osr_clk);
return PTR_ERR(rx_bit_clk);
}
clk_set_rate(rx_bit_clk, 8);
ret = clk_prepare_enable(rx_bit_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_spkr_bit_clk\n");
clk_put(rx_bit_clk);
clk_disable_unprepare(rx_osr_clk);
clk_put(rx_osr_clk);
return ret;
}
timpani_poweramp_on();
msleep(30);
/* End of platform specific logic */
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
tx_osr_clk = clk_get(NULL, "i2s_mic_osr_clk");
if (IS_ERR(tx_osr_clk)) {
pr_debug("Failed to get i2s_mic_osr_clk\n");
return PTR_ERR(tx_osr_clk);
}
/* Master clock OSR 256 */
clk_set_rate(tx_osr_clk, 8000 * 256);
ret = clk_prepare_enable(tx_osr_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_mic_osr_clk\n");
clk_put(tx_osr_clk);
return ret;
}
tx_bit_clk = clk_get(NULL, "i2s_mic_bit_clk");
if (IS_ERR(tx_bit_clk)) {
pr_debug("Failed to get i2s_mic_bit_clk\n");
clk_disable_unprepare(tx_osr_clk);
clk_put(tx_osr_clk);
return PTR_ERR(tx_bit_clk);
}
clk_set_rate(tx_bit_clk, 8);
ret = clk_prepare_enable(tx_bit_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_mic_bit_clk\n");
clk_put(tx_bit_clk);
clk_disable_unprepare(tx_osr_clk);
clk_put(tx_osr_clk);
return ret;
}
msm_snddev_enable_dmic_power();
msleep(30);
}
return ret;
}
开发者ID:TeamRegular,项目名称:android_kernel_lge_iproj,代码行数:74,代码来源:msm8660.c
示例14: snddev_mi2s_open
static int snddev_mi2s_open(struct msm_snddev_info *dev_info)
{
int rc = 0;
union afe_port_config afe_config;
u8 channels;
u8 num_of_sd_lines = 0;
struct snddev_mi2s_drv_state *drv = &snddev_mi2s_drv;
struct snddev_mi2s_data *snddev_mi2s_data = dev_info->private_data;
if (!dev_info) {
pr_err("%s: msm_snddev_info is null\n", __func__);
return -EINVAL;
}
/* set up osr clk */
drv->tx_osrclk = clk_get_sys(NULL, "mi2s_osr_clk");
if (IS_ERR(drv->tx_osrclk))
pr_err("%s master clock Error\n", __func__);
rc = clk_set_rate(drv->tx_osrclk,
SNDDEV_MI2S_CLK_RATE(dev_info->sample_rate));
if (IS_ERR_VALUE(rc)) {
pr_err("ERROR setting osr clock\n");
return -ENODEV;
}
clk_prepare_enable(drv->tx_osrclk);
/* set up bit clk */
drv->tx_bitclk = clk_get_sys(NULL, "mi2s_bit_clk");
if (IS_ERR(drv->tx_bitclk))
pr_err("%s clock Error\n", __func__);
rc = clk_set_rate(drv->tx_bitclk, 8);
if (IS_ERR_VALUE(rc)) {
pr_err("ERROR setting bit clock\n");
clk_disable_unprepare(drv->tx_osrclk);
return -ENODEV;
}
clk_prepare_enable(drv->tx_bitclk);
afe_config.mi2s.bitwidth = 16;
if (snddev_mi2s_data->channel_mode == 1)
channels = AFE_MI2S_MONO;
else if (snddev_mi2s_data->channel_mode == 2)
channels = AFE_MI2S_STEREO;
else if (snddev_mi2s_data->channel_mode == 4)
channels = AFE_MI2S_4CHANNELS;
else if (snddev_mi2s_data->channel_mode == 6)
channels = AFE_MI2S_6CHANNELS;
else if (snddev_mi2s_data->channel_mode == 8)
channels = AFE_MI2S_8CHANNELS;
else {
pr_err("ERROR: Invalid MI2S channel mode\n");
goto error_invalid_data;
}
num_of_sd_lines = num_of_bits_set(snddev_mi2s_data->sd_lines);
switch (num_of_sd_lines) {
case 1:
switch (snddev_mi2s_data->sd_lines) {
case MI2S_SD0:
afe_config.mi2s.line = AFE_I2S_SD0;
break;
case MI2S_SD1:
afe_config.mi2s.line = AFE_I2S_SD1;
break;
case MI2S_SD2:
afe_config.mi2s.line = AFE_I2S_SD2;
break;
case MI2S_SD3:
afe_config.mi2s.line = AFE_I2S_SD3;
break;
default:
pr_err("%s: invalid SD line\n",
__func__);
goto error_invalid_data;
}
if (channels != AFE_MI2S_STEREO &&
channels != AFE_MI2S_MONO) {
pr_err("%s: for one SD line, channel "
"must be 1 or 2\n", __func__);
goto error_invalid_data;
}
afe_config.mi2s.channel = channels;
break;
case 2:
switch (snddev_mi2s_data->sd_lines) {
case MI2S_SD0 | MI2S_SD1:
afe_config.mi2s.line = AFE_I2S_QUAD01;
break;
case MI2S_SD2 | MI2S_SD3:
afe_config.mi2s.line = AFE_I2S_QUAD23;
break;
default:
pr_err("%s: invalid SD line\n",
__func__);
goto error_invalid_data;
}
//.........这里部分代码省略.........
开发者ID:1041574425,项目名称:Z5S_NX503A_130_kernel,代码行数:101,代码来源:snddev_mi2s.c
示例15: sdhci_pxav2_probe
static int sdhci_pxav2_probe(struct platform_device *pdev)
{
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
struct device *dev = &pdev->dev;
struct sdhci_host *host = NULL;
struct sdhci_pxa *pxa = NULL;
const struct of_device_id *match;
int ret;
struct clk *clk;
pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
if (!pxa)
return -ENOMEM;
host = sdhci_pltfm_init(pdev, NULL, 0);
if (IS_ERR(host)) {
kfree(pxa);
return PTR_ERR(host);
}
pltfm_host = sdhci_priv(host);
pltfm_host->priv = pxa;
clk = clk_get(dev, "PXA-SDHCLK");
if (IS_ERR(clk)) {
dev_err(dev, "failed to get io clock\n");
ret = PTR_ERR(clk);
goto err_clk_get;
}
pltfm_host->clk = clk;
clk_prepare_enable(clk);
host->quirks = SDHCI_QUIRK_BROKEN_ADMA
| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
if (match) {
pdata = pxav2_get_mmc_pdata(dev);
}
if (pdata) {
if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
/* on-chip device */
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
host->mmc->caps |= MMC_CAP_NONREMOVABLE;
}
/* If slot design supports 8 bit data, indicate this to MMC. */
if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
if (pdata->quirks)
host->quirks |= pdata->quirks;
if (pdata->host_caps)
host->mmc->caps |= pdata->host_caps;
if (pdata->pm_caps)
host->mmc->pm_caps |= pdata->pm_caps;
}
host->ops = &pxav2_sdhci_ops;
ret = sdhci_add_host(host);
if (ret) {
dev_err(&pdev->dev, "failed to add host\n");
goto err_add_host;
}
platform_set_drvdata(pdev, host);
return 0;
err_add_host:
clk_disable_unprepare(clk);
clk_put(clk);
err_clk_get:
sdhci_pltfm_free(pdev);
kfree(pxa);
return ret;
}
开发者ID:AkyZero,项目名称:wrapfs-latest,代码行数:80,代码来源:sdhci-pxav2.c
示例16: tegra_asoc_utils_set_rate
int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
int mclk)
{
int new_baseclock;
bool clk_change;
int err;
switch (srate) {
case 11025:
case 22050:
case 44100:
case 88200:
if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
new_baseclock = 56448000;
else
new_baseclock = 564480000;
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
new_baseclock = 73728000;
else
new_baseclock = 552960000;
break;
default:
return -EINVAL;
}
clk_change = ((new_baseclock != data->set_baseclock) ||
(mclk != data->set_mclk));
if (!clk_change)
return 0;
data->set_baseclock = 0;
data->
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