本文整理汇总了C++中clk_set_rate函数 的典型用法代码示例。如果您正苦于以下问题:C++ clk_set_rate函数的具体用法?C++ clk_set_rate怎么用?C++ clk_set_rate使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了clk_set_rate函数 的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: lcdc_on
static int lcdc_on(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
unsigned long panel_pixclock_freq = 0;
#ifndef CONFIG_MSM_BUS_SCALING
unsigned long pm_qos_rate;
#endif
mfd = platform_get_drvdata(pdev);
if (lcdc_pdata && lcdc_pdata->lcdc_get_clk)
panel_pixclock_freq = lcdc_pdata->lcdc_get_clk();
if (!panel_pixclock_freq)
panel_pixclock_freq = mfd->fbi->var.pixclock;
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(2);
#else
#ifdef CONFIG_MSM_NPA_SYSTEM_BUS
pm_qos_rate = MSM_AXI_FLOW_MDP_LCDC_WVGA_2BPP;
#else
if (panel_pixclock_freq > 65000000)
/* pm_qos_rate should be in Khz */
pm_qos_rate = panel_pixclock_freq / 1000 ;
else
pm_qos_rate = 65000;
#endif
if (mfd->ebi1_clk) {
clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000);
clk_enable(mfd->ebi1_clk);
}
#endif
mfd = platform_get_drvdata(pdev);
mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk,
mfd->fbi->var.pixclock);
if(firsttime)
{
firsttime=false;
}
else
ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock);
if (ret) {
pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n",
__func__, mfd->fbi->var.pixclock);
goto out;
}
clk_enable(pixel_mdp_clk);
clk_enable(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(1);
if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
ret = lcdc_pdata->lcdc_gpio_config(1);
ret = panel_next_on(pdev);
out:
return ret;
}
开发者ID:ChuckMichael, 项目名称:android-kernel-zte-v9a, 代码行数:62, 代码来源:lcdc.c
示例2: mali_clk_set_rate
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
{
unsigned long rate = 0;
mali_bool bis_vpll = MALI_TRUE;
#ifndef CONFIG_VPLL_USE_FOR_TVENC
bis_vpll = MALI_TRUE;
#endif
#if !MALI_DVFS_ENABLED
clk = mali_gpu_clk;
#endif
_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
if (mali_clk_get(bis_vpll) == MALI_FALSE)
return MALI_FALSE;
rate = (unsigned long)clk * (unsigned long)mhz;
MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz ));
if (bis_vpll)
{
clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ);
clk_set_parent(vpll_src_clock, ext_xtal_clock);
clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
clk_set_parent(mali_parent_clock, sclk_vpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
}
else
{
clk_set_parent(mali_parent_clock, mpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
}
if (clk_enable(mali_clock) < 0)
return MALI_FALSE;
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
rate, 0, 0, 0, 0);
#endif
clk_set_rate(mali_clock, rate);
rate = clk_get_rate(mali_clock);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
rate, 1, 0, 0, 0);
#endif
if (bis_vpll)
mali_gpu_clk = (int)(rate / mhz);
else
mali_gpu_clk = (int)((rate + 500000) / mhz);
GPU_MHZ = mhz;
MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk));
mali_clk_put(MALI_FALSE);
_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
return MALI_TRUE;
}
开发者ID:DerTeufel, 项目名称:SGS3-Sourcedrops, 代码行数:70, 代码来源:mali_platform.c
示例3: mali_clock_on
/*****************************************************************************
function name : mali_clock_on
description : clock on mali by calling clk
input vars : void
output vars : NA
return value : void
calls : clk_enable
called : mali_platform_powerup
history :
1.data : 04/03/2014
author : s00250033
modify : new
*****************************************************************************/
_mali_osk_errcode_t mali_clock_on(void)
{
int err;
int core_freq = 0;
int pclk_freq = 0;
#if 0
if( IS_ERR_OR_NULL(gpu_pll) )
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : gpu_pll is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(gpu_pll);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : gpu_pll enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
if( IS_ERR_OR_NULL(media_pll) )
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_pll is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(media_pll);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_pll enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
#endif
if( IS_ERR_OR_NULL(media_clk_g3d))
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_clk_g3d is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(media_clk_g3d);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_clk_g3d enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
err = of_property_read_u32(np, "pclk_freq",&pclk_freq);
if (err) {
MALI_DEBUG_PRINT(1, ("ERROR: get mali pclk freq failed!\n"));
return _MALI_OSK_ERR_FAULT;
}
if(0 != clk_set_rate(media_clk_g3d, (pclk_freq) * GPU_MHZ))
{
MALI_DEBUG_PRINT(1, ("ERROR: fail to set media_clk_g3d!\n"));
}
if( IS_ERR_OR_NULL(mali_clock))
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : mali_clock is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = of_property_read_u32(np, "mali_def_freq",&core_freq);
if (err) {
MALI_DEBUG_PRINT(1, ("ERROR: get mali default freq failed!\n"));
return _MALI_OSK_ERR_FAULT;
}
if(0 != clk_set_rate(mali_clock, core_freq * GPU_MHZ))
{
MALI_DEBUG_PRINT(1, ("ERROR: fail to set mali_clock!\n"));
}
err = clk_prepare_enable(mali_clock);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : mali_clock enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
//.........这里部分代码省略.........
开发者ID:mildrock, 项目名称:overlay_plane_display, 代码行数:101, 代码来源:mali_balong_pmm.c
示例4: bockw_init
static void __init bockw_init(void)
{
void __iomem *base;
struct clk *clk;
int i;
r8a7778_clock_init();
r8a7778_init_irq_extpin(1);
r8a7778_add_standard_devices();
platform_device_register_full(ðer_info);
platform_device_register_full(&vin0_info);
/* VIN1 has a pin conflict with Ether */
if (!IS_ENABLED(CONFIG_SH_ETH))
platform_device_register_full(&vin1_info);
platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0,
&iclink0_ml86v7667,
sizeof(iclink0_ml86v7667));
platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
&iclink1_ml86v7667,
sizeof(iclink1_ml86v7667));
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));
spi_register_board_info(spi_board_info,
ARRAY_SIZE(spi_board_info));
pinctrl_register_mappings(bockw_pinctrl_map,
ARRAY_SIZE(bockw_pinctrl_map));
r8a7778_pinmux_init();
platform_device_register_resndata(
&platform_bus, "sh_mmcif", -1,
mmc_resources, ARRAY_SIZE(mmc_resources),
&sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
platform_device_register_resndata(
&platform_bus, "rcar_usb_phy", -1,
usb_phy_resources,
ARRAY_SIZE(usb_phy_resources),
&usb_phy_platform_data,
sizeof(struct rcar_phy_platform_data));
regulator_register_fixed(0, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* for SMSC */
fpga = ioremap_nocache(FPGA, SZ_1M);
if (fpga) {
/*
* CAUTION
*
* IRQ0/1 is cascaded interrupt from FPGA.
* it should be cared in the future
* Now, it is assuming IRQ0 was used only from SMSC.
*/
u16 val = ioread16(fpga + IRQ0MR);
val &= ~(1 << 4); /* enable SMSC911x */
iowrite16(val, fpga + IRQ0MR);
platform_device_register_resndata(
&platform_bus, "smsc911x", -1,
smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
&smsc911x_data, sizeof(smsc911x_data));
}
/* for SDHI */
base = ioremap_nocache(PFC, 0x200);
if (base) {
/*
* FIXME
*
* SDHI CD/WP pin needs pull-up
*/
iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
iounmap(base);
platform_device_register_resndata(
&platform_bus, "sh_mobile_sdhi", 0,
sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
&sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
}
/* for Audio */
clk = clk_get(NULL, "audio_clk_b");
clk_set_rate(clk, 24576000);
clk_put(clk);
rsnd_codec_power(5, 1); /* enable ak4642 */
platform_device_register_simple(
"ak4554-adc-dac", 0, NULL, 0);
platform_device_register_simple(
"ak4554-adc-dac", 1, NULL, 0);
platform_device_register_resndata(
&platform_bus, "rcar_sound", -1,
rsnd_resources, ARRAY_SIZE(rsnd_resources),
//.........这里部分代码省略.........
开发者ID:7799, 项目名称:linux, 代码行数:101, 代码来源:board-bockw.c
示例5: sdhci_msm_probe
static int sdhci_msm_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_msm_host *msm_host;
struct resource *core_memres;
int ret;
u16 host_version, core_minor;
u32 core_version, caps;
u8 core_major;
host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
if (IS_ERR(host))
return PTR_ERR(host);
pltfm_host = sdhci_priv(host);
msm_host = sdhci_pltfm_priv(pltfm_host);
msm_host->mmc = host->mmc;
msm_host->pdev = pdev;
ret = mmc_of_parse(host->mmc);
if (ret)
goto pltfm_free;
sdhci_get_of_property(pdev);
/* Setup SDCC bus voter clock. */
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (!IS_ERR(msm_host->bus_clk)) {
/* Vote for max. clk rate for max. performance */
ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
if (ret)
goto pltfm_free;
ret = clk_prepare_enable(msm_host->bus_clk);
if (ret)
goto pltfm_free;
}
/* Setup main peripheral bus clock */
msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
if (IS_ERR(msm_host->pclk)) {
ret = PTR_ERR(msm_host->pclk);
dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
goto bus_clk_disable;
}
ret = clk_prepare_enable(msm_host->pclk);
if (ret)
goto bus_clk_disable;
/* Setup SDC MMC clock */
msm_host->clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(msm_host->clk)) {
ret = PTR_ERR(msm_host->clk);
dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
goto pclk_disable;
}
/* Vote for maximum clock rate for maximum performance */
ret = clk_set_rate(msm_host->clk, INT_MAX);
if (ret)
dev_warn(&pdev->dev, "core clock boost failed\n");
ret = clk_prepare_enable(msm_host->clk);
if (ret)
goto pclk_disable;
core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
if (IS_ERR(msm_host->core_mem)) {
dev_err(&pdev->dev, "Failed to remap registers\n");
ret = PTR_ERR(msm_host->core_mem);
goto clk_disable;
}
/* Reset the core and Enable SDHC mode */
writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
CORE_SW_RST, msm_host->core_mem + CORE_POWER);
/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
usleep_range(1000, 5000);
if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
dev_err(&pdev->dev, "Stuck in reset\n");
ret = -ETIMEDOUT;
goto clk_disable;
}
/* Set HC_MODE_EN bit in HC_MODE register */
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT));
core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
CORE_VERSION_MAJOR_SHIFT;
core_minor = core_version & CORE_VERSION_MINOR_MASK;
//.........这里部分代码省略.........
开发者ID:020gzh, 项目名称:linux, 代码行数:101, 代码来源:sdhci-msm.c
示例6: wand_set_spdif_clk_rate
static int wand_set_spdif_clk_rate(struct clk *clk, unsigned long rate) {
unsigned long rate_actual;
rate_actual = clk_round_rate(clk, rate);
clk_set_rate(clk, rate_actual);
return 0;
}
开发者ID:gitter-badger, 项目名称:ARRR, 代码行数:6, 代码来源:board-wand.c
示例7: mdss_edp_clk_enable
int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv)
{
int ret;
if (edp_drv->clk_on) {
pr_info("%s: edp clks are already ON\n", __func__);
return 0;
}
if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0)
pr_err("%s: link_clk - clk_set_rate failed\n",
__func__);
if (clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) < 0)
pr_err("%s: aux_clk - clk_set_rate failed\n",
__func__);
if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0)
pr_err("%s: pixel_clk - clk_set_rate failed\n",
__func__);
ret = clk_enable(edp_drv->aux_clk);
if (ret) {
pr_err("%s: Failed to enable aux clk\n", __func__);
goto c4;
}
ret = clk_enable(edp_drv->pixel_clk);
if (ret) {
pr_err("%s: Failed to enable pixel clk\n", __func__);
goto c3;
}
ret = clk_enable(edp_drv->ahb_clk);
if (ret) {
pr_err("%s: Failed to enable ahb clk\n", __func__);
goto c2;
}
ret = clk_enable(edp_drv->link_clk);
if (ret) {
pr_err("%s: Failed to enable link clk\n", __func__);
goto c1;
}
ret = clk_enable(edp_drv->mdp_core_clk);
if (ret) {
pr_err("%s: Failed to enable mdp_core_clk\n", __func__);
goto c0;
}
edp_drv->clk_on = 1;
return 0;
c0:
clk_disable(edp_drv->link_clk);
c1:
clk_disable(edp_drv->ahb_clk);
c2:
clk_disable(edp_drv->pixel_clk);
c3:
clk_disable(edp_drv->aux_clk);
c4:
return ret;
}
开发者ID:Qualcomm-msm, 项目名称:LG-G3_Kernel, 代码行数:62, 代码来源:msm_mdss_io_8974.c
示例8: tegra30_spdif_hw_params
static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = substream->pcm->card->dev;
struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
int ret, srate, spdifclock;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
dev_err(dev, "spdif capture is not supported\n");
return -EINVAL;
}
spdif->reg_ctrl &= ~TEGRA30_SPDIF_CTRL_BIT_MODE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_PACK_ENABLE;
spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT;
break;
default:
return -EINVAL;
}
srate = params_rate(params);
spdif->reg_ch_sta_a &= ~TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK;
spdif->reg_ch_sta_b &= ~TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK;
switch (srate) {
case 32000:
spdifclock = 4096000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000;
break;
case 44100:
spdifclock = 5644800;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100;
break;
case 48000:
spdifclock = 6144000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000;
break;
case 88200:
spdifclock = 11289600;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200;
break;
case 96000:
spdifclock = 12288000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000;
break;
case 176400:
spdifclock = 22579200;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400;
break;
case 192000:
spdifclock = 24576000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
if (ret) {
dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
return ret;
}
tegra30_spdif_enable_clocks(spdif);
tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_A,
spdif->reg_ch_sta_a);
tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_B,
spdif->reg_ch_sta_b);
tegra30_spdif_disable_clocks(spdif);
ret = tegra_hdmi_setup_audio_freq_source(srate, SPDIF);
if (ret) {
dev_err(dev, "Can't set HDMI audio freq source: %d\n", ret);
return ret;
}
//.........这里部分代码省略.........
开发者ID:ARMP, 项目名称:android_kernel_lge_x3, 代码行数:101, 代码来源:tegra30_spdif.c
示例9: s3cfb_clk_on
int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk)
{
struct clk *sclk = NULL;
struct clk *mout_fimd = NULL, *mout_mpll = NULL;
u32 rate = 0;
int ret;
sclk = clk_get(&pdev->dev, "sclk_fimd");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for fimd\n");
goto err_clk1;
}
#if defined(CONFIG_S5PV210_SCLKFIMD_USE_VPLL)
mout_mpll = clk_get(&pdev->dev, "mout_vpll");
#else
mout_mpll = clk_get(&pdev->dev, "mout_mpll");
#endif
if (IS_ERR(mout_mpll)) {
dev_err(&pdev->dev, "failed to get mout_mpll\n");
goto err_clk1;
}
mout_fimd = clk_get(&pdev->dev, "mout_fimd");
if (IS_ERR(mout_fimd)) {
dev_err(&pdev->dev,
"failed to get mout_fimd\n");
goto err_clk2;
}
clk_set_parent(sclk, mout_fimd);
clk_set_parent(mout_fimd, mout_mpll);
rate = clk_round_rate(sclk, 166750000);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
if (!rate)
rate = 166750000;
#if defined(CONFIG_MACH_S5PC110_P1)
#if defined(CONFIG_TARGET_PCLK_44_46)
rate = 45000000;
#elif defined(CONFIG_TARGET_PCLK_47_6)
//P1_ATT PCLK -> 47.6MHz
rate = 48000000;
#else
rate = 54000000;
#endif
#endif
clk_set_rate(sclk, rate);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
clk_put(mout_mpll);
clk_put(mout_fimd);
#if defined(CONFIG_MACH_S5PC110_P1)
{
struct clk * sclk_mdnie;
struct clk * sclk_mdnie_pwm;
sclk_mdnie = clk_get(&pdev->dev, "sclk_mdnie");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for mdnie\n");
}
else
{
#if defined(CONFIG_TARGET_PCLK_44_46)
clk_set_rate(sclk_mdnie, 45*1000000);
#elif defined(CONFIG_TARGET_PCLK_47_6)
//P1_ATT PCLK -> 47.6MHz
clk_set_rate(sclk_mdnie, 48*1000000);
#else
clk_set_rate(sclk_mdnie, 54*1000000);
#endif
clk_put(sclk_mdnie);
}
sclk_mdnie_pwm = clk_get(&pdev->dev, "sclk_mdnie_pwm");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for mdnie pwm\n");
}
else
{
clk_set_rate(sclk_mdnie_pwm, 2400*1000); // mdnie pwm need to 24Khz*100
clk_put(sclk_mdnie_pwm);
}
}
#endif
ret = s5pv210_pd_enable("fimd_pd");
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable fimd power domain\n");
goto err_clk2;
}
clk_enable(sclk);
*s3cfb_clk = sclk;
return 0;
//.........这里部分代码省略.........
开发者ID:Smackbox, 项目名称:linux-2.6-sgt, 代码行数:101, 代码来源:setup-fb.c
示例10: unifb_set_par
/*
* This routine actually sets the video mode. It's in here where we
* the hardware state info->par and fix which can be affected by the
* change in par. For this driver it doesn't do much.
*/
static int unifb_set_par(struct fb_info *info)
{
int hTotal, vTotal, hSyncStart, hSyncEnd, vSyncStart, vSyncEnd;
int format;
#ifdef CONFIG_PUV3_PM
struct clk *clk_vga;
u32 pixclk = 0;
int i;
for (i = 0; i <= 10; i++) {
if (info->var.xres == unifb_modes[i].xres
&& info->var.yres == unifb_modes[i].yres
&& info->var.upper_margin == unifb_modes[i].upper_margin
&& info->var.lower_margin == unifb_modes[i].lower_margin
&& info->var.left_margin == unifb_modes[i].left_margin
&& info->var.right_margin == unifb_modes[i].right_margin
&& info->var.hsync_len == unifb_modes[i].hsync_len
&& info->var.vsync_len == unifb_modes[i].vsync_len) {
pixclk = unifb_modes[i].pixclock;
break;
}
}
/* set clock rate */
clk_vga = clk_get(info->device, "VGA_CLK");
if (clk_vga == ERR_PTR(-ENOENT))
return -ENOENT;
if (pixclk != 0) {
if (clk_set_rate(clk_vga, pixclk)) { /* set clock failed */
info->fix = unifb_fix;
info->var = unifb_default;
if (clk_set_rate(clk_vga, unifb_default.pixclock))
return -EINVAL;
}
}
#endif
info->fix.line_length = get_line_length(info->var.xres_virtual,
info->var.bits_per_pixel);
hSyncStart = info->var.xres + info->var.right_margin;
hSyncEnd = hSyncStart + info->var.hsync_len;
hTotal = hSyncEnd + info->var.left_margin;
vSyncStart = info->var.yres + info->var.lower_margin;
vSyncEnd = vSyncStart + info->var.vsync_len;
vTotal = vSyncEnd + info->var.upper_margin;
switch (info->var.bits_per_pixel) {
case 8:
format = UDE_CFG_DST8;
break;
case 16:
format = UDE_CFG_DST16;
break;
case 24:
format = UDE_CFG_DST24;
break;
case 32:
format = UDE_CFG_DST32;
break;
default:
return -EINVAL;
}
writel(info->fix.smem_start, UDE_FSA);
writel(info->var.yres, UDE_LS);
writel(get_line_length(info->var.xres,
info->var.bits_per_pixel) >> 3, UDE_PS);
/* >> 3 for hardware required. */
writel((hTotal << 16) | (info->var.xres), UDE_HAT);
writel(((hTotal - 1) << 16) | (info->var.xres - 1), UDE_HBT);
writel(((hSyncEnd - 1) << 16) | (hSyncStart - 1), UDE_HST);
writel((vTotal << 16) | (info->var.yres), UDE_VAT);
writel(((vTotal - 1) << 16) | (info->var.yres - 1), UDE_VBT);
writel(((vSyncEnd - 1) << 16) | (vSyncStart - 1), UDE_VST);
writel(UDE_CFG_GDEN_ENABLE | UDE_CFG_TIMEUP_ENABLE
| format | 0xC0000001, UDE_CFG);
return 0;
}
开发者ID:119-org, 项目名称:hi3518-osdrv, 代码行数:88, 代码来源:fb-puv3.c
示例11: imx6q_clocks_init
//.........这里部分代码省略.........
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_PRE0] = imx_clk_gate2("pre0", "pre_axi", base + 0x80, 16);
clk[IMX6QDL_CLK_PRE1] = imx_clk_gate2("pre1", "pre_axi", base + 0x80, 18);
clk[IMX6QDL_CLK_PRE2] = imx_clk_gate2("pre2", "pre_axi", base + 0x80, 20);
clk[IMX6QDL_CLK_PRE3] = imx_clk_gate2("pre3", "pre_axi", base + 0x80, 22);
clk[IMX6QDL_CLK_PRG0_AXI] = imx_clk_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0);
clk[IMX6QDL_CLK_PRG1_AXI] = imx_clk_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1);
clk[IMX6QDL_CLK_PRG0_APB] = imx_clk_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0);
clk[IMX6QDL_CLK_PRG1_APB] = imx_clk_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1);
}
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
/*
* The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
* to clock gpt_ipg_per to ease the gpt driver code.
*/
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
clk_on_imx6dl()) {
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
if (clk_on_imx6dl())
clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.
* So choose pll2_pfd2_396m as enfc_sel's parent.
*/
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
}
/*
* Let's initially set up CLKO with OSC24M, since this configuration
* is widely used by imx6q board designs to clock audio codec.
*/
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
if (!ret)
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
if (ret)
pr_warn("failed to set up CLKO: %d\n", ret);
/* Audio-related clocks configuration */
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
/* All existing boards with PCIe use LVDS1 */
if (IS_ENABLED(CONFIG_PCI_IMX6))
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
/*
* Initialize the GPU clock muxes, so that the maximum specified clock
* rates for the respective SoC are not exceeded.
*/
if (clk_on_imx6dl()) {
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
} else if (clk_on_imx6q()) {
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
clk[IMX6QDL_CLK_PLL3_USB_OTG]);
}
imx_register_uart_clocks(uart_clks);
}
开发者ID:acton393, 项目名称:linux, 代码行数:101, 代码来源:clk-imx6q.c
示例12: exynos4415_fimc_is_cfg_clk
static int exynos4415_fimc_is_cfg_clk(struct platform_device *pdev)
{
struct clk *mout_isp_pll = NULL;
struct clk *mout_aclk_isp0_300 = NULL;
struct clk *dout_aclk_isp0_300 = NULL;
struct clk *mout_aclk_isp1_300 = NULL;
struct clk *dout_aclk_isp1_300 = NULL;
struct clk *aclk_isp0_300 = NULL;
struct clk *aclk_isp1_300 = NULL;
struct clk *dout_sclk_csis1 = NULL;
struct clk *dout_aclk_3aa1 = NULL;
struct clk *dout_aclk_lite_b = NULL;
struct clk *dout_pclk_isp0_a_150 = NULL;
struct clk *dout_pclk_isp0_b_150 = NULL;
struct clk *dout_pclk_isp0_b_75 = NULL;
struct clk *dout_pclk_isp1_150 = NULL;
struct clk *dout_pclk_isp1_75 = NULL;
struct clk *aclk_isp0_400 = NULL;
struct clk *aclk_isp0_400_pre = NULL;
struct clk *mout_mpll_user_top = NULL;
struct clk *sclk_pwm_isp = NULL;
struct clk *dout_spi0_isp = NULL;
struct clk *dout_spi1_isp = NULL;
struct clk *sclk_csis0 = NULL;
struct clk *sclk_csis1 = NULL;
struct clk *sclk_pxlasync_csis0_fimc = NULL;
struct clk *sclk_pxlasync_csis1_fimc = NULL;
struct clk *phyclk_rxbyte_clkhs0_s2a = NULL;
struct clk *mout_phyclk_rxbyte_clkhs0_s2a = NULL;
struct clk *phyclk_rxbyte_clkhs0_s4 = NULL;
struct clk *mout_phyclk_rxbyte_clkhs0_s4 = NULL;
/* front DPHY */
phyclk_rxbyte_clkhs0_s2a = clk_get(&pdev->dev, "phyclk_rxbyte_clkhs0_s2a");
if (IS_ERR(phyclk_rxbyte_clkhs0_s2a)) {
pr_err("%s : clk_get(phyclk_rxbyte_clkhs0_s2a) failed\n", __func__);
return PTR_ERR(phyclk_rxbyte_clkhs0_s2a);
}
mout_phyclk_rxbyte_clkhs0_s2a = clk_get(&pdev->dev, "mout_phyclk_rxbyte_clkhs0_s2a");
if (IS_ERR(mout_phyclk_rxbyte_clkhs0_s2a)) {
pr_err("%s : clk_get(mout_phyclk_rxbyte_clkhs0_s2a) failed\n", __func__);
return PTR_ERR(mout_phyclk_rxbyte_clkhs0_s2a);
}
clk_set_parent(mout_phyclk_rxbyte_clkhs0_s2a, phyclk_rxbyte_clkhs0_s2a);
clk_put(mout_phyclk_rxbyte_clkhs0_s2a);
clk_put(phyclk_rxbyte_clkhs0_s2a);
/* main DPHY */
phyclk_rxbyte_clkhs0_s4 = clk_get(&pdev->dev, "phyclk_rxbyte_clkhs0_s4");
if (IS_ERR(phyclk_rxbyte_clkhs0_s4)) {
pr_err("%s : clk_get(phyclk_rxbyte_clkhs0_s4) failed\n", __func__);
return PTR_ERR(phyclk_rxbyte_clkhs0_s4);
}
mout_phyclk_rxbyte_clkhs0_s4 = clk_get(&pdev->dev, "mout_phyclk_rxbyte_clkhs0_s4");
if (IS_ERR(mout_phyclk_rxbyte_clkhs0_s4)) {
pr_err("%s : clk_get(mout_phyclk_rxbyte_clkhs0_s4) failed\n", __func__);
return PTR_ERR(mout_phyclk_rxbyte_clkhs0_s4);
}
clk_set_parent(mout_phyclk_rxbyte_clkhs0_s4, phyclk_rxbyte_clkhs0_s4);
clk_put(mout_phyclk_rxbyte_clkhs0_s4);
clk_put(phyclk_rxbyte_clkhs0_s4);
mout_isp_pll = clk_get(&pdev->dev, "mout_isp_pll");
if (IS_ERR(mout_isp_pll)) {
pr_err("%s : clk_get(mout_isp_pll) failed\n", __func__);
return PTR_ERR(mout_isp_pll);
}
/* ack_isp0_300 */
mout_aclk_isp0_300 = clk_get(&pdev->dev, "mout_aclk_isp0_300");
if (IS_ERR(mout_aclk_isp0_300)) {
pr_err("%s : clk_get(mout_aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
return PTR_ERR(mout_aclk_isp0_300);
}
dout_aclk_isp0_300 = clk_get(&pdev->dev, "dout_aclk_isp0_300");
if (IS_ERR(dout_aclk_isp0_300)) {
pr_err("%s : clk_get(dout_aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp0_300);
return PTR_ERR(dout_aclk_isp0_300);
}
aclk_isp0_300 = clk_get(&pdev->dev, "aclk_isp0_300");
if (IS_ERR(aclk_isp0_300)) {
pr_err("%s : clk_get(aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp0_300);
clk_put(dout_aclk_isp0_300);
return PTR_ERR(aclk_isp0_300);
}
clk_set_parent(mout_aclk_isp0_300, mout_isp_pll);
clk_set_parent(aclk_isp0_300, dout_aclk_isp0_300);
clk_set_rate(dout_aclk_isp0_300, 300 * 1000000);
pr_info("dout_aclk_isp0_300 : %ld\n", clk_get_rate(dout_aclk_isp0_300));
clk_put(mout_aclk_isp0_300);
clk_put(dout_aclk_isp0_300);
clk_put(aclk_isp0_300);
//.........这里部分代码省略.........
开发者ID:Biktorgj, 项目名称:kminilte_kernel, 代码行数:101, 代码来源:setup-fimc-is.c
示例13: asoc_dmic_probe
static __devinit int asoc_dmic_probe(struct platform_device *pdev)
{
struct tegra_dmic *dmic;
struct resource *dmic_resource, *dmic_region;
int ret = 0;
char *dmic_clk_name;
long unsigned parent_rate;
dmic = devm_kzalloc(&pdev->dev, sizeof(struct tegra_dmic),
GFP_KERNEL);
if (!dmic)
return -ENOMEM;
platform_set_drvdata(pdev, dmic);
dmic->dev = &pdev->dev;
tegra_dmic_init_params(dmic);
mutex_init(&dmic->mutex);
switch (pdev->id) {
case TEGRA_DMIC_FRONT:
dmic_clk_name = "dmic0";
break;
case TEGRA_DMIC_BACK:
dmic_clk_name = "dmic1";
break;
default:
ret = -EINVAL;
goto err_free_dmic;
}
dmic->clk = clk_get(dmic->dev, dmic_clk_name);
if (IS_ERR(dmic->clk)) {
dev_err(dmic->dev, "cant get dmic clk\n");
ret = -ENODEV;
goto err_put_clk;
}
dmic->parent = clk_get(dmic->dev, "pll_a_out0");
if (IS_ERR(dmic->parent)) {
dev_err(dmic->dev, "cant get dmic parent\n");
ret = -ENODEV;
goto err_put_clk;
}
parent_rate = clk_get_rate(dmic->parent);
ret = clk_set_rate(dmic->clk, parent_rate);
if (ret < 0) {
dev_err(dmic->dev, "can't set dmic clk rate\n");
goto err_put_clk;
}
dmic_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!dmic_resource) {
dev_err(&pdev->dev, "No memory 0 resource\n");
ret = -ENODEV;
goto err_put_clk;
}
dmic_region = devm_request_mem_region(&pdev->dev,
dmic_resource->start, resource_size(dmic_resource),
pdev->name);
if (!dmic_region) {
dev_err(&pdev->dev, "Memory region 0 already claimed\n");
ret = -EBUSY;
goto err_put_clk;
}
dmic->io_base = devm_ioremap(&pdev->dev, dmic_resource->start,
resource_size(dmic_resource));
if (!dmic->io_base) {
dev_err(&pdev->dev, "ioremap 0 failed\n");
ret = -ENOMEM;
goto err_put_clk;
}
ret = snd_soc_register_dai(&pdev->dev, &tegra_dmic_dai[pdev->id]);
if (ret) {
dev_err(&pdev->dev, "dai registration failed\n");
ret = -EBUSY;
goto err_put_clk;
}
tegra_dmic_debug_add(dmic, pdev->id);
return 0;
err_put_clk:
if (dmic->parent)
clk_put(dmic->parent);
if (dmic->clk)
clk_put(dmic->clk);
err_free_dmic:
kfree(dmic);
return ret;
}
开发者ID:Packmaan7144, 项目名称:kernel_nvidia_s8515, 代码行数:97, 代码来源:tegra_dmic.c
示例14: exynos3_fimc_is_cfg_clk
int exynos3_fimc_is_cfg_clk(struct platform_device *pdev)
{
//int cfg;
/*parent*/
struct clk *sclk_mpll_pre_div = NULL;
struct clk *xusbxti = NULL;
/*mcuisp*/
struct clk *dout_aclk_400 = NULL;
struct clk *aclk_400_mcuisp = NULL;
struct clk *aclk_mcuisp_div0 = NULL;
struct clk *aclk_mcuisp_div1 = NULL;
/*ack_266*/
struct clk *mout_aclk_266_0 = NULL;
struct clk *dout_aclk_266 = NULL;
struct clk *aclk_266 = NULL;
struct clk *aclk_div0 = NULL;
struct clk *aclk_div1 = NULL;
struct clk *aclk_div2 = NULL;
/*function sclk*/
// struct clk *sclk_pwm_isp = NULL;
struct clk *sclk_uart_isp = NULL;
struct clk *sclk_spi1_isp = NULL;
struct clk *dout_sclk_spi1_isp = NULL;
struct clk *sclk_spi0_isp = NULL;
struct clk *dout_sclk_spi0_isp = NULL;
/*MCLK*/
struct clk *sclk_cam1 = NULL;
unsigned long mcu_isp_400;
unsigned long isp_266;
unsigned long isp_uart;
// unsigned long isp_pwm;
unsigned long isp_spi1;
unsigned long isp_spi0;
unsigned long isp_cam1;
pr_info(" %s\n",__func__);
/* initialize Clocks */
/*
* HACK: hard clock setting to preventing
* ISP init fail problem
*/
#if 0
writel(0x31, EXYNOS5_CLKDIV_ISP0);
writel(0x31, EXYNOS5_CLKDIV_ISP1);
writel(0x1, EXYNOS5_CLKDIV_ISP2);
cfg = readl(EXYNOS5_CLKDIV2_RATIO0);
cfg |= (0x1 < 6);
writel(0x1, EXYNOS5_CLKDIV2_RATIO0);
#endif
/* 0. Parent*/
sclk_mpll_pre_div = clk_get(&pdev->dev, "sclk_mpll_pre_div");
if (IS_ERR(sclk_mpll_pre_div)) {
pr_err("%s : clk_get(sclk_mpll_pre_div) failed\n", __func__);
return PTR_ERR(sclk_mpll_pre_div);
}
//clk_set_rate(sclk_mpll_pre_div, 800 * 1000000);
pr_info("sclk_mpll_pre_div : %ld\n", clk_get_rate(sclk_mpll_pre_div));
xusbxti = clk_get(&pdev->dev, "xusbxti");
if (IS_ERR(xusbxti)) {
pr_err("%s : clk_get(xxti) failed\n", __func__);
return PTR_ERR(xusbxti);
}
pr_info("xusbxti : %ld\n", clk_get_rate(xusbxti));
/* 1. MCUISP and DIV*/
/*
mout_mpll
sclk_mpll_mif
sclk_mpll_pre_div
dout_aclk_400
aclk_400_mcuisp
*/
dout_aclk_400 = clk_get(&pdev->dev, "dout_aclk_400");
if (IS_ERR(dout_aclk_400)) {
pr_err("%s : clk_get(dout_aclk_400) failed\n", __func__);
return PTR_ERR(dout_aclk_400);
}
clk_set_parent(dout_aclk_400, sclk_mpll_pre_div);
clk_set_rate(dout_aclk_400, 400 * 1000000);
aclk_400_mcuisp = clk_get(&pdev->dev, "aclk_400_mcuisp");
if (IS_ERR(aclk_400_mcuisp)) {
pr_err("%s : clk_get(aclk_400_mcuisp) failed\n", __func__);
//.........这里部分代码省略.........
开发者ID:Biktorgj, 项目名称:kminilte_kernel, 代码行数:101, 代码来源:setup-fimc-is.c
示例15: arch_setup
//.........这里部分代码省略.........
cn12_enabled = true;
#elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
gpio_request(GPIO_FN_SDHI1WP, NULL);
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
gpio_request(GPIO_FN_SDHI1D3, NULL);
gpio_request(GPIO_FN_SDHI1D2, NULL);
gpio_request(GPIO_FN_SDHI1D1, NULL);
gpio_request(GPIO_FN_SDHI1D0, NULL);
cn12_enabled = true;
#endif
if (cn12_enabled)
/* I/O buffer drive ability is high for CN12 */
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
IODRIVEA);
/* enable FSI */
gpio_request(GPIO_FN_FSIMCKB, NULL);
gpio_request(GPIO_FN_FSIIBSD, NULL);
gpio_request(GPIO_FN_FSIOBSD, NULL);
gpio_request(GPIO_FN_FSIIBBCK, NULL);
gpio_request(GPIO_FN_FSIIBLRCK, NULL);
gpio_request(GPIO_FN_FSIOBBCK, NULL);
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
if (!IS_ERR(clk)) {
/* 48kHz dummy clock was used to make sure 1/1 divide */
clk_set_rate(&sh7724_fsimckb_clk, 48000);
clk_set_parent(clk, &sh7724_fsimckb_clk);
clk_set_rate(clk, 48000);
clk_put(clk);
}
gpio_request(GPIO_PTU0, NULL);
gpio_direction_output(GPIO_PTU0, 0);
mdelay(20);
/* enable motion sensor */
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_direction_input(GPIO_FN_INTC_IRQ1);
/* set VPU clock to 166 MHz */
clk = clk_get(NULL, "vpu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 166000000));
clk_put(clk);
}
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
gpio_request(GPIO_PTU5, NULL);
开发者ID:VizXu, 项目名称:linux, 代码行数:67, 代码来源:setup.c
示例16: exynos5260_fimc_is_cfg_clk
/* Exynos5260 */
int exynos5260_fimc_is_cfg_clk(struct platform_device *pdev)
{
/* top */
struct clk *sclk_bustop_pll = NULL;
struct clk *mout_isp1_media_266 = NULL;
struct clk *sclk_memtop_pll = NULL;
/* isp */
struct clk *aclk_isp_266 = NULL;
struct clk *aclk_isp_266_user = NULL;
struct clk *pclk_isp_133 = NULL;
struct clk *pclk_isp_66 = NULL;
struct clk *sclk_mpwm_isp = NULL;
/* mcuctl */
struct clk *aclk_isp_400 = NULL;
struct clk *aclk_ca5_clkin = NULL;
struct clk *aclk_ca5_atclkin = NULL;
struct clk *pclk_ca5_pclkdbg = NULL;
#ifdef USE_UART_DEBUG
struct clk *sclk_uart_isp = NULL;
struct clk *sclk_uart_isp_div = NULL;
unsigned long isp_uart;
#endif
pr_info("%s\n", __func__);
/* 0. TOP */
sclk_memtop_pll = clk_get(&pdev->dev, "sclk_memtop_pll");
if (IS_ERR(sclk_memtop_pll))
return PTR_ERR(sclk_memtop_pll);
mout_isp1_media_266 = clk_get(&pdev->dev, "mout_isp1_media_266");
if (IS_ERR(mout_isp1_media_266)) {
clk_put(sclk_memtop_pll);
return PTR_ERR(mout_isp1_media_266);
}
aclk_isp_266 = clk_get(&pdev->dev, "aclk_isp_266");
if (IS_ERR(aclk_isp_266)) {
clk_put(sclk_memtop_pll);
clk_put(mout_isp1_media_266);
return PTR_ERR(aclk_isp_266);
}
clk_set_parent(mout_isp1_media_266, sclk_memtop_pll);
clk_set_parent(aclk_isp_266, mout_isp1_media_266);
clk_set_rate(aclk_isp_266, 300 * 1000000);
clk_put(sclk_memtop_pll);
clk_put(mout_isp1_media_266);
sclk_bustop_pll = clk_get(&pdev->dev, "sclk_bustop_pll");
if (IS_ERR(sclk_bustop_pll))
return PTR_ERR(sclk_bustop_pll);
aclk_isp_400 = clk_get(&pdev->dev, "aclk_isp_400");
if (IS_ERR(aclk_isp_400)) {
clk_put(sclk_bustop_pll);
return PTR_ERR(aclk_isp_400);
}
clk_set_parent(aclk_isp_400, sclk_bustop_pll);
clk_set_rate(aclk_isp_400, 400 * 1000000);
/* 1. MCUISP: aclk_isp_400 */
aclk_ca5_clkin = clk_get(&pdev->dev, "aclk_ca5_clkin");
if (IS_ERR(aclk_ca5_clkin)) {
clk_put(aclk_isp_400);
return PTR_ERR(aclk_ca5_clkin);
}
aclk_ca5_atclkin = clk_get(&pdev->dev, "aclk_ca5_atclkin");
if (IS_ERR(aclk_ca5_atclkin)) {
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
return PTR_ERR(aclk_ca5_atclkin);
}
pclk_ca5_pclkdbg = clk_get(&pdev->dev, "pclk_ca5_pclkdbg");
if (IS_ERR(pclk_ca5_pclkdbg)) {
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
clk_put(aclk_ca5_atclkin);
return PTR_ERR(pclk_ca5_pclkdbg);
}
clk_set_parent(aclk_ca5_clkin, aclk_isp_400);
clk_set_rate(aclk_ca5_atclkin, 200 * 1000000);
clk_set_rate(pclk_ca5_pclkdbg, 100 * 1000000);
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
clk_put(aclk_ca5_atclkin);
clk_put(pclk_ca5_pclkdbg);
/* 2. ACLK_ISP: aclk_isp_266 */
aclk_isp_266_user = clk_get(&pdev->dev, "aclk_isp_266_user");
if (IS_ERR(aclk_isp_266_user)) {
clk_put(aclk_isp_266);
//.........这里部分代码省略.........
开发者ID:Biktorgj, 项目名称:kminilte_kernel, 代码行数:101, 代码来源:setup-fimc-is.c
示例17: kbase_devfreq_target
六六分期app的软件客服如何联系?不知道吗?加qq群【895510560】即可!标题:六六分期
阅读:18128| 2023-10-27
今天小编告诉大家如何处理win10系统火狐flash插件总是崩溃的问题,可能很多用户都不知
阅读:9627| 2022-11-06
今天小编告诉大家如何对win10系统删除桌面回收站图标进行设置,可能很多用户都不知道
阅读:8159| 2022-11-06
今天小编告诉大家如何对win10系统电脑设置节能降温的设置方法,想必大家都遇到过需要
阅读:8537| 2022-11-06
我们在使用xp系统的过程中,经常需要对xp系统无线网络安装向导设置进行设置,可能很多
阅读:8438| 2022-11-06
今天小编告诉大家如何处理win7系统玩cf老是与主机连接不稳定的问题,可能很多用户都不
阅读:9356| 2022-11-06
电脑对日常生活的重要性小编就不多说了,可是一旦碰到win7系统设置cf烟雾头的问题,很
阅读:8405| 2022-11-06
我们在日常使用电脑的时候,有的小伙伴们可能在打开应用的时候会遇见提示应用程序无法
阅读:7840| 2022-11-06
今天小编告诉大家如何对win7系统打开vcf文件进行设置,可能很多用户都不知道怎么对win
阅读:8392| 2022-11-06
今天小编告诉大家如何对win10系统s4开启USB调试模式进行设置,可能很多用户都不知道怎
阅读:7385| 2022-11-06
请发表评论