本文整理汇总了C++中cpu_is_omap34xx函数的典型用法代码示例。如果您正苦于以下问题:C++ cpu_is_omap34xx函数的具体用法?C++ cpu_is_omap34xx怎么用?C++ cpu_is_omap34xx使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了cpu_is_omap34xx函数的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: omap2_i2c_add_bus
static inline int omap2_i2c_add_bus(int bus_id)
{
int l;
struct omap_hwmod *oh;
struct omap_device *od;
char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
struct omap_i2c_bus_platform_data *pdata;
omap2_i2c_mux_pins(bus_id);
l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
"String buffer overflow in I2C%d device setup\n", bus_id);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -EEXIST;
}
pdata = &i2c_pdata[bus_id - 1];
/*
* When waiting for completion of a i2c transfer, we need to
* set a wake up latency constraint for the MPU. This is to
* ensure quick enough wakeup from idle, when transfer
* completes.
* Only omap3 has support for constraints
*/
if (cpu_is_omap34xx())
pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
od = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data),
omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
return PTR_ERR(od);
}
开发者ID:007kumarraja,项目名称:rockchip-rk3188-mk908,代码行数:36,代码来源:i2c.c
示例2: omap_init_pmu
static int __init omap_init_pmu(void)
{
unsigned oh_num;
char **oh_names;
/* XXX Remove this check when the CTI driver is available */
if (cpu_is_omap443x()) {
pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
return 0;
}
if (of_have_populated_dt())
return 0;
/*
* To create an ARM-PMU device the following HWMODs
* are required for the various OMAP2+ devices.
*
* OMAP24xx: mpu
* OMAP3xxx: mpu, debugss
* OMAP4430: l3_main_3, l3_instr, debugss
* OMAP4460/70: mpu, debugss
*/
if (cpu_is_omap443x()) {
oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
oh_names = omap4430_pmu_oh_names;
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
oh_names = omap3_pmu_oh_names;
} else {
oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
oh_names = omap2_pmu_oh_names;
}
return omap2_init_pmu(oh_num, oh_names);
}
开发者ID:01org,项目名称:KVMGT-kernel,代码行数:36,代码来源:pmu.c
示例3: omap2_map_sram
/*
* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
*/
static void __init omap2_map_sram(void)
{
int cached = 1;
#ifdef CONFIG_OMAP4_ERRATA_I688
if (cpu_is_omap44xx()) {
omap_sram_start += PAGE_SIZE;
omap_sram_size -= SZ_16K;
}
#endif
if (cpu_is_omap34xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
* SDRAM controller disabled, and if it is marked cached,
* the ARM may attempt to write cache lines back to SDRAM
* which will cause the system to hang.
*/
cached = 0;
}
omap_map_sram(omap_sram_start, omap_sram_size,
omap_sram_skip, cached);
}
开发者ID:01org,项目名称:XenGT-Preview-kernel,代码行数:27,代码来源:sram.c
示例4: omap_dss_probe
/* PLATFORM DEVICE */
static int omap_dss_probe(struct platform_device *pdev)
{
struct omap_dss_board_info *pdata = pdev->dev.platform_data;
int skip_init = 0;
int r;
int i;
core.pdev = pdev;
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);
/*
* FIX-ME: Replace with correct clk node when clk
* framework is available
*/
if (!cpu_is_omap44xx()) {
r = dss_get_clocks();
if (r)
goto fail0;
}
dss_clk_enable_all_no_ctx();
core.ctx_id = dss_get_ctx_id();
DSSDBG("initial ctx id %u\n", core.ctx_id);
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
/* DISPC_CONTROL */
if (omap_readl(0x48050440) & 1) /* LCD enabled? */
skip_init = 1;
#endif
r = dss_init(skip_init);
if (r) {
DSSERR("Failed to initialize DSS\n");
goto fail0;
}
#ifdef CONFIG_OMAP2_DSS_RFBI
r = rfbi_init();
if (r) {
DSSERR("Failed to initialize rfbi\n");
goto fail0;
}
#endif
r = dpi_init();
if (r) {
DSSERR("Failed to initialize dpi\n");
goto fail0;
}
r = dispc_init();
if (r) {
DSSERR("Failed to initialize dispc\n");
goto fail0;
}
#ifdef CONFIG_OMAP2_DSS_VENC
r = venc_init(pdev);
if (r) {
DSSERR("Failed to initialize venc\n");
goto fail0;
}
#endif
if (cpu_is_omap34xx()) {
#ifdef CONFIG_OMAP2_DSS_SDI
r = sdi_init(skip_init);
if (r) {
DSSERR("Failed to initialize SDI\n");
goto fail0;
}
#endif
}
#ifdef CONFIG_OMAP2_DSS_DSI
printk(KERN_INFO "dsi_init calling");
r = dsi_init(pdev);
if (r) {
DSSERR("Failed to initialize DSI\n");
goto fail0;
}
if (cpu_is_omap44xx()) {
printk(KERN_INFO "dsi2_init calling");
r = dsi2_init(pdev);
if (r) {
DSSERR("Failed to initialize DSI2\n");
goto fail0;
}
}
#endif
#ifdef CONFIG_OMAP2_DSS_HDMI
r = hdmi_init(pdev, hdmi_code);
if (r) {
DSSERR("Failed to initialize hdmi\n");
goto fail0;
}
#endif
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
//.........这里部分代码省略.........
开发者ID:macroliu,项目名称:samsung_kernel_nowplus,代码行数:101,代码来源:core.c
示例5: omap_detect_sram
/*
* The amount of SRAM depends on the core type.
* Note that we cannot try to test for SRAM here because writes
* to secure SRAM will hang the system. Also the SRAM is not
* yet mapped at this point.
*/
static void __init omap_detect_sram(void)
{
if (cpu_class_is_omap2()) {
if (is_sram_locked()) {
if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PUB_PA;
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
omap_sram_size = 0x7000; /* 28K */
} else {
omap_sram_size = 0x8000; /* 32K */
}
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_START_PA;
omap_sram_size = OMAP4_SRAM_SIZE; /* 56KB */
omap_sram_size -= OMAP4_SRAM_HS_RESERVE;
omap_sram_start += OMAP4_SRAM_HS_RESERVE;
} else if (cpu_is_omap54xx()) {
omap_sram_start = OMAP4_SRAM_START_PA;
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_HS_RESERVE;
omap_sram_start += OMAP5_SRAM_HS_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
}
} else {
if (cpu_is_am33xx()) {
omap_sram_start = AM33XX_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_START_PA;
omap_sram_size = OMAP4_SRAM_SIZE; /* 56K */
omap_sram_size -= OMAP4_SRAM_GP_RESERVE;
omap_sram_start += OMAP4_SRAM_GP_RESERVE;
} else if (cpu_is_omap54xx()) {
omap_sram_start = OMAP4_SRAM_START_PA;
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_GP_RESERVE;
omap_sram_start += OMAP5_SRAM_GP_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
omap_sram_size = 0xa0000; /* 640K */
else if (cpu_is_omap243x())
omap_sram_size = 0x10000; /* 64K */
}
}
} else {
omap_sram_start = OMAP1_SRAM_PA;
if (cpu_is_omap7xx())
omap_sram_size = 0x32000; /* 200K */
else if (cpu_is_omap15xx())
omap_sram_size = 0x30000; /* 192K */
else if (cpu_is_omap1610() || cpu_is_omap1611() ||
cpu_is_omap1621() || cpu_is_omap1710())
omap_sram_size = 0x4000; /* 16K */
else {
pr_err("Could not detect SRAM size\n");
omap_sram_size = 0x4000;
}
}
}
开发者ID:SciAps,项目名称:android-kernel,代码行数:73,代码来源:sram.c
示例6: omap_i2c_init
//.........这里部分代码省略.........
* 19.2 2 1
*/
if (fclk_rate > 12000000)
psc = fclk_rate / 12000000;
}
if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
/*
* HSI2C controller internal clk rate should be 19.2 Mhz for
* HS and for all modes on 2430. On 34xx we can use lower rate
* to get longer filter period for better noise suppression.
* The filter is iclk (fclk for HS) period.
*/
if (dev->speed > 400 || cpu_is_omap2430())
internal_clk = 19200;
else if (dev->speed > 100)
internal_clk = 9600;
else
internal_clk = 4000;
fclk = clk_get(dev->dev, "fck");
fclk_rate = clk_get_rate(fclk) / 1000;
clk_put(fclk);
/* Compute prescaler divisor */
psc = fclk_rate / internal_clk;
psc = psc - 1;
/* If configured for High Speed */
if (dev->speed > 400) {
unsigned long scl;
/* For first phase of HS mode */
scl = internal_clk / 400;
fsscll = scl - (scl / 3) - 7;
fssclh = (scl / 3) - 5;
/* For second phase of HS mode */
scl = fclk_rate / dev->speed;
hsscll = scl - (scl / 3) - 7;
hssclh = (scl / 3) - 5;
} else if (dev->speed > 100) {
unsigned long scl;
/* Fast mode */
scl = internal_clk / dev->speed;
fsscll = scl - (scl / 3) - 7;
fssclh = (scl / 3) - 5;
} else {
/* Standard mode */
fsscll = internal_clk / (dev->speed * 2) - 7;
fssclh = internal_clk / (dev->speed * 2) - 5;
}
scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
} else {
/* Program desired operating rate */
fclk_rate /= (psc + 1) * 1000;
if (psc > 2)
psc = 2;
scll = fclk_rate / (dev->speed * 2) - 7 + psc;
sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
}
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
/* SCL low and high time values */
omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
if (dev->fifo_size) {
/* Note: setup required fifo size - 1. RTRSH and XTRSH */
buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
(dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
}
/* Take the I2C module out of reset: */
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
dev->errata = 0;
if (cpu_is_omap2430() || cpu_is_omap34xx())
dev->errata |= I2C_OMAP_ERRATA_I207;
/* Enable interrupts */
dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
if (cpu_is_omap34xx()) {
dev->pscstate = psc;
dev->scllstate = scll;
dev->sclhstate = sclh;
dev->bufstate = buf;
}
return 0;
}
开发者ID:1DeMaCr,项目名称:android_hd_kernel_samsung_codina,代码行数:101,代码来源:i2c-omap.c
示例7: omap_prcm_restart
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_restart(char mode, const char *cmd)
{
s16 prcm_offs = 0;
if (cpu_is_omap24xx()) {
omap2xxx_clk_prepare_for_reboot();
prcm_offs = WKUP_MOD;
} else if (cpu_is_omap34xx()) {
prcm_offs = OMAP3430_GR_MOD;
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
} else if (cpu_is_omap44xx()) {
omap4_prminst_global_warm_sw_reset(); /* never returns */
} else if (cpu_is_omap54xx()) {
/*
* Erratum i744:
* Seems that the HSDIVIDER ratio is corrupted after WARM reset
* H/w team WA is as follows:
* when warm reset is generated, PMIC must be set to generate
* cold reset OR, in the specific case of TWL6035,
* "TWL6035 device, it is recommended to connect the OMAP
* sys_nreswarm pin to the reset_in pin."
* Instead, Since many of the boards are not accessible for
* modification OR may use other PMICs which may not be capable,
* lets do cold reset in the first place.
*
* NOTE: this does not save us from other h/w Warm reset sources
* such as WDT/Thermal events.
*/
if (OMAP5430_REV_ES1_0 == omap_rev() ||
OMAP5432_REV_ES1_0 == omap_rev())
omap4_pm_cold_reset("Cold reset as WA reboot for i744");
else
omap4_prminst_global_warm_sw_reset();
/* Neither should return.. if they did, bug */
BUG();
} else {
WARN_ON(1);
}
/*
* As per Errata i520, in some cases, user will not be able to
* access DDR memory after warm-reset.
* This situation occurs while the warm-reset happens during a read
* access to DDR memory. In that particular condition, DDR memory
* does not respond to a corrupted read command due to the warm
* reset occurrence but SDRC is waiting for read completion.
* SDRC is not sensitive to the warm reset, but the interconnect is
* reset on the fly, thus causing a misalignment between SDRC logic,
* interconnect logic and DDR memory state.
* WORKAROUND:
* Steps to perform before a Warm reset is trigged:
* 1. enable self-refresh on idle request
* 2. put SDRC in idle
* 3. wait until SDRC goes to idle
* 4. generate SW reset (Global SW reset)
*
* Steps to be performed after warm reset occurs (in bootloader):
* if HW warm reset is the source, apply below steps before any
* accesses to SDRAM:
* 1. Reset SMS and SDRC and wait till reset is complete
* 2. Re-initialize SMS, SDRC and memory
*
* NOTE: Above work around is required only if arch reset is implemented
* using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
* the WA since it resets SDRC as well as part of cold reset.
*/
/* XXX should be moved to some OMAP2/3 specific code */
omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
OMAP2_RM_RSTCTRL);
omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
}
开发者ID:SciAps,项目名称:android-kernel,代码行数:74,代码来源:prcm.c
示例8: usbhs_init
void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
{
struct omap_hwmod *oh[4];
struct omap_device *od;
int bus_id = -1;
int i;
for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
usbhs_data.port_mode[i] = pdata->port_mode[i];
ohci_data.port_mode[i] = pdata->port_mode[i];
ehci_data.port_mode[i] = pdata->port_mode[i];
ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
ehci_data.regulator[i] = pdata->regulator[i];
ehci_data.transceiver_clk[i] = pdata->transceiver_clk[i];
}
ehci_data.phy_reset = pdata->phy_reset;
ohci_data.es2_compatibility = pdata->es2_compatibility;
usbhs_data.ehci_data = &ehci_data;
usbhs_data.ohci_data = &ohci_data;
oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
if (!oh[0]) {
pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
return;
}
oh[1] = omap_hwmod_lookup(USBHS_OHCI_HWMODNAME);
if (!oh[1]) {
pr_err("Could not look up %s\n", USBHS_OHCI_HWMODNAME);
return;
}
oh[2] = omap_hwmod_lookup(USBHS_EHCI_HWMODNAME);
if (!oh[2]) {
pr_err("Could not look up %s\n", USBHS_EHCI_HWMODNAME);
return;
}
oh[3] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
if (!oh[3]) {
pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
return;
}
if (cpu_is_omap34xx()) {
setup_ehci_io_mux(pdata->port_mode);
setup_ohci_io_mux(pdata->port_mode);
} else if (cpu_is_omap44xx()) {
oh[2]->mux = setup_4430ehci_io_mux(pdata->port_mode);
if (oh[2]->mux)
omap_hwmod_mux(oh[2]->mux, _HWMOD_STATE_ENABLED);
oh[1]->mux = setup_4430ohci_io_mux(pdata->port_mode);
if (oh[1]->mux)
omap_hwmod_mux(oh[1]->mux, _HWMOD_STATE_ENABLED);
}
od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 4,
(void *)&usbhs_data, sizeof(usbhs_data),
omap_uhhtll_latency,
ARRAY_SIZE(omap_uhhtll_latency), false);
if (IS_ERR(od)) {
pr_err("Could not build hwmod devices %s, %s\n",
USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
return;
}
usbhs_wake = kmalloc(sizeof(*usbhs_wake), GFP_KERNEL);
if (!usbhs_wake) {
pr_err("Could not allocate usbhs_wake\n");
return;
}
INIT_WORK(&usbhs_wake->wakeup_work, usbhs_resume_work);
usbhs_wake->oh_ehci = oh[2];
usbhs_wake->oh_ohci = oh[1];
usbhs_wake->dev = &od->pdev.dev;
}
开发者ID:andi34,项目名称:Dhollmen_Kernel,代码行数:78,代码来源:usb-host.c
示例9: dss_init
int dss_init(struct platform_device *pdev)
{
int r = 0, dss_irq;
u32 rev;
struct resource *dss_mem;
bool skip_init = false;
dss.pdata = pdev->dev.platform_data;
dss.pdev = pdev;
if (cpu_is_omap44xx())
dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
else
dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!dss_mem) {
WARN_ON(1);
r = -ENODEV;
goto fail0;
}
dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
if (!dss.base) {
DSSERR("can't ioremap DSS\n");
r = -ENOMEM;
goto fail0;
}
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M | DSS_CLK_96M);
dss_mainclk_enable();
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
/* DISPC_CONTROL */
if (omap_readl(0x48050440) & 1) /* LCD enabled? */
skip_init = true;
#endif
if (!skip_init) {
/* disable LCD and DIGIT output. This seems to fix the synclost
* problem that we get, if the bootloader starts the DSS and
* the kernel resets it */
omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
/* We need to wait here a bit, otherwise we sometimes start to
* get synclost errors, and after that only power cycle will
* restore DSS functionality. I have no idea why this happens.
* And we have to wait _before_ resetting the DSS, but after
* enabling clocks.
*/
msleep(50);
}
/* autoidle */
REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
/* Select DPLL */
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
#ifdef CONFIG_OMAP2_DSS_VENC
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
#endif
if (!cpu_is_omap44xx())
r = request_irq(INT_24XX_DSS_IRQ,
cpu_is_omap24xx()
? dss_irq_handler_omap2
: dss_irq_handler_omap3,
0, "OMAP DSS", NULL);
else {
dss_irq = platform_get_irq(pdev, 0);
r = request_irq(dss_irq,
dss_irq_handler_omap2,
0, "OMAP DSS", NULL);
}
if (r < 0) {
DSSERR("omap2 dss: request_irq failed\n");
goto fail1;
}
if (cpu_is_omap34xx()) {
dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
if (IS_ERR(dss.dpll4_m4_ck)) {
DSSERR("Failed to get dpll4_m4_ck\n");
r = PTR_ERR(dss.dpll4_m4_ck);
goto fail2;
}
}
dss.dsi1_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
dss.dsi2_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
dss.lcd1_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
dss.lcd2_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
dss_save_context();
rev = dss_read_reg(DSS_REVISION);
printk(KERN_INFO "OMAP DSS rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
//.........这里部分代码省略.........
开发者ID:matianfu,项目名称:kunlun-kernel,代码行数:101,代码来源:dss.c
示例10: omap2_onenand_probe
//.........这里部分代码省略.........
gpio_direction_input(c->gpio_irq);
if ((r = request_irq(gpio_to_irq(c->gpio_irq),
omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
pdev->dev.driver->name, c)) < 0)
goto err_release_gpio;
}
if (c->dma_channel >= 0) {
r = omap_request_dma(0, pdev->dev.driver->name,
omap2_onenand_dma_cb, (void *) c,
&c->dma_channel);
if (r == 0) {
omap_set_dma_write_mode(c->dma_channel,
OMAP_DMA_WRITE_NON_POSTED);
omap_set_dma_src_data_pack(c->dma_channel, 1);
omap_set_dma_src_burst_mode(c->dma_channel,
OMAP_DMA_DATA_BURST_8);
omap_set_dma_dest_data_pack(c->dma_channel, 1);
omap_set_dma_dest_burst_mode(c->dma_channel,
OMAP_DMA_DATA_BURST_8);
} else {
dev_info(&pdev->dev,
"failed to allocate DMA for OneNAND, "
"using PIO instead\n");
c->dma_channel = -1;
}
}
dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
"base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
c->onenand.base, c->freq);
c->pdev = pdev;
c->mtd.name = dev_name(&pdev->dev);
c->mtd.priv = &c->onenand;
c->mtd.owner = THIS_MODULE;
c->mtd.dev.parent = &pdev->dev;
this = &c->onenand;
if (c->dma_channel >= 0) {
this->wait = omap2_onenand_wait;
if (cpu_is_omap34xx()) {
this->read_bufferram = omap3_onenand_read_bufferram;
this->write_bufferram = omap3_onenand_write_bufferram;
} else {
this->read_bufferram = omap2_onenand_read_bufferram;
this->write_bufferram = omap2_onenand_write_bufferram;
}
}
if (pdata->regulator_can_sleep) {
c->regulator = regulator_get(&pdev->dev, "vonenand");
if (IS_ERR(c->regulator)) {
dev_err(&pdev->dev, "Failed to get regulator\n");
r = PTR_ERR(c->regulator);
goto err_release_dma;
}
c->onenand.enable = omap2_onenand_enable;
c->onenand.disable = omap2_onenand_disable;
}
if (pdata->skip_initial_unlocking)
this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
if ((r = onenand_scan(&c->mtd, 1)) < 0)
goto err_release_regulator;
r = mtd_device_parse_register(&c->mtd, NULL, NULL,
pdata ? pdata->parts : NULL,
pdata ? pdata->nr_parts : 0);
if (r)
goto err_release_onenand;
platform_set_drvdata(pdev, c);
return 0;
err_release_onenand:
onenand_release(&c->mtd);
err_release_regulator:
regulator_put(c->regulator);
err_release_dma:
if (c->dma_channel != -1)
omap_free_dma(c->dma_channel);
if (c->gpio_irq)
free_irq(gpio_to_irq(c->gpio_irq), c);
err_release_gpio:
if (c->gpio_irq)
gpio_free(c->gpio_irq);
err_iounmap:
iounmap(c->onenand.base);
err_release_mem_region:
release_mem_region(c->phys_base, c->mem_size);
err_kfree:
kfree(c);
return r;
}
开发者ID:AllenDou,项目名称:linux,代码行数:101,代码来源:omap2.c
示例11: cpu_is_omap34xx
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include <linux/usb/musb.h>
#include <mach/hardware.h>
#include <mach/pm.h>
#include <mach/mux.h>
#include <mach/usb.h>
#ifdef CONFIG_USB_MUSB_SOC
static struct resource musb_resources[] = {
[0] = {
.start = cpu_is_omap34xx()
? OMAP34XX_HSUSB_OTG_BASE
: OMAP243X_HS_BASE,
.end = cpu_is_omap34xx()
? OMAP34XX_HSUSB_OTG_BASE + SZ_8K - 1
: OMAP243X_HS_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
[1] = { /* general IRQ */
.start = INT_243X_HS_USB_MC,
.flags = IORESOURCE_IRQ,
},
[2] = { /* DMA IRQ */
.start = INT_243X_HS_USB_DMA,
.flags = IORESOURCE_IRQ,
},
开发者ID:smartassfox,项目名称:archos_kernel_27,代码行数:31,代码来源:usb-musb.c
示例12: omapdss_dpi_display_enable
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
{
int r;
if (cpu_is_omap44xx() && dssdev->channel != OMAP_DSS_CHANNEL_LCD2) {
/* Only LCD2 channel is connected to DPI on OMAP4 */
return -EINVAL;
}
r = omap_dss_start_device(dssdev);
if (r) {
DSSERR("failed to start device\n");
return r;
}
if (cpu_is_omap34xx() && !cpu_is_omap3630()) {
r = regulator_enable(dpi.vdds_dsi_reg);
if (r)
goto err0;
}
/* turn on clock(s) */
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
if (!cpu_is_omap44xx())
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
/*Should need only FCK2 (38.4MHz)*/
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2);
#endif
dss_mainclk_state_enable();
dpi_basic_init(dssdev);
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
if (!cpu_is_omap44xx())
r = dsi_pll_init(dssdev, 0, 1);
else {
r = dsi_pll_init(dssdev, 1, 1);
}
if (r)
goto err1;
#endif /* CONFIG_OMAP2_DSS_USE_DSI_PLL */
r = dpi_set_mode(dssdev);
if (r)
goto err2;
mdelay(2);
if (dssdev->manager) {
if (cpu_is_omap44xx())
dpi_start_auto_update(dssdev);
dssdev->manager->enable(dssdev->manager);
}
return 0;
err2:
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
dsi_pll_uninit(dssdev->channel == OMAP_DSS_CHANNEL_LCD ? DSI1 : DSI2);
err1:
#endif
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
if (!cpu_is_omap44xx())
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
dss_mainclk_state_disable(true);
if (cpu_is_omap34xx() && !cpu_is_omap3630())
regulator_disable(dpi.vdds_dsi_reg);
err0:
omap_dss_stop_device(dssdev);
return r;
}
开发者ID:CelticWebSolutions,项目名称:Android-Kernel-2.6.35-Nook-Tablet,代码行数:74,代码来源:dpi.c
示例13: omap2_mmc_mux
static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
if ((mmc_controller->slots[0].switch_pin > 0) && \
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
if ((mmc_controller->slots[0].gpio_wp > 0) && \
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap2420() && controller_nr == 0) {
omap_cfg_reg(H18_24XX_MMC_CMD);
omap_cfg_reg(H15_24XX_MMC_CLKI);
omap_cfg_reg(G19_24XX_MMC_CLKO);
omap_cfg_reg(F20_24XX_MMC_DAT0);
omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
omap_cfg_reg(H14_24XX_MMC_DAT1);
omap_cfg_reg(E19_24XX_MMC_DAT2);
omap_cfg_reg(D19_24XX_MMC_DAT3);
omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
}
/*
* Use internal loop-back in MMC/SDIO Module Input Clock
* selection
*/
if (mmc_controller->slots[0].internal_clock) {
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
//.........这里部分代码省略.........
开发者ID:CunningLogic,项目名称:asteroid_smart_kernel,代码行数:101,代码来源:devices.c
示例14: omap_dss_probe
/* PLATFORM DEVICE */
static int omap_dss_probe(struct platform_device *pdev)
{
struct omap_dss_board_info *pdata = pdev->dev.platform_data;
int r = 0;
int i;
core.pdev = pdev;
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);
#ifdef CONFIG_HAS_EARLYSUSPEND
omap_pm_set_min_bus_tput(&pdev->dev, OCP_INITIATOR_AGENT, 166 * 1000 * 4);
#endif
if (cpu_is_omap44xx())
dss_init_writeback(pdev); /*Write back init*/
#ifdef HWMOD
if (!cpu_is_omap44xx()) {
r = dss_get_clocks();
if (r)
goto err_clocks;
}
core.ctx_id = dss_get_ctx_id();
DSSDBG("initial ctx id %u\n", core.ctx_id);
r = dss_init(pdev);
if (r) {
DSSERR("Failed to initialize DSS\n");
goto err_dss;
}
r = rfbi_init();
if (r) {
DSSERR("Failed to initialize rfbi\n");
goto err_rfbi;
}
r = dpi_init(pdev);
if (r) {
DSSERR("Failed to initialize dpi\n");
goto err_dpi;
}
r = dispc_init(pdev);
if (r) {
DSSERR("Failed to initialize dispc\n");
goto err_dispc;
}
r = venc_init(pdev);
if (r) {
DSSERR("Failed to initialize venc\n");
goto err_venc;
}
if (cpu_is_omap34xx()) {
r = sdi_init(skip_init);
if (r) {
DSSERR("Failed to initialize SDI\n");
goto err_sdi;
}
}
if (!cpu_is_omap24xx()) {
r = dsi_init(pdev);
if (r) {
DSSERR("Failed to initialize DSI\n");
goto err_dsi1;
}
if (cpu_is_omap44xx()) {
r = dsi2_init(pdev);
if (r) {
DSSERR("Failed to initialize DSI2\n");
goto err_dsi2;
}
}
}
#ifdef CONFIG_OMAP2_DSS_HDMI
r = hdmi_init(pdev);
if (r) {
DSSERR("Failed to initialize hdmi\n");
goto err_hdmi;
}
#endif
#endif
r = dss_initialize_debugfs();
if (r)
goto err_debugfs;
for (i = 0; i < pdata->num_devices; ++i) {
struct omap_dss_device *dssdev = pdata->devices[i];
r = omap_dss_register_device(dssdev);
if (r) {
DSSERR("device %d %s register failed %d\n", i,
dssdev->name ?: "unnamed", r);
//.........这里部分代码省略.........
开发者ID:mephistophilis,项目名称:samsung_nowplus_kernel,代码行数:101,代码来源:core.c
示例15: omap_hsmmc_reset
/**
* omap_hsmmc_reset() - Full reset of each HS-MMC controller
*
* Ensure that each MMC controller is fully reset. Controllers
* left in an unknown state (by bootloader) may prevent retention
* or OFF-mode. This is especially important in cases where the
* MMC driver is not enabled, _or_ built as a module.
*
* In order for reset to work, interface, functional and debounce
* clocks must be enabled. The debounce clock comes from func_32k_clk
* and is not under SW control, so we only enable i- and f-clocks.
**/
static void __init omap_hsmmc_reset(void)
{
u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
for (i = 0; i < nr_controllers; i++) {
u32 v, base = 0;
struct clk *iclk, *fclk;
struct device *dev = &dummy_pdev.dev;
switch (i) {
case 0:
base = OMAP2_MMC1_BASE;
break;
case 1:
base = OMAP2_MMC2_BASE;
break;
case 2:
base = OMAP3_MMC3_BASE;
break;
case 3:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC4_BASE;
break;
case 4:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC5_BASE;
break;
}
if (cpu_is_omap44xx())
base += OMAP4_MMC_REG_OFFSET;
dummy_pdev.id = i;
dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
iclk = clk_get(dev, "ick");
if (iclk && clk_enable(iclk))
iclk = NULL;
fclk = clk_get(dev, "fck");
if (fclk && clk_enable(fclk))
fclk = NULL;
if (!iclk || !fclk) {
printk(KERN_WARNING
"%s: Unable to enable clocks for MMC%d, "
"cannot reset.\n", __func__, i);
break;
}
omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
v = omap_readl(base + MMCHS_SYSSTATUS);
while (!(omap_readl(base + MMCHS_SYSSTATUS) &
MMCHS_SYSSTATUS_RESETDONE))
cpu_relax();
if (fclk) {
clk_disable(fclk);
clk_put(fclk);
}
if (iclk) {
clk_disable(iclk);
clk_put(iclk);
}
}
}
开发者ID:paalsteek,项目名称:android_kernel_moto_milestone2,代码行数:80,代码来源:devices.c
示例16: omap_hsmmc_mux
static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
开发者ID:4atty,项目名称:linux,代码行数:80,代码来源:hsmmc.c
示例17: omap2_mmc_mux
static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
if (cpu_is_omap2420() && controller_nr == 0) {
omap_cfg_reg(H18_24XX_MMC_CMD);
omap_cfg_reg(H15_24XX_MMC_CLKI);
omap_cfg_reg(G19_24XX_MMC_CLKO);
omap_cfg_reg(F20_24XX_MMC_DAT0);
omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
if (mmc_controller->slots[0].wires == 4) {
omap_cfg_reg(H14_24XX_MMC_DAT1);
omap_cfg_reg(E19_24XX_MMC_DAT2);
omap_cfg_reg(D19_24XX_MMC_DAT3);
omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
}
/*
* Use internal loop-back in MMC/SDIO Module Input Clock
* selection
*/
if (mmc_controller->slots[0].internal_clock) {
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
if (cpu_is_omap34xx()) {
u32 dev_conf = 0, v_shift = 0;
if (controller_nr == 0) {
omap_cfg_reg(N28_34XX_MMC1_CLK);
omap_cfg_reg(M27_34XX_MMC1_CMD);
omap_cfg_reg(N27_34XX_MMC1_DAT0);
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(N26_34XX_MMC1_DAT1);
omap_cfg_reg(N25_34XX_MMC1_DAT2);
omap_cfg_reg(P28_34XX_MMC1_DAT3);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(P27_34XX_MMC1_DAT4);
omap_cfg_reg(P26_34XX_MMC1_DAT5);
omap_cfg_reg(R27_34XX_MMC1_DAT6);
omap_cfg_reg(R25_34XX_MMC1_DAT7);
}
dev_conf = OMAP2_CONTROL_DEVCONF0;
v_shift = OMAP2_MMCSDIO1ADPCLKISEL;
}
if (controller_nr == 1) {
/* MMC2 */
omap_cfg_reg(AE2_34XX_MMC2_CLK);
omap_cfg_reg(AG5_34XX_MMC2_CMD);
omap_cfg_reg(AH5_34XX_MMC2_DAT0);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
* in the board-*.c files
*/
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AH4_34XX_MMC2_DAT1);
omap_cfg_reg(AG4_34XX_MMC2_DAT2);
omap_cfg_reg(AF4_34XX_MMC2_DAT3);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AE4_34XX_MMC2_DAT4);
omap_cfg_reg(AH3_34XX_MMC2_DAT5);
omap_cfg_reg(AF3_34XX_MMC2_DAT6);
omap_cfg_reg(AE3_34XX_MMC2_DAT7);
}
dev_conf = OMAP343X_CONTROL_DEVCONF1;
v_shift = OMAP2_MMCSDIO2ADPCLKISEL;
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
/*
* Use internal loop-back in MMC/SDIO Module Input Clock
* selection
*/
if (mmc_controller->slots[0].internal_clock && dev_conf) {
u32 v = omap_ctrl_readl(dev_conf);
v |= (1 << v_shift);
omap_ctrl_writel(v, dev_conf);
}
}
}
开发者ID:paalsteek,项目名称:android_kernel_moto_milestone2,代码行数:92,代码来源:devices.c
示例18: omap2_dpll_round_rate
/**
* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
* @clk: struct clk * for a DPLL
* @target_rate: desired DPLL clock rate
*
* Given a DPLL and a desired target rate, round the target rate to a
* possible, programmable rate for this DPLL. Attempts to select the
* minimum possible n. Stores the computed (m, n) in the DPLL's
* dpll_data structure so set_rate() will not need to call this
* (expensive) function again. Returns ~0 if the target rate cannot
* be rounded, or the rounded rate upon success.
*/
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
{
int m, n, r, scaled_max_m;
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
clk->name, target_rate);
scaled_rt_rp = DIV_ROUND_CLOSEST(target_rate,
dd->clk_ref->rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
for (n = dd->min_divider; n <= dd->max_divider; n++) {
if (cpu_is_omap34xx()) {
/* Is the (input clk, divider)pair valid for the DPLL?*/
r = _dpll_test_fint(clk, n);
if (r == DPLL_FINT_UNDERFLOW)
break;
else if (r == DPLL_FINT_INVALID)
continue;
}
/* Compute the scaled DPLL multiplier, based on the divider */
m = scaled_rt_rp * n;
/*
* Since we're counting n up, a m overflow means we
* can bail out completely (since as n increases in
* the next iteration, there's no way that m can
* increase beyond the current m)
*/
if (m > scaled_max_m)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
dd->clk_ref->rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
clk->name, m, n, new_rate);
if (target_rate == new_rate) {
dd->last_rounded_m = m;
dd->last_rounded_n = n;
dd->last_rounded_rate = target_rate;
break;
}
}
if (target_rate != new_rate) {
pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
target_rate);
return ~0;
}
return target_rate;
}
开发者ID:0rt,项目名称:mpokang_kernel,代码行数:82,代码来源:clkt_dpll.c
示例19 |
请发表评论