static int snd_ak4113_spdif_pget(struct snd_kcontrol *kcontrol,
				 struct snd_ctl_elem_value *ucontrol)
{
	struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
	unsigned short tmp;

	ucontrol->value.integer.value[0] = 0xf8f2;
	ucontrol->value.integer.value[1] = 0x4e1f;
	tmp = reg_read(chip, AK4113_REG_Pc0) |
		(reg_read(chip, AK4113_REG_Pc1) << 8);
	ucontrol->value.integer.value[2] = tmp;
	tmp = reg_read(chip, AK4113_REG_Pd0) |
		(reg_read(chip, AK4113_REG_Pd1) << 8);
	ucontrol->value.integer.value[3] = tmp;
	return 0;
}

int snd_ak4114_external_rate(struct ak4114 *ak4114)
{
	unsigned char rcs1;

	rcs1 = reg_read(ak4114, AK4114_REG_RCS1);
	return external_rate(rcs1);
}

int
ig4iic_detach(ig4iic_softc_t *sc)
{
	int error;

	mtx_lock(&sc->mtx);

	reg_write(sc, IG4_REG_INTR_MASK, 0);
	reg_read(sc, IG4_REG_CLR_INTR);
	set_controller(sc, 0);

	if (sc->generic_attached) {
		error = bus_generic_detach(sc->dev);
		if (error)
			goto done;
		sc->generic_attached = 0;
	}
	if (sc->smb) {
		device_delete_child(sc->dev, sc->smb);
		sc->smb = NULL;
	}
	if (sc->intr_handle) {
		bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
		sc->intr_handle = NULL;
	}

	error = 0;
done:
	mtx_unlock(&sc->mtx);
	return error;
}

/* ------------------------------------------------------------------------*//**
 * @FUNCTION		sr54xx_export
 * @BRIEF		export module register content to file, in XML format.
 * @RETURNS		0 in case of success
 *			OMAPCONF_ERR_CPU
 *			OMAPCONF_ERR_ARG
 *			OMAPCONF_ERR_REG_ACCESS
 * @param[in,out]	fp: output file stream (opened for write operations)
 * @param[in]		id: SR module ID
 * @DESCRIPTION		export module register content to file, in XML format.
 *//*------------------------------------------------------------------------ */
int sr54xx_export(FILE *fp, sr54xx_mod_id id)
{
	reg **mod;
	unsigned int i;

	CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
	CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
	CHECK_ARG_LESS_THAN(id, SR54XX_MODS_COUNT, OMAPCONF_ERR_ARG);

	if (!sr54xx_is_enabled(id)) {
		printf("%s export: module not running, skipping "
			"registers export.\n", sr54xx_mod_name_get(id));
		return 0;
	}

	mod = sr54xx_mods[id];

	fprintf(fp, "          <submodule id=\"%u\" name=\"%s\">\n",
		id, sr54xx_mod_name_get(id));

	for (i = 0; i < OMAP5430_SMARTREFLEX_CORE_MOD_REGCOUNT; i++)
		fprintf(fp, "            <register id=\"%u\" name=\"%s\" "
			"addr=\"0x%08X\" data=\"0x%08X\" />\n", i,
			(mod[i])->name, (mod[i])->addr, reg_read(mod[i]));

	fprintf(fp, "          </submodule>\n");

	return 0;
}

/* ------------------------------------------------------------------------*//**
 * @FUNCTION		sr54xx_last_vp_voltage_get
 * @BRIEF		return the last voltage set by the voltage processor
 *			for a domain.
 * @RETURNS		>= 0 last voltage set by voltage processor for this
 *			domain (in volt)
 *			OMAPCONF_ERR_ARG
 *			OMAPCONF_ERR_CPU
 * @param[in]		id: valid SR module ID
 * @DESCRIPTION		return the last voltage set by the voltage processor
 *			for a domain
 *			NB: SR/VP/VC HAVE TO BE AT LEAST INITIALIZED (SR COULD
 *			BE DISABLED) OTHERWISE THIS VALUE HAS NO SENSE.
 *//*------------------------------------------------------------------------ */
double sr54xx_last_vp_voltage_get(sr54xx_mod_id id)
{
	unsigned int vp_voltage, uv;
	unsigned char vsel;
	reg *vp_voltage_r;
	voltdm54xx_id vdd_id = VDD54XX_ID_MAX;

	CHECK_CPU(54xx, (double) OMAPCONF_ERR_CPU);

	/* Retrieve corresponding register address */
	switch (id) {
	case SR54XX_SMARTREFLEX_MPU:
		vp_voltage_r = &omap5430_prm_vp_mpu_voltage;
		vdd_id = VDD54XX_MPU;
		break;
	case SR54XX_SMARTREFLEX_MM:
		vp_voltage_r = &omap5430_prm_vp_mm_voltage;
		vdd_id = VDD54XX_MM;
		break;
	case SR54XX_SMARTREFLEX_CORE:
		vp_voltage_r = &omap5430_prm_vp_core_voltage;
		vdd_id = VDD54XX_CORE;
		break;
	default:
		return (double) OMAPCONF_ERR_ARG;
	}

	/* Retrieve register content and extract voltage */
	vp_voltage = reg_read(vp_voltage_r);
	vp_last_voltage_get(vp_voltage, (unsigned short) vdd_id, &vsel, &uv);
	return (double) uv / 1000000.0;
}

/*
 * only support irom booting.
 */
void irom_copyself(void)
{
	u8_t gpn;
	u32_t * mem;
	u32_t page, block, size;

	/* GPN15, GPN14, GPN13 */
	reg_write(S3C6410_GPNCON, reg_read(S3C6410_GPNCON)&0x03ffffff);
	reg_write(S3C6410_GPNPUD, reg_read(S3C6410_GPNPUD)&0x03ffffff);
	gpn = (u8_t)((reg_read(S3C6410_GPNDAT)>>13)&0x7);

	/* sd-mmc(ch0) */
	if(gpn == 0x0)
	{
		/*
		 * high speed mmc0 initialize.
		 */
		reg_write(S3C6410_HM_CONTROL4_0, reg_read(S3C6410_HM_CONTROL4_0)|(0x3<<16));

		/*
		 * the xboot's memory base address.
		 */
		mem = (u32_t *)__text_start;

		/*
		 * the size which will be copyed, the 'size' is
		 * 1 : 256KB, 2 : 512KB, 3 : 768KB, 4 : 1024KB ...
		 */
		size = (__data_shadow_end - __text_start + 0x00040000) >> 18;

		/*
		 * how many blocks the 'size' is , 512 bytes per block.
		 * size * 256 *1024 / 512 = size * 2^9 = size << 9
		 */
		size = size << 9;

		/*
		 * the xboot's store position in sd card.
		 * it can be written using s3c6410-irom-sd.sh script.
		 */
		block = irom_movi_total_blkcnt - (size + 16 + 1 + 1);

		/*
		 * copy xboot to memory from movi nand.
		 */
		irom_movi_to_mem(0, block, size, mem, 0);
	}

static int snd_ak4117_rate_get(snd_kcontrol_t *kcontrol,
			       snd_ctl_elem_value_t *ucontrol)
{
	ak4117_t *chip = snd_kcontrol_chip(kcontrol);

	ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1));
	return 0;
}

static void reg_clear_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask)
{
	u16 value;

	value = reg_read(i2c_hs, reg_offset);
	value &= ~mask;
	reg_write(i2c_hs, reg_offset, value);
}

static int mxci2c_hs_disable(mxc_i2c_hs *i2c_hs)
{
	reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) & (~HICR_HIEN));
	clk_disable(i2c_hs->ipg_clk);
	clk_disable(i2c_hs->serial_clk);

	return 0;
}

static void reg_dump(ak4117_t *ak4117)
{
	int i;

	printk(KERN_DEBUG "AK4117 REG DUMP:\n");
	for (i = 0; i < 0x1b; i++)
		printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) ? ak4117->regmap[i] : 0);
}

static inline void disable_mailbox_irq(void)
{
    u32 cfg;

    // How to lock ERX_CFG_REG access - could be used from user side at same time!
    cfg = reg_read(&mailbox, ERX_CFG_REG);
    reg_write(&mailbox, ERX_CFG_REG, cfg & ~MAILBOX_ENABLE);
}

void setup_peripheral_device(unsigned *ICMR, unsigned *ICLR, unsigned *OIER){

	*ICMR = reg_read(INT_ICMR_ADDR);
	*ICLR = reg_read(INT_ICLR_ADDR);
	*OIER = reg_read(OSTMR_OIER_ADDR);

	reg_write(INT_ICMR_ADDR,INT_ICCR_DIM<<INT_OSTMR_0);
	reg_write(INT_ICLR_ADDR,0x0);


	reg_clear(OSTMR_OIER_ADDR,OSTMR_OIER_E0|OSTMR_OIER_E1|OSTMR_OIER_E2|OSTMR_OIER_E3);
	reg_set(OSTMR_OIER_ADDR,OSTMR_OIER_E0);
	reg_write(OSTMR_OSMR_ADDR(0),reg_read(OSTMR_OSCR_ADDR)+irq_elapse_count);



}

static int reg_set(struct i2c_client *client, const u8 reg,
		   const u8 data, u8 mask)
{
	int ret = reg_read(client, reg);
	if (ret < 0)
		return ret;
	return reg_write(client, reg, (ret & ~mask) | (data & mask));
}

int acclib_wait_kernel(acclib_kernel *kernel) {
	if (!kernel) {
		if (verbose) printf("Invalid kernel\n");
		return -1;
	}
	while ((reg_read(kernel->user_addr, 0) & 0x2) == 0) {
		//usleep(10);
	}

	if (kernel -> is_ret) {
		printf("return value is in %x\n", 0x18+(kernel->argc-1)*0x8);
		return reg_read(kernel->user_addr, 0x18+(kernel->argc-1)*0x8); // return val
	}
	else {
		return 0;
	}
}

/* ------------------------------------------------------------------------*//**
 * @FUNCTION		cm54xx_export
 * @BRIEF		export module register content to file, in XML format.
 * @RETURNS		0 in case of success
 *			OMAPCONF_ERR_CPU
 *			OMAPCONF_ERR_ARG
 *			OMAPCONF_ERR_INTERNAL
 * @param[in,out]	fp: output file stream (opened for write operations)
 * @param[in]		id: CM module ID
 * @DESCRIPTION		export module register content to file, in XML format.
 *//*------------------------------------------------------------------------ */
int cm54xx_export(FILE *fp, cm54xx_mod_id id)
{
	reg **mod;
	unsigned int i;

	CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
	CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
	CHECK_ARG_LESS_THAN(id, CM54XX_MODS_COUNT, OMAPCONF_ERR_ARG);

	if ((cpu_revision_get() != REV_ES1_0) &&
		(id == CM54XX_L4PER_CM_CORE)) {
		fprintf(stderr, "omapconf: %s(): L4_PER does not exist!!!\n",
			__func__);
		return OMAPCONF_ERR_ARG;
	}

	dprintf("%s(): exporting CM %s (%u) module ...\n", __func__,
		cm54xx_mod_name_get(id), id);

	if (cpu_revision_get() == REV_ES1_0)
		mod = cm54xxes1_mods[id];
	else
		mod = cm54xx_mods[id];
	if (mod == NULL) {
		fprintf(stderr, "omapconf: %s(): mod == NULL!!!\n", __func__);
		return OMAPCONF_ERR_INTERNAL;
	}

	if ((id == CM54XX_INSTR_CM_CORE) &&
		!cm54xx_is_profiling_running(CM54XX_INSTR_CM_CORE)) {
		dprintf(
			"%s(%s): CM module is not accessible, don't export registers\n",
			__func__, cm54xx_mod_name_get(id));
		return 0;
	} else if ((id == CM54XX_INSTR_CM_CORE_AON) &&
		!cm54xx_is_profiling_running(CM54XX_INSTR_CM_CORE_AON)) {
		dprintf(
			"%s(%s): CM module is not accessible, don't export registers\n",
			__func__, cm54xx_mod_name_get(id));
		return 0;
	}

	fprintf(fp, "          <submodule id=\"%u\" name=\"%s\">\n",
		id, cm54xx_mod_name_get(id));

	for (i = 0; mod[i] != NULL; i++)
		fprintf(fp,
			"            <register id=\"%u\" name=\"%s\" addr=\"0x%08X\" data=\"0x%08X\" />\n",
			i, reg_name_get(mod[i]), reg_addr_get(mod[i]),
			reg_read(mod[i]));

	fprintf(fp, "          </submodule>\n");
	fflush(fp);

	dprintf("%s(): CM %s (%u) module exported.\n", __func__,
		cm54xx_mod_name_get(id), id);
	return 0;
}

static int gs_st_open(struct inode *inode, struct file *file)
{			
       reg_read(this_gs_data, GS_ST_REG_STATUS ); /* read status */

       /* enable x, y, z; low power mode 50 HZ */	
       reg_write(this_gs_data, GS_ST_REG_CTRL1, GS_ST_CTRL1_PD|
	       GS_ST_CTRL1_Zen|
	       GS_ST_CTRL1_Yen|
	       GS_ST_CTRL1_Xen);
	
       reg_write(this_gs_data, GS_ST_REG_CTRL3, GS_INTMODE_DATA_READY);

       reg_read(this_gs_data, GS_ST_REG_OUT_XL ); /* read X */
       reg_read(this_gs_data, GS_ST_REG_OUT_XH ); /* read X */
       reg_read(this_gs_data, GS_ST_REG_OUT_YL ); /* read Y */
       reg_read(this_gs_data, GS_ST_REG_OUT_YH ); /* read Y */
       reg_read(this_gs_data, GS_ST_REG_OUT_ZL ); /* read Z*/
       reg_read(this_gs_data, GS_ST_REG_OUT_ZH ); /* read Z*/

       if (this_gs_data->use_irq)
	       enable_irq(this_gs_data->client->irq);
       else
	       hrtimer_start(&this_gs_data->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
	
		
       return nonseekable_open(inode, file);
}

static void
reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
{
	int old_val;

	old_val = reg_read(priv, reg);
	if (old_val >= 0)
		reg_write(priv, reg, old_val & ~val);
}

static void
reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
{
	int old_val;

	old_val = reg_read(priv, reg);
	if (old_val >= 0)
		reg_write(priv, reg, old_val | val);
}

static int aotag_hw_init(struct platform_device *pdev)
{
	int ret = 0;
	unsigned long reg = 0;
	struct aotag_sensor_info_t *ps_info = PDEV2SENSOR_INFO(pdev);
	struct sensor_common_params_t *pcparams =
		SENSOR_INFO2COMMON_PARAMS(ps_info);

	/*
	 * init CONFIG_0 registers
	 */
	reg = 0;
	clear_bit(CONFIG0_STOP_POS, &reg);
	clear_bit(CONFIG0_RO_SEL_POS, &reg);
	clear_bit(CONFIG0_STATUS_CLR_POS, &reg);
	FILL_REG_OR(pcparams->tall, CONFIG0_TALL, &reg);
	reg_write(pdev, pmc, reg, PMC_TSENSOR_CONFIG0);

	/*
	 * init CONFIG_1 registers
	 */
	reg = 0;
	FILL_REG_OR(pcparams->count, CONFIG1_TEN_COUNT, &reg);
	FILL_REG_OR(pcparams->tiddq, CONFIG1_TIDDQ_EN, &reg);
	pcparams->tsample--;
	FILL_REG_OR(pcparams->tsample, CONFIG1_TSAMPLE, &reg);
	pcparams->tsample++;
	set_bit(CONFIG1_TEMP_ENABLE_POS, &reg);
	reg_write(pdev, pmc, reg, PMC_TSENSOR_CONFIG1);

	/*
	 * init CONFIG_2 registers
	 */
	reg = 0;
	FILL_REG_OR(pcparams->pdiv, TSENSOR_PDIV, &reg);
	reg_write(pdev, pmc, reg, PMC_TSENSOR_PDIV0);

	/*
	 * Enable AOTAG + THERMTRIP
	 */
	ret = aotag_update_shutdown_temp(pdev);
	if (unlikely(ret)) {
		aotag_pdev_print(alert, pdev,
				"failed to get shutdown temp, using default\n");
	}

	reg = 0;
	set_bit(CFG_TAG_EN_POS, &reg);
	clear_bit(CFG_DISABLE_CLK_POS, &reg);
	set_bit(CFG_THERMTRIP_EN_POS, &reg);
	reg_write(pdev, pmc, reg, PMC_AOTAG_CFG);
	aotag_pdev_print(info, pdev, "AOTAG EN %x\n",
			reg_read(pdev, pmc, PMC_AOTAG_CFG));

	return ret;
}

/*
 * Interrupt Operation, see ig4_var.h for locking semantics.
 */
static void
ig4iic_intr(void *cookie)
{
	ig4iic_softc_t *sc = cookie;
	uint32_t status;

	mtx_lock(&sc->io_lock);
/*	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
	status = reg_read(sc, IG4_REG_I2C_STA);
	while (status & IG4_STATUS_RX_NOTEMPTY) {
		sc->rbuf[sc->rnext & IG4_RBUFMASK] =
		    (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
		++sc->rnext;
		status = reg_read(sc, IG4_REG_I2C_STA);
	}
	reg_read(sc, IG4_REG_CLR_INTR);
	wakeup(sc);
	mtx_unlock(&sc->io_lock);
}