本文整理汇总了C++中register_syscore_ops函数的典型用法代码示例。如果您正苦于以下问题:C++ register_syscore_ops函数的具体用法?C++ register_syscore_ops怎么用?C++ register_syscore_ops使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了register_syscore_ops函数的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: mtrr_init_finialize
static int __init mtrr_init_finialize(void)
{
if (!mtrr_if)
return 0;
if (use_intel()) {
if (!changed_by_mtrr_cleanup)
mtrr_state_warn();
return 0;
}
/*
* The CPU has no MTRR and seems to not support SMP. They have
* specific drivers, we use a tricky method to support
* suspend/resume for them.
*
* TBD: is there any system with such CPU which supports
* suspend/resume? If no, we should remove the code.
*/
register_syscore_ops(&mtrr_syscore_ops);
return 0;
}
开发者ID:1111saeid,项目名称:jb_kernel_3.0.16_htc_golfu,代码行数:23,代码来源:main.c
示例2: s3c64xx_clk_sleep_init
static void s3c64xx_clk_sleep_init(void)
{
s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
ARRAY_SIZE(s3c64xx_clk_regs));
if (!s3c64xx_save_common)
goto err_warn;
if (!is_s3c6400) {
s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
ARRAY_SIZE(s3c6410_clk_regs));
if (!s3c64xx_save_soc)
goto err_soc;
}
register_syscore_ops(&s3c64xx_clk_syscore_ops);
return;
err_soc:
kfree(s3c64xx_save_common);
err_warn:
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
__func__);
}
开发者ID:0-T-0,项目名称:ps4-linux,代码行数:23,代码来源:clk-s3c64xx.c
示例3: alchemy_usb_init
static int __init alchemy_usb_init(void)
{
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
case ALCHEMY_CPU_AU1500:
case ALCHEMY_CPU_AU1100:
au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
break;
case ALCHEMY_CPU_AU1550:
au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
break;
case ALCHEMY_CPU_AU1200:
au1200_usb_init();
break;
case ALCHEMY_CPU_AU1300:
au1300_usb_init();
break;
}
register_syscore_ops(&alchemy_usb_pm_ops);
return 0;
}
开发者ID:romanbb,项目名称:android_kernel_lge_d851,代码行数:23,代码来源:alchemy-common.c
示例4: combiner_of_init
static int __init combiner_of_init(struct device_node *np,
struct device_node *parent)
{
void __iomem *combiner_base;
combiner_base = of_iomap(np, 0);
if (!combiner_base) {
pr_err("%s: failed to map combiner registers\n", __func__);
return -ENXIO;
}
if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
pr_info("%s: number of combiners not specified, "
"setting default as %d.\n",
__func__, max_nr);
}
combiner_init(combiner_base, np);
register_syscore_ops(&combiner_syscore_ops);
return 0;
}
开发者ID:AK101111,项目名称:linux,代码行数:23,代码来源:exynos-combiner.c
示例5: syscnt_assist_init_ops
static int __init syscnt_assist_init_ops(void)
{
register_syscore_ops(&syscnt_assist_syscore_ops);
return 0;
}
开发者ID:CobraJet93,项目名称:kernel-3.10.54,代码行数:5,代码来源:mt_gpt.c
示例6: sched_clock_syscore_init
static int __init sched_clock_syscore_init(void)
{
register_syscore_ops(&sched_clock_ops);
return 0;
}
开发者ID:davidmueller13,项目名称:valexKernel-lt03wifi,代码行数:5,代码来源:sched_clock.c
示例7: exynos_audss_clk_init
/* register exynos_audss clocks */
static void __init exynos_audss_clk_init(struct device_node *np)
{
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: failed to map audss registers\n", __func__);
return;
}
clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
if (!clk_table) {
pr_err("%s: could not allocate clk lookup table\n", __func__);
return;
}
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
0, &lock);
clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
"dout_aud_bus", "dout_srp", 0,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
&lock);
clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
"dout_aud_bus", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
"dout_i2s", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
"sclk_pcm", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
"div_pcm0", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
pr_info("Exynos: Audss: clock setup completed\n");
}
开发者ID:03199618,项目名称:linux,代码行数:68,代码来源:clk-exynos-audss.c
示例8: hisik3v2_wdt_init
static int __init hisik3v2_wdt_init(void)
{
register_syscore_ops(&wdt_syscore_ops);
return platform_driver_register(&hisik3v2_wdt_driver);
}
开发者ID:softbalajibi,项目名称:android_kernel_huawei_mediapad10fhd,代码行数:5,代码来源:hisik3_wdt.c
示例9: tegra_init_timer
//.........这里部分代码省略.........
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 12800000:
timer_writel(0x043F, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
#endif
default:
if (tegra_platform_is_qt()) {
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
}
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
hotplug_cpu_register(np);
#endif
of_node_put(np);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra20_init_timer();
#else
tegra30_init_timer();
#endif
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32,
clocksource_mmio_readl_up);
if (ret) {
pr_err("%s: Failed to register clocksource: %d\n",
__func__, ret);
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("%s: Failed to register timer IRQ: %d\n",
__func__, ret);
BUG();
}
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
#ifndef CONFIG_ARM64
#ifdef CONFIG_ARM_ARCH_TIMER
/* Architectural timers take precedence over broadcast timers.
Only register a broadcast clockevent device if architectural
timers do not exist or cannot be initialized. */
if (tegra_init_arch_timer())
#endif
/* Architectural timers do not exist or cannot be initialzied.
Fall back to using the broadcast timer as the sched clock. */
setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
#endif
register_syscore_ops(&tegra_timer_syscore_ops);
#ifndef CONFIG_ARM64
late_time_init = tegra_init_late_timer;
#endif
//arm_delay_ops.delay = __tegra_delay;
//arm_delay_ops.const_udelay = __tegra_const_udelay;
//arm_delay_ops.udelay = __tegra_udelay;
}
开发者ID:1ee7,项目名称:linux_l4t_tx1,代码行数:101,代码来源:tegra-nvtimers.c
示例10: tf_device_register
/*
* First routine called when the kernel module is loaded
*/
static int __init tf_device_register(void)
{
int error;
struct tf_device *dev = &g_tf_dev;
dprintk(KERN_INFO "tf_device_register()\n");
/*
* Initialize the device
*/
dev->dev_number = MKDEV(device_major_number,
TF_DEVICE_MINOR_NUMBER);
cdev_init(&dev->cdev, &g_tf_device_file_ops);
dev->cdev.owner = THIS_MODULE;
INIT_LIST_HEAD(&dev->connection_list);
spin_lock_init(&dev->connection_list_lock);
#if defined(MODULE) && defined(CONFIG_TF_ZEBRA)
error = (*tf_comm_early_init)();
if (error)
goto module_early_init_failed;
error = tf_device_mshield_init(smc_mem);
if (error)
goto mshield_init_failed;
#ifdef CONFIG_TF_DRIVER_CRYPTO_FIPS
error = tf_crypto_hmac_module_init();
if (error)
goto hmac_init_failed;
error = tf_self_test_register_device();
if (error)
goto self_test_register_device_failed;
#endif
#endif
/* register the sysfs object driver stats */
error = kobject_init_and_add(&dev->kobj, &tf_ktype, NULL, "%s",
TF_DEVICE_BASE_NAME);
if (error) {
printk(KERN_ERR "tf_device_register(): "
"kobject_init_and_add failed (error %d)!\n", error);
kobject_put(&dev->kobj);
goto kobject_init_and_add_failed;
}
register_syscore_ops((struct syscore_ops *)&g_tf_syscore_ops);
/*
* Register the char device.
*/
printk(KERN_INFO "Registering char device %s (%u:%u)\n",
TF_DEVICE_BASE_NAME,
MAJOR(dev->dev_number),
MINOR(dev->dev_number));
error = register_chrdev_region(dev->dev_number, 1,
TF_DEVICE_BASE_NAME);
if (error != 0) {
printk(KERN_ERR "tf_device_register():"
" register_chrdev_region failed (error %d)!\n",
error);
goto register_chrdev_region_failed;
}
error = cdev_add(&dev->cdev, dev->dev_number, 1);
if (error != 0) {
printk(KERN_ERR "tf_device_register(): "
"cdev_add failed (error %d)!\n",
error);
goto cdev_add_failed;
}
/*
* Initialize the communication with the Secure World.
*/
#ifdef CONFIG_TF_TRUSTZONE
dev->sm.soft_int_irq = soft_interrupt;
#endif
error = tf_init(&g_tf_dev.sm);
if (error != S_SUCCESS) {
dprintk(KERN_ERR "tf_device_register(): "
"tf_init failed (error %d)!\n",
error);
goto init_failed;
}
#ifdef CONFIG_TF_DRIVER_CRYPTO_FIPS
error = tf_self_test_post_init(&(g_tf_dev.kobj));
/* N.B. error > 0 indicates a POST failure, which will not
prevent the module from loading. */
if (error < 0) {
dprintk(KERN_ERR "tf_device_register(): "
"tf_self_test_post_vectors failed (error %d)!\n",
error);
goto post_failed;
//.........这里部分代码省略.........
开发者ID:nickh186,项目名称:Samsung-GT-P3113-AOSP-CM-Kernel-and-Ramdisk,代码行数:101,代码来源:tf_device.c
示例11: acpi_processor_syscore_init
void acpi_processor_syscore_init(void)
{
register_syscore_ops(&acpi_processor_syscore_ops);
}
开发者ID:AndroidGX,项目名称:SimpleGX-L-5.0.2_BOD6_G901F,代码行数:4,代码来源:processor_idle.c
示例12: sirfsoc_irq_pm_init
static int __init sirfsoc_irq_pm_init(void)
{
register_syscore_ops(&sirfsoc_irq_syscore_ops);
return 0;
}
开发者ID:08opt,项目名称:linux,代码行数:5,代码来源:irq.c
示例13: exynos4212_register_clocks
void __init exynos4212_register_clocks(void)
{
int ptr;
/* usbphy1 is removed in exynos 4212 */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used instead of mout_mpll in exynos 4212 */
exynos4_clkset_group_list[6] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_mout_mfc0_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
exynos4_clk_aclk_200.sources = &exynos4212_clkset_aclk_200;
exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP1;
exynos4_clk_aclk_200.reg_src.shift = 20;
exynos4_clk_aclk_200.reg_src.size = 1;
exynos4_clk_fimg2d.enable = exynos4_clk_ip_dmc_ctrl;
exynos4_clk_fimg2d.ctrlbit = (1 << 23);
exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d0.reg_src.shift = 20;
exynos4_clk_mout_g2d0.reg_src.size = 1;
exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d1.reg_src.shift = 24;
exynos4_clk_mout_g2d1.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_sclk_fimg2d.reg_src.shift = 28;
exynos4_clk_sclk_fimg2d.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_DMC1;
exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
exynos4_clk_sclk_fimg2d.reg_div.size = 4;
exynos4_epll_ops.get_rate = exynos4212_epll_get_rate;
exynos4_epll_ops.set_rate = exynos4212_epll_set_rate;
exynos4_vpll_ops.get_rate = exynos4212_vpll_get_rate;
exynos4_vpll_ops.set_rate = exynos4212_vpll_set_rate;
for (ptr = 0; ptr < ARRAY_SIZE(exynos4212_sysclks); ptr++)
s3c_register_clksrc(exynos4212_sysclks[ptr], 1);
s3c_register_clksrc(exynos4212_clksrcs, ARRAY_SIZE(exynos4212_clksrcs));
s3c_register_clocks(exynos4212_init_clocks, ARRAY_SIZE(exynos4212_init_clocks));
s3c_register_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_disable_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_register_clksrc(&exynos4212_clk_isp_srcs_div0, 1);
s3c_register_clksrc(exynos4212_clk_isp_srcs, ARRAY_SIZE(exynos4212_clk_isp_srcs));
s3c_register_clocks(exynos4212_clk_isp, ARRAY_SIZE(exynos4212_clk_isp));
s3c_disable_clocks(&exynos4212_clk_isp_srcs[3].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[4].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[5].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[6].clk, 1);
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
开发者ID:1yankeedt,项目名称:D710BST_FL24_Kernel,代码行数:63,代码来源:clock-exynos4212.c
示例14: fiq_glue_syscore_init
static int __init fiq_glue_syscore_init(void)
{
register_syscore_ops(&fiq_glue_syscore_ops);
return 0;
}
开发者ID:0xroot,项目名称:Blackphone-BP1-Kernel,代码行数:5,代码来源:fiq_glue_setup.c
示例15: rk3288_clk_sleep_init
static void rk3288_clk_sleep_init(void __iomem *reg_base)
{
rk3288_cru_base = reg_base;
register_syscore_ops(&rk3288_clk_syscore_ops);
}
开发者ID:Seagate,项目名称:SMR_FS-EXT4,代码行数:5,代码来源:clk-rk3288.c
示例16: timer_init_syscore_ops
static int __init timer_init_syscore_ops(void)
{
register_syscore_ops(&timer_syscore_ops);
return 0;
}
开发者ID:anewkirk,项目名称:AJK,代码行数:6,代码来源:time.c
示例17: armada_370_xp_timer_common_init
static void __init armada_370_xp_timer_common_init(struct device_node *np)
{
u32 clr = 0, set = 0;
int res;
timer_base = of_iomap(np, 0);
WARN_ON(!timer_base);
local_base = of_iomap(np, 1);
if (timer25Mhz) {
set = TIMER0_25MHZ;
enable_mask = TIMER0_EN;
} else {
clr = TIMER0_25MHZ;
enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
}
atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
local_timer_ctrl_clrset(clr, set);
/*
* We use timer 0 as clocksource, and private(local) timer 0
* for clockevents
*/
armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
/*
* Setup free-running clocksource timer (interrupts
* disabled).
*/
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
atomic_io_modify(timer_base + TIMER_CTRL_OFF,
TIMER0_RELOAD_EN | enable_mask,
TIMER0_RELOAD_EN | enable_mask);
/*
* Set scale and timer for sched_clock.
*/
sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
"armada_370_xp_clocksource",
timer_clk, 300, 32, clocksource_mmio_readl_down);
register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
armada_370_xp_evt = alloc_percpu(struct clock_event_device);
/*
* Setup clockevent timer (interrupt-driven).
*/
res = request_percpu_irq(armada_370_xp_clkevt_irq,
armada_370_xp_timer_interrupt,
"armada_370_xp_per_cpu_tick",
armada_370_xp_evt);
/* Immediately configure the timer on the boot CPU */
if (!res)
armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
register_syscore_ops(&armada_370_xp_timer_syscore_ops);
}
开发者ID:0x000000FF,项目名称:edison-linux,代码行数:65,代码来源:time-armada-370-xp.c
示例18: s3c64xx_syscore_init
static __init int s3c64xx_syscore_init(void)
{
register_syscore_ops(&s3c64xx_irq_syscore_ops);
return 0;
}
开发者ID:03199618,项目名称:linux,代码行数:6,代码来源:irq-pm.c
示例19: armada_370_xp_timer_common_init
static int __init armada_370_xp_timer_common_init(struct device_node *np)
{
u32 clr = 0, set = 0;
int res;
timer_base = of_iomap(np, 0);
if (!timer_base) {
pr_err("Failed to iomap");
return -ENXIO;
}
local_base = of_iomap(np, 1);
if (!local_base) {
pr_err("Failed to iomap");
return -ENXIO;
}
if (timer25Mhz) {
set = TIMER0_25MHZ;
enable_mask = TIMER0_EN;
} else {
clr = TIMER0_25MHZ;
enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
}
atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
local_timer_ctrl_clrset(clr, set);
/*
* We use timer 0 as clocksource, and private(local) timer 0
* for clockevents
*/
armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
/*
* Setup free-running clocksource timer (interrupts
* disabled).
*/
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
atomic_io_modify(timer_base + TIMER_CTRL_OFF,
TIMER0_RELOAD_EN | enable_mask,
TIMER0_RELOAD_EN | enable_mask);
armada_370_delay_timer.freq = timer_clk;
register_current_timer_delay(&armada_370_delay_timer);
/*
* Set scale and timer for sched_clock.
*/
sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
"armada_370_xp_clocksource",
timer_clk, 300, 32, clocksource_mmio_readl_down);
if (res) {
pr_err("Failed to initialize clocksource mmio");
return res;
}
armada_370_xp_evt = alloc_percpu(struct clock_event_device);
if (!armada_370_xp_evt)
return -ENOMEM;
/*
* Setup clockevent timer (interrupt-driven).
*/
res = request_percpu_irq(armada_370_xp_clkevt_irq,
armada_370_xp_timer_interrupt,
"armada_370_xp_per_cpu_tick",
armada_370_xp_evt);
/* Immediately configure the timer on the boot CPU */
if (res) {
pr_err("Failed to request percpu irq");
return res;
}
res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
"clockevents/armada:starting",
armada_370_xp_timer_starting_cpu,
armada_370_xp_timer_dying_cpu);
if (res) {
pr_err("Failed to setup hotplug state and timer");
return res;
}
register_syscore_ops(&armada_370_xp_timer_syscore_ops);
return 0;
}
开发者ID:AshishNamdev,项目名称:linux,代码行数:92,代码来源:time-armada-370-xp.c
示例20: exynos4212_register_clocks
void __init exynos4212_register_clocks(void)
{
int ptr;
unsigned int tmp;
/* usbphy1 is removed in exynos 4212 */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used instead of mout_mpll in exynos 4212 */
exynos4_clkset_group_list[6] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_mout_mfc0_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
exynos4_clk_aclk_200.sources = &exynos4212_clkset_aclk_200;
exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP1;
exynos4_clk_aclk_200.reg_src.shift = 20;
exynos4_clk_aclk_200.reg_src.size = 1;
exynos4_clk_fimg2d.enable = exynos4_clk_ip_dmc_ctrl;
exynos4_clk_fimg2d.ctrlbit = (1 << 23);
exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d0.reg_src.shift = 20;
exynos4_clk_mout_g2d0.reg_src.size = 1;
exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d1.reg_src.shift = 24;
exynos4_clk_mout_g2d1.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_sclk_fimg2d.reg_src.shift = 28;
exynos4_clk_sclk_fimg2d.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_DMC1;
exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
exynos4_clk_sclk_fimg2d.reg_div.size = 4;
exynos4_epll_ops.get_rate = exynos4212_epll_get_rate;
exynos4_epll_ops.set_rate = exynos4212_epll_set_rate;
exynos4_vpll_ops.get_rate = exynos4212_vpll_get_rate;
exynos4_vpll_ops.set_rate = exynos4212_vpll_set_rate;
for (ptr = 0; ptr < ARRAY_SIZE(exynos4212_sysclks); ptr++)
s3c_register_clksrc(exynos4212_sysclks[ptr], 1);
s3c_register_clksrc(exynos4212_clksrcs, ARRAY_SIZE(exynos4212_clksrcs));
s3c_register_clocks(exynos4212_init_clocks, ARRAY_SIZE(exynos4212_init_clocks));
s3c_register_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_disable_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_register_clksrc(&exynos4212_clk_isp_srcs_div0, 1);
s3c_register_clksrc(exynos4212_clk_isp_srcs, ARRAY_SIZE(exynos4212_clk_isp_srcs));
s3c_register_clocks(exynos4212_clk_isp, ARRAY_SIZE(exynos4212_clk_isp));
s3c_disable_clocks(&exynos4212_clk_isp_srcs[3].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[4].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[5].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[6].clk, 1);
/* To save power,
* Disable CLKOUT of LEFTBUS, RIGHTBUS, TOP, DMC, CPU and ISP
*/
for (ptr = 0 ; ptr < ARRAY_SIZE(exynos4x12_cmu_config) ; ptr++) {
tmp = __raw_readl(exynos4x12_cmu_config[ptr].reg);
tmp &= ~(0x1 << 16);
tmp |= (exynos4x12_cmu_config[ptr].val << 16);
__raw_writel(tmp, exynos4x12_cmu_config[ptr].reg);
}
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
开发者ID:0x7678,项目名称:SJKernel-gn2,代码行数:74,代码来源:clock-exynos4212.c
注:本文中的register_syscore_ops函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台,相关代码片段筛选自各路编程大神贡献的开源项目,源码版权归原作者所有,传播和使用请参考对应项目的License;未经允许,请勿转载。 |
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