def execute(self, statements):
     for s in statements:
         if isinstance(s, _Assign):
             self.assign(s.l, self.eval(s.r))
         elif isinstance(s, If):
             if self.eval(s.cond) & (2**len(s.cond) - 1):
                 self.execute(s.t)
             else:
                 self.execute(s.f)
         elif isinstance(s, Case):
             nbits, signed = value_bits_sign(s.test)
             test = _truncate(self.eval(s.test), nbits, signed)
             found = False
             for k, v in s.cases.items():
                 if isinstance(k, Constant) and k.value == test:
                     self.execute(v)
                     found = True
                     break
             if not found and "default" in s.cases:
                 self.execute(s.cases["default"])
         elif isinstance(s, collections.abc.Iterable):
             self.execute(s)
         elif isinstance(s, Display):
             args = []
             for arg in s.args:
                 assert isinstance(arg, _Value)
                 try:
                     args.append(self.signal_values[arg])
                 except: # not yet evaluated
                     args.append(arg.reset.value)
             print(s.s %(*args,))
         else:
             raise NotImplementedError

 def visit_Part(self, node):
     value_proxy = node.value
     offset_proxy = node.offset
     if not isinstance(node.value, Signal):
         value_proxy = Signal(value_bits_sign(node.value))
         if self.target_context:
             a = _Assign(node.value, value_proxy)
         else:
             a = _Assign(value_proxy, node.value)
         self.comb.append(self.visit_Assign(a))
     if not isinstance(node.offset, Signal):
         offset_proxy = Signal(value_bits_sign(node.offset))
         if self.target_context:
             a = _Assign(node.offset, offset_proxy)
         else:
             a = _Assign(offset_proxy, node.offset)
         self.comb.append(self.visit_Assign(a))
     node = _Part(value_proxy, offset_proxy, node.width)
     return NodeTransformer.visit_Part(self, node)

 def visit_Slice(self, node):
     if not isinstance(node.value, Signal):
         slice_proxy = Signal(value_bits_sign(node.value))
         if self.target_context:
             a = _Assign(node.value, slice_proxy)
         else:
             a = _Assign(slice_proxy, node.value)
         self.comb.append(self.visit_Assign(a))
         node = _Slice(slice_proxy, node.start, node.stop)
     return NodeTransformer.visit_Slice(self, node)

 def emit_verilog(tristate, ns, add_data_file):
     def pe(e):
         return verilog_printexpr(ns, e)[0]
     w, s = value_bits_sign(tristate.target)
     r = "assign " + pe(tristate.target) + " = " \
         + pe(tristate.oe) + " ? " + pe(tristate.o) \
         + " : " + str(w) + "'bz;\n"
     if tristate.i is not None:
         r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n"
     r += "\n"
     return r

	def like(cls, other, **kwargs):
		"""Create Signal based on another.

		Parameters
		----------
		other : Value
			Object to base this Signal on.

		See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
		"""
		from migen.fhdl.bitcontainer import value_bits_sign
		return cls(bits_sign=value_bits_sign(other), **kwargs)

 def visit_ArrayProxy(self, node):
     # TODO: rewrite without variables
     array_muxed = Signal(value_bits_sign(node), variable=True)
     if self.target_context:
         k = self.visit(node.key)
         cases = {}
         for n, choice in enumerate(node.choices):
             cases[n] = [self.visit_Assign(_Assign(choice, array_muxed))]
         self.extra_stmts.append(Case(k, cases).makedefault())
     else:
         cases = dict((n, _Assign(array_muxed, self.visit(choice)))
             for n, choice in enumerate(node.choices))
         self.comb.append(Case(self.visit(node.key), cases).makedefault())
     return array_muxed

	def __init__(self, i, o, odomain, n):
		self.i = i
		self.o = o
		self.odomain = odomain

		w, signed = value_bits_sign(self.i)
		self.regs = [Signal((w, signed)) for i in range(n)]

		###

		src = self.i
		for reg in self.regs:
			sd = getattr(self.sync, self.odomain)
			sd += reg.eq(src)
			src = reg
		self.comb += self.o.eq(src)
		self.specials += [NoRetiming(reg) for reg in self.regs]

 def visit_unknown(self, node):
     if isinstance(node, NextState):
         try:
             actual_state = self.aliases[node.state]
         except KeyError:
             actual_state = node.state
         return self.next_state_signal.eq(self.encoding[actual_state])
     elif isinstance(node, NextValue):
         try:
             next_value_ce, next_value = self.registers[node.register]
         except KeyError:
             related = node.register if isinstance(node.register, Signal) else None
             next_value = Signal(bits_sign=value_bits_sign(node.register), related=related)
             next_value_ce = Signal(related=related)
             self.registers[node.register] = next_value_ce, next_value
         return next_value.eq(node.value), next_value_ce.eq(1)
     else:
         return node

    def like(cls, other, **kwargs):
        """Create Signal based on another.

        Parameters
        ----------
        other : _Value
            Object to base this Signal on.

        See `migen.fhdl.bitcontainer.value_bits_sign` for details.
        """
        from migen.fhdl.bitcontainer import value_bits_sign
        kw = dict(bits_sign=value_bits_sign(other))
        if isinstance(other, cls):
            kw.update(variable=other.variable,
                      reset=other.reset.value, reset_less=other.reset_less,
                      related=other.related, attr=set(other.attr))
        kw.update(kwargs)
        return cls(**kw)

    def __init__(self, i, o, odomain, n, reset=0):
        self.i = i
        self.o = o
        self.odomain = odomain

        w, signed = value_bits_sign(self.i)
        self.regs = [Signal((w, signed), reset=reset, reset_less=True)
                for i in range(n)]

        ###

        sd = getattr(self.sync, self.odomain)
        src = self.i
        for reg in self.regs:
            sd += reg.eq(src)
            src = reg
        self.comb += self.o.eq(src)
        for reg in self.regs:
            reg.attr.add("no_retiming")

 def __init__(self, io, o, oe, i):
     nbits, sign = value_bits_sign(io)
     if nbits == 1:
         # If `io` is an expression like `port[x]`, it is not legal to index further
         # into it if it is only 1 bit wide.
         self.specials += \
             Instance("SB_IO",
                 p_PIN_TYPE=C(0b101001, 6),
                 io_PACKAGE_PIN=io,
                 i_OUTPUT_ENABLE=oe,
                 i_D_OUT_0=o,
                 o_D_IN_0=i,
             )
     else:
         for bit in range(nbits):
             self.specials += \
                 Instance("SB_IO",
                     p_PIN_TYPE=C(0b101001, 6),
                     io_PACKAGE_PIN=io[bit],
                     i_OUTPUT_ENABLE=oe,
                     i_D_OUT_0=o[bit],
                     o_D_IN_0=i[bit],
                 )

 def execute(self, statements):
     for s in statements:
         if isinstance(s, _Assign):
             self.assign(s.l, self.eval(s.r))
         elif isinstance(s, If):
             if self.eval(s.cond) & (2**len(s.cond) - 1):
                 self.execute(s.t)
             else:
                 self.execute(s.f)
         elif isinstance(s, Case):
             nbits, signed = value_bits_sign(s.test)
             test = _truncate(self.eval(s.test), nbits, signed)
             found = False
             for k, v in s.cases.items():
                 if isinstance(k, Constant) and k.value == test:
                     self.execute(v)
                     found = True
                     break
             if not found and "default" in s.cases:
                 self.execute(s.cases["default"])
         elif isinstance(s, collections.Iterable):
             self.execute(s)
         else:
             raise NotImplementedError

 def __len__(self):
     from migen.fhdl.bitcontainer import value_bits_sign
     return value_bits_sign(self)[0]