def main():
	dut = Counter()
	# We do not specify a top-level nor runner object, and use the defaults.
	sim = Simulator(dut.get_fragment())
	# Since we do not use sim.interrupt, limit the simulation
	# to some number of cycles.
	sim.run(20)

def main():
	# Compute filter coefficients with SciPy.
	coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
	fir = FIR(coef)
	
	# Simulate for different frequencies and concatenate
	# the results.
	in_signals = []
	out_signals = []
	for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
		tb = TB(fir, frequency)
		fragment = autofragment.from_local()
		sim = Simulator(fragment, Runner())
		sim.run(100)
		in_signals += tb.inputs
		out_signals += tb.outputs
	
	# Plot data from the input and output waveforms.
	plt.plot(in_signals)
	plt.plot(out_signals)
	plt.show()
	
	# Print the Verilog source for the filter.
	print(verilog.convert(fir.get_fragment(),
		ios={fir.i, fir.o}))

class SDRAMHostReadTest(sim.sdram_test_util.SDRAMUTFramework, unittest.TestCase):
#    def setUp(self):

    def _run(self, dummy_data, dummy_idle, max_burst_length, host_burst_length):
        self.tb = TestBench("mt48lc16m16a2", dummy_data, dummy_idle, max_burst_length, host_burst_length)
        # Verify that all necessary files are present
        files = gather_files(self.tb)
        for i in files:
            if not os.path.exists(i):
                raise FileNotFoundError("Please download and save the vendor "
                                        "SDRAM model in %s (not redistributable)"
                                        % i)

        runner = icarus.Runner(extra_files=files)
        vcd = "test_%s.vcd" % self.__class__.__name__
        self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner) 
        with self.sim:
            self.sim.run(10000)
    
    def test_sdram_host_read(self):
        self._run(300, 1000, 256, 16)

    def test_sdram_host_read_2(self):
        self._run(300, 10, 256, 256)

    def test_sdram_host_read_3(self):
        self._run(300, 1000, 16, 17)

    def test_sdram_host_read_4(self):
        self._run(300, 10, 32, 64)

def main():
	dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
	logger = CommandLogger(dut.cmd)
	granter = Granter(dut.req, dut.ack)
	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
	sim = Simulator(fragment)
	sim.run(400)

def main():
	# Create graph
	g = DataFlowGraph()
	gen1 = ComposableSource(g, NumberGen())
	gen2 = ComposableSource(g, NumberGen())
	
	ps = gen1 + gen2
	result = ps*gen1 + ps*gen2
	
	g.add_connection(result.actor_node, ActorNode(Dumper()))

	gen1.actor_node.actor.name = "gen1"
	gen2.actor_node.actor.name = "gen2"
	result.actor_node.name = "result"
	
	# Elaborate
	print("is_abstract before elaboration: " + str(g.is_abstract()))
	draw(g)
	g.elaborate()
	print("is_abstract after elaboration : " + str(g.is_abstract()))
	draw(g)

	# Simulate
	c = CompositeActor(g)
	fragment = c.get_fragment()
	sim = Simulator(fragment, Runner())
	sim.run(100)

def main():
	nbits = 32
	
	# See:
	# http://www.csse.monash.edu.au/~damian/Idioms/Topics/12.1.DataFlow/html/text.html
	g = DataFlowGraph()
	
	adder = ActorNode(Add(BV(nbits)))
	bufadd = ActorNode(plumbing.Buffer) # TODO FIXME: deadlocks without this buffer
	init1 = ActorNode(Init(nbits))
	buf1 = ActorNode(plumbing.Buffer)
	init2 = ActorNode(Init(nbits))
	buf2 = ActorNode(plumbing.Buffer)
	
	g.add_connection(adder, bufadd)
	g.add_connection(bufadd, init1)
	g.add_connection(init1, buf1)
	g.add_connection(buf1, adder, sink_subr="a")
	g.add_connection(buf1, init2)
	g.add_connection(init2, buf2)
	g.add_connection(buf2, adder, sink_subr="b")
	
	g.add_connection(bufadd, ActorNode(Dumper(nbits)))
	
	c = CompositeActor(g)
	fragment = c.get_fragment()
	sim = Simulator(fragment, Runner())
	sim.run(100)

def main():
	base_layout = [("value", 32)]
	packed_layout = structuring.pack_layout(base_layout, pack_factor)
	rawbits_layout = [("value", 32*pack_factor)]
	
	source = SimActor(source_gen(), ("source", Source, base_layout))
	sink = SimActor(sink_gen(), ("sink", Sink, base_layout))
	
	# A tortuous way of passing integer tokens.
	packer = structuring.Pack(base_layout, pack_factor)
	to_raw = structuring.Cast(packed_layout, rawbits_layout)
	from_raw = structuring.Cast(rawbits_layout, packed_layout)
	unpacker = structuring.Unpack(pack_factor, base_layout)
	
	g = DataFlowGraph()
	g.add_connection(source, packer)
	g.add_connection(packer, to_raw)
	g.add_connection(to_raw, from_raw)
	g.add_connection(from_raw, unpacker)
	g.add_connection(unpacker, sink)
	comp = CompositeActor(g)
	reporter = perftools.DFGReporter(g)
	
	fragment = comp.get_fragment() + reporter.get_fragment()
	sim = Simulator(fragment, Runner())
	sim.run(1000)
	
	g_layout = nx.spectral_layout(g)
	nx.draw(g, g_layout)
	nx.draw_networkx_edge_labels(g, g_layout, reporter.get_edge_labels())
	plt.show()

def main():
	hub = asmibus.Hub(16, 128)
	port = hub.get_port()
	hub.finalize()
	
	dut = Framebuffer(1, port, True)
	
	fragment = hub.get_fragment() + dut.get_fragment()
	sim = Simulator(fragment)
	
	sim.run(1)
	def csr_w(addr, d):
		sim.wr(dut.bank.description[addr].field.storage, d)
		
	hres = 4
	vres = 4
	
	csr_w(1, hres) # hres
	csr_w(2, hres+3) # hsync_start
	csr_w(3, hres+5) # hsync_stop
	csr_w(4, hres+10) # hscan
	csr_w(5, vres) # vres
	csr_w(6, vres+3) # vsync_start
	csr_w(7, vres+5) # vsync_stop
	csr_w(8, vres+10) # vscan
	csr_w(10, hres*vres*4) # length
	csr_w(0, 1) # enable
	
	sim.run(1000)

def test_writer():
    print("*** Testing writer")
    trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
    writer = dma_wishbone.Writer()
    g = DataFlowGraph()
    g.add_connection(trgen, writer)
    comp = CompositeActor(g)

    peripheral = MyPeripheral()
    tap = wishbone.Tap(peripheral.bus)
    interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)

    def end_simulation(s):
        s.interrupt = trgen.done and not s.rd(comp.busy)

    fragment = (
        comp.get_fragment()
        + peripheral.get_fragment()
        + tap.get_fragment()
        + interconnect.get_fragment()
        + Fragment(sim=[end_simulation])
    )

    sim = Simulator(fragment, Runner())
    sim.run()

def run_sim(ng):
	g = DataFlowGraph()
	d = Dumper(layout)
	g.add_connection(ng, d)
	
	c = CompositeActor(g)
	sim = Simulator(c)
	sim.run(30)
	del sim

def run_sim(ng):
	g = DataFlowGraph()
	d = Dumper(layout)
	g.add_connection(ng, d)
	
	c = CompositeActor(g)
	fragment = c.get_fragment()
	sim = Simulator(fragment, Runner())
	sim.run(30)
	del sim

def main():
	source = SimSource()
	loop = misc.IntSequence(32)
	sink = SimSink()
	g = DataFlowGraph()
	g.add_connection(source, loop)
	g.add_connection(loop, sink)
	comp = CompositeActor(g)
	sim = Simulator(comp)
	sim.run(500)

def main():
	g = DataFlowGraph()
	g.add_connection(DataGen(), PE43602Driver(PE43602()))
	c = CompositeActor(g)
	
	def end_simulation(s):
		s.interrupt = s.cycle_counter > 5 and not s.rd(c.busy)
	f = c.get_fragment() + Fragment(sim=[end_simulation])
	sim = Simulator(f, TopLevel(vcd_name="pe43602.vcd"))
	sim.run()

def main():
	source = ActorNode(SimActor(source_gen(), ("source", Source, [("value", BV(32))])))
	loop = ActorNode(control.For(32))
	sink = ActorNode(SimActor(sink_gen(), ("sink", Sink, [("value", BV(32))])))
	g = DataFlowGraph()
	g.add_connection(source, loop)
	g.add_connection(loop, sink)
	comp = CompositeActor(g)
	fragment = comp.get_fragment()
	sim = Simulator(fragment, Runner())
	sim.run(500)

def main():
	source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
	sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
	g = DataFlowGraph()
	g.add_connection(source, sink)
	comp = CompositeActor(g)
	def end_simulation(s):
		s.interrupt = source.token_exchanger.done
	fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
	sim = Simulator(fragment, Runner())
	sim.run()

def main():
	source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
	loop = misc.IntSequence(32)
	sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
	g = DataFlowGraph()
	g.add_connection(source, loop)
	g.add_connection(loop, sink)
	comp = CompositeActor(g)
	fragment = comp.get_fragment()
	sim = Simulator(fragment)
	sim.run(500)

def _main():
	from migen.sim.generic import Simulator, TopLevel
	from migen.fhdl import verilog

	pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
	s = SpiFlash(pads)
	print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
		s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))

	tb = SpiFlashTB()
	sim = Simulator(tb, TopLevel("spiflash.vcd"))
	sim.run()

def asmi_sim(efragment, hub, end_simulation):
	def _end_simulation(s):
		s.interrupt = end_simulation(s)
	peripheral = asmibus.Target(MyModelASMI(), hub)
	tap = asmibus.Tap(hub)
	def _end_simulation(s):
		s.interrupt = end_simulation(s)
	fragment = efragment \
		+ peripheral.get_fragment() \
		+ tap.get_fragment() \
		+ Fragment(sim=[_end_simulation])
	sim = Simulator(fragment)
	sim.run()

def wishbone_sim(efragment, master, end_simulation):
	peripheral = wishbone.Target(MyModelWB())
	tap = wishbone.Tap(peripheral.bus)
	interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus)
	def _end_simulation(s):
		s.interrupt = end_simulation(s)
	fragment = efragment \
		+ peripheral.get_fragment() \
		+ tap.get_fragment() \
		+ interconnect.get_fragment() \
		+ Fragment(sim=[_end_simulation])
	sim = Simulator(fragment)
	sim.run()

def run_sim(ng):
	g = DataFlowGraph()
	d = Dumper(layout)
	g.add_connection(ng, d)
	
	slave = wishbone.Target(SlaveModel())
	intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)
	
	c = CompositeActor(g)
	fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
	
	sim = Simulator(fragment)
	sim.run(50)
	del sim