def example_t(file):
    print("testing file: " + file)
    pyrtl.reset_working_block()
    try:
        output = subprocess.check_output(['python', file])
    except subprocess.CalledProcessError as e:
        raise e

    def test_function_RomBlock(self):

        def rom_data_function(add):
            return int((add + 5)/2)

        pyrtl.reset_working_block()
        self.bitwidth = 4
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='rom', romdata=rom_data_function)
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]
        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)

        input_signals = {}
        for i in range(0, 5):
            input_signals[i] = {self.read_addr1: i, self.read_addr2: 2*i}
            self.sim.step(input_signals[i])

        exp_out = self.generate_expected_output((("o1", lambda x: rom_data_function(x)),
                                                 ("o2", lambda x: rom_data_function(2*x))), 6)
        self.compareIO(self.sim_trace, exp_out)

 def test_undriven_net(self):
     w = pyrtl.WireVector(name='testwire', bitwidth=3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     r = pyrtl.Register(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     o = pyrtl.Output(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)

 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.addrwidth = 5
     self.output1 = pyrtl.Output(self.bitwidth, "output1")
     self.in1 = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.in2 = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.memory = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='self.memory', romdata=self.data, max_read_ports=None)

 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.addrwidth = 5
     self.output1 = pyrtl.Output(self.bitwidth, "output1")
     self.mem_read_address1 = pyrtl.Input(self.addrwidth, name='mem_read_address1')
     self.mem_read_address2 = pyrtl.Input(self.addrwidth, name='mem_read_address2')
     self.mem_write_address = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.mem_write_data = pyrtl.Input(self.bitwidth, name='mem_write_data')

    def test_complete_adders(self):
        for bitwidth in range(9, 10):
            r = pyrtl.Register(bitwidth=bitwidth, name='r')
            const_one = pyrtl.Const(1)
            addby = const_one.zero_extended(bitwidth)
            sum, cout = generate_full_adder(r, addby)
            r.next <<= sum

            self.assertTrue(isinstance(r, pyrtl.Register))
            self.assertTrue(isinstance(cout, pyrtl.WireVector))
            pyrtl.reset_working_block()

    def test_net_odd_wires(self):
        wire = pyrtl.WireVector(2, 'wire')
        net = self.new_net(args=(wire, wire))
        other_block = pyrtl.Block()
        wire._block = other_block
        self.invalid_net("net references different block", net)

        pyrtl.reset_working_block()
        wire = pyrtl.WireVector(2, 'wire')
        net = self.new_net(args=(wire,))
        pyrtl.working_block().remove_wirevector(wire)
        self.invalid_net("net with unknown source", net)

    def test_minus_sim_overflow(self):
        pyrtl.reset_working_block()
        i = pyrtl.Input(8, 'i')
        o = pyrtl.Output(name='o')
        o <<= i - 1

        tracer = pyrtl.SimulationTrace()
        sim = self.sim(tracer=tracer)
        sim.step({i: 1})
        self.assertEqual(sim.inspect(o), 0)
        sim.step({i: 0})
        self.assertEqual(sim.inspect(o), 0x1ff)

    def setUp(self):
        pyrtl.reset_working_block()
        bitwidth = 3
        self.a = pyrtl.Input(bitwidth=bitwidth)
        self.b = pyrtl.Input(bitwidth=bitwidth)
        self.sel = pyrtl.Input(bitwidth=1)
        self.muxout = pyrtl.Output(bitwidth=bitwidth, name='muxout')
        self.muxout <<= generate_full_mux(self.a, self.b, self.sel)

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)

    def test_partition_sim(self):
        pyrtl.reset_working_block()
        wires, vals = utils.make_wires_and_values(exact_bitwidth=32, num_wires=1)
        out_wires = [pyrtl.Output(8, "o" + str(i)) for i in range(4)]
        partitioned_w = libutils.partition_wire(wires[0], 8)
        for p_wire, o_wire in zip(partitioned_w, out_wires):
            o_wire <<= p_wire

        out_vals = utils.sim_and_ret_outws(wires, vals)
        partitioned_vals = [[(val >> i) & 0xFF for i in (0, 8, 16, 24)] for val in vals[0]]
        true_vals = tuple(zip(*partitioned_vals))
        for index, wire in enumerate(out_wires):
            self.assertEqual(tuple(out_vals[wire]), true_vals[index])

    def test_order_dependent_ops(self):
        # subtract, lt, gt simarlarly are order dependent.
        # therefore we need to check that we aren't mangling them
        for op, opcode in ((operator.sub, '-'), (operator.gt, '>'), (operator.lt, '<')):
            pyrtl.reset_working_block()
            ins = [pyrtl.Input(5) for i in range(2)]
            outs = [pyrtl.Output(10) for i in range(2)]
            outs[0] <<= op(ins[1], ins[0])
            outs[1] <<= op(ins[0], ins[1])

            pyrtl.common_subexp_elimination()
            self.num_net_of_type(opcode, 2)
            self.num_net_of_type('w', 2)
            pyrtl.working_block().sanity_check()

 def setUp(self):
     pyrtl.reset_working_block()
     bitwidth = 3
     self.r = pyrtl.Register(bitwidth=bitwidth, name='r')
     self.result = _basic_add(self.r, pyrtl.Const(1).zero_extended(bitwidth))
     self.r.next <<= self.result

 def setUp(self):
     pyrtl.reset_working_block()
     self.inp_val = pyrtl.Input(8, 'inp_val')
     self.inp_shift = pyrtl.Input(2, 'inp_shift')
     self.out_zeros = pyrtl.Output(18, 'out_zeros')
     self.out_ones = pyrtl.Output(18, 'out_ones')

 def setUp(self):
     pyrtl.reset_working_block()
     self.vnames = inputoutput._VerilogSanitizer("_sani_test")

 def setUp(self):
     pyrtl.reset_working_block()
     self.aes = aes.AES()
     self.in_vector = pyrtl.Input(bitwidth=128, name='in_vector')
     self.out_vector = pyrtl.Output(bitwidth=128, name='out_vector')

mem2_init = {addr: 9 for addr in range(8)}

# The simulation only recognizes initial values of memories when they are in a
# dictionary composing of memory : mem_values pairs.
memvals = {mem1: mem1_init, mem2: mem2_init}

# now run the simulation like before. Note the adding of the memory
# value map.
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace, memory_value_map=memvals)
for cycle in range(len(simvals['we'])):
    sim.step({k: int(v[cycle]) for k, v in simvals.items()})
sim_trace.render_trace()

# cleanup in preparation for the rom example
pyrtl.reset_working_block()

# --- Part 2: ROMs -----------------------------------------------------------

# ROMs are another type of memory. Unlike normal memories, ROMs are read only
# and therefore only have read ports. They are used to store predefined data

# There are two different ways to define the data stored in the ROMs
# either through passing a function or though a list or tuple


def rom_data_func(address):
    return 31 - 2 * address

rom_data_array = [rom_data_func(a) for a in range(16)]

 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.r = pyrtl.Register(bitwidth=self.bitwidth)
     self.output = pyrtl.Output(bitwidth=self.bitwidth, name='r')
     self.output <<= self.r

 def test_wire_from_another_block(self):
     w = pyrtl.Input(1)
     pyrtl.reset_working_block()
     self.bad_rtl_assert(w, self.RTLSampleException())

 def setUpClass(cls):
     pyrtl.reset_working_block()

 def tearDown(self):
     pyrtl.reset_working_block()