def rlca(cpu, opcode, logger):
        cflag = Bits.getNthBit(cpu.A, 7)
        cpu.A = Bits.setNthBit(cpu.A << 1, 0, cflag)
        cpu.CFlag = Bits.set() if cflag != 0 else Bits.reset()

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("RLCA")

 def test_jr_z_does_not_change_the_z_flag(self):
     cpu = CPU(ROM('\x28\x00\x28\x00'))
     cpu.ZFlag = Bits.reset()
     cpu.readOp()
     self.assertFalse(cpu.ZFlag)
     cpu.ZFlag = Bits.set()
     cpu.readOp()
     self.assertTrue(cpu.ZFlag)

 def cpl(cpu, opcode, logger):
     old = cpu.A
     new = ~old
     cpu.A = new
     cpu.HFlag = Bits.set()
     cpu.NFlag = Bits.set()
     cpu.m_cycles, cpu.t_states = 1, 4
     logger.info("CPL")

 def _checkInterrupts(self):
     if self.iff1:
         self.halted = Bits.reset()
         self.iff1 = Bits.reset()
         self.iff2 = Bits.reset()
         self.ram[--self.SP] = Bits.limitTo8Bits(self.pc)
         self.ram[--self.SP] = self.pc >> 8
         self.R += 1
         if self.im == 0 or self.im == 1:
             self.PC = 0x0038

 def dec_at_hl(cpu, opcode, logger):
     old_val = cpu.ram[cpu.HL]
     new_val = old_val - 1
     cpu.ram[cpu.HL] = new_val
     cpu.ZFlag = Bits.isZero(new_val)
     cpu.SFlag = Bits.isNegative(new_val)
     cpu.NFlag = Bits.set()
     cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
     cpu.m_cycles, cpu.t_states = 3, 11
     logger.info("DEC (HL)")

	def _and(cpu, opcode, logger):
		logger.info("AND A")
		regInd = opcode & 7
		cpu.A = cpu.A & cpu.regs[regInd]
		cpu.flags[HF] = True
		cpu.flags[CF] = False
		cpu.flags[NF] = False
		cpu.flags[ZF] = Bits.isZero(cpu.A)
		cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
		cpu.flags[PVF] = Bits.paritySet(cpu.A)

    def add_iy_rr(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3
        val = cpu.Reg16(regInd, iy=True)

        old = cpu.IY
        cpu.IY = cpu.IY + val
        cpu.NFlag = Bits.reset()
        cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
        cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
        cpu.m_cycles, cpu.t_states = 4, 15
        logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))

	def inc8(cpu, opcode, logger):
		logger.info("INC r")
		index = ( opcode >> 3 ) & 7
		oldValue =  cpu.regs[index]
		cpu.regs[index] = (cpu.regs[index] + 1 ) & 0xFF

		cpu.NFlag = False
		cpu.ZFlag = Bits.isZero(cpu.regs[index])
		cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
		cpu.PVFlag = True if oldValue == 0x7f else False
		cpu.SFlag = Bits.twos_comp(cpu.regs[index]) < 0

 def dec_at_ix_d(cpu, opcode, logger):
     d = cpu.ram[cpu.PC]
     old_val = cpu.ram[cpu.IX+d]
     new_val = old_val - 1
     cpu.ram[cpu.IX+d] = new_val
     cpu.ZFlag = Bits.isZero(new_val)
     cpu.SFlag = Bits.isNegative(new_val)
     cpu.NFlag = Bits.set()
     cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
     cpu.m_cycles, cpu.t_states = 6, 23
     logger.info("DEC (IX+{:02X})".format(d))

    def adc_r(cpu, opcode, logger):
        reg_idx = (opcode & 7)
        old_val = cpu.A
        cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)

        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.NFlag = Bits.reset()

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))

	def cp(cpu, opcode, logger):
		regInd = opcode & 7
		logger.info(regInd)
		value = cpu.A - cpu.regs[regInd]
		"""Flags"""
		cpu.flags[ZF] = Bits.isZero(value)
		cpu.flags[CF] = Bits.carryFlag(value)
		cpu.flags[NF] = True
		cpu.flags[HF] = Bits.halfCarrySub(cpu.A, value)
		cpu.flags[SF] = Bits.signFlag(value)
		cpu.flags[PVF] = Bits.overflow(cpu.A, value)
		logger.info("CP r")

	def xorA(cpu, opcode, logger):
		"""XOR A"""
		regInd = opcode & 7
		cpu.A = cpu.A ^ cpu.regs[regInd]
		"""Flags"""
		cpu.flags[ZF] = Bits.isZero(cpu.A)
		cpu.flags[CF] = False
		cpu.flags[NF] = False
		cpu.flags[HF] = False
		cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
		cpu.flags[PVF] = Bits.paritySet(cpu.A)
		logger.info("XOR A")

    def sub_n(cpu, opcode, logger):
        n = cpu.ram[cpu.PC]
        value = cpu.A - n

        cpu.NFlag = Bits.set()
        cpu.ZFlag = Bits.isZero(value)
        cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
        cpu.PVFlag = Bits.overflow(cpu.A, value)
        cpu.CFlag = Bits.carryFlag(value)
        cpu.A = value

        logger.info("SUB {:02X}".format(n))

    def add16(cpu, opcode, logger):
        regInd = (opcode & 0x30) >> 4
        value = cpu.Reg16(regInd)

        oldHL = cpu.HL
        cpu.HL = cpu.HL + value

        cpu.NFlag = Bits.reset()
        cpu.CFlag = Bits.carryFlag16(oldHL, cpu.HL)
        cpu.HFlag = Bits.carryFlag16(oldHL, cpu.HL, bits=11)
        cpu.m_cycles, cpu.t_states = 3, 11
        logger.info("ADD HL, {}".format(IndexToReg.translate16Bit(regInd)))

    def inc8(cpu, opcode, logger):
        index = (opcode >> 3) & 7
        oldValue = cpu.regs[index]
        cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)

        cpu.NFlag = Bits.reset()
        cpu.ZFlag = Bits.isZero(cpu.regs[index])
        cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
        cpu.PVFlag = True if oldValue == 0x7f else False
        cpu.SFlag = Bits.isNegative(cpu.regs[index])

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("INC {}".format(IndexToReg.translate8Bit(index)))

    def dec8b(cpu, opcode, logger):
        reg_index = (opcode >> 3) & 7
        old_val = cpu.regs[reg_index]
        cpu.regs[reg_index] = cpu.regs[reg_index] - 1

        cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
        cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
        cpu.NFlag = Bits.set()
        cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
        cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))

    def dec_mem_at_iy(cpu, opcode, logger):
        displacement = cpu.ram[cpu.PC]
        addr = cpu.IY + displacement
        value = cpu.ram[addr]
        new_value = value - 1
        cpu.ram[addr] = new_value

        cpu.NFlag = Bits.set()
        cpu.SFlag = Bits.isNegative(new_value)
        cpu.ZFlag = Bits.isZero(new_value)
        cpu.PVFlag = True if value == 0x80 else False
        cpu.HFlag = Bits.halfCarrySub(value, new_value)
        logger.info("DEC (IY+{:2X})".format(displacement))

 def rrd(cpu, opcode, logger):
     low_a = cpu.A & 0x0F
     mem_hl = cpu.ram[cpu.HL]
     low_hl = mem_hl & 0x0F
     high_hl = (mem_hl & 0xF0) >> 4
     cpu.A = (cpu.A & 0xF0) | low_hl
     mem_hl = (low_a << 4) | high_hl
     cpu.ram[cpu.HL] = mem_hl
     cpu.ZFlag = Bits.isZero(cpu.A)
     cpu.SFlag = Bits.isNegative(cpu.A)
     cpu.HFlag = Bits.reset()
     cpu.NFlag = Bits.reset()
     cpu.PVFlag = Bits.isEvenParity(cpu.A)
     cpu.m_cycles, cpu.t_states = 5, 18
     logger.info("RRD")

 def test_add_a_e_with_C_flag_set_correctly_caluclates_value(self):
     cpu = CPU(ROM('\x8b'))
     cpu.A = 0x22
     cpu.E = 0x66
     cpu.CFlag = Bits.set()
     cpu.readOp()
     self.assertEqual(0x89, cpu.A)

    def jr_e(cpu, opcode, logger):
        pc = cpu.PC
        jumpOffset = Bits.twos_comp(cpu.ram[pc])

        cpu.PC = pc + jumpOffset + 1
        cpu.m_cycles, cpu.t_states = 3, 12
        logger.info("JR {0:x}".format(jumpOffset))