本文整理汇总了Python中veriloggen.reset函数的典型用法代码示例。如果您正苦于以下问题：Python reset函数的具体用法？Python reset怎么用？Python reset使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了reset函数的19个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的Python代码示例。
示例1: test
def test(request):
veriloggen.reset()
simtype = request.config.getoption('--sim')
rslt = thread_uart_nexys4.run(filename=None, simtype=simtype)
verify_rslt = rslt.splitlines()[-1]
assert(verify_rslt == '# verify: PASSED')
开发者ID:PyHDI，项目名称:veriloggen，代码行数:9，代码来源:test_thread_uart_nexys4.py
示例2: test
def test():
veriloggen.reset()
try:
test_module = multiple_definition_instance_variable.mkLed()
except ValueError as e:
assert(e.args[0] == "Object 'inst_sub' is already defined.")
return
assert(False)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:9，代码来源:test_multiple_definition_instance_variable.py
示例3: test
def test(request):
veriloggen.reset()
simtype = request.config.getoption('--sim')
rslt = thread_stream_fixed.run(filename=None, simtype=simtype,
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
verify_rslt = rslt.splitlines()[-1]
assert(verify_rslt == '# verify: PASSED')
开发者ID:PyHDI，项目名称:veriloggen，代码行数:10，代码来源:test_thread_stream_fixed.py
示例4: test
def test():
veriloggen.reset()
test_module = thread_multibank_ram_rtl_connect.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_thread_multibank_ram_rtl_connect.py
示例5: test
def test():
veriloggen.reset()
test_module = seq_delayed_eager_val_lazy_cond.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_seq_delayed_eager_val_lazy_cond.py
示例6: test
def test():
veriloggen.reset()
test_module = from_verilog_module_oldstylecode.mkTop()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_from_verilog_module_oldstylecode.py
示例7: test
def test():
veriloggen.reset()
test_module = thread_call_from_different_point.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_thread_call_from_different_point.py
示例8: test
def test():
veriloggen.reset()
test_module = thread_intrinsic_method_prefix.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_thread_intrinsic_method_prefix.py
示例9: test
def test():
veriloggen.reset()
test_module = regchain.mkRegChain(length=120)
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_regchain.py
示例10: test
def test():
veriloggen.reset()
test_module = types_axi_read_lite.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_types_axi_read_lite.py
示例11: test
def test():
veriloggen.reset()
test_module = primitive_mux.mkLed()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_primitive_mux.py
示例12: test
def test():
veriloggen.reset()
test_module = pipeline_acc_add_valid.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_pipeline_acc_add_valid.py
示例13: test
def test():
veriloggen.reset()
test_module = dataflow_two_outputs_mul.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_dataflow_two_outputs_mul.py
示例14: test
def test():
veriloggen.reset()
modules = from_verilog_pycoram_object.mkUserlogic()
code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ])
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:13，代码来源:test_from_verilog_pycoram_object.py
示例15: test
def test():
veriloggen.reset()
test_module = embeddedcode.mkLed()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
#parser = VerilogParser()
#expected_ast = parser.parse(expected_verilog)
#codegen = ASTCodeGenerator()
#expected_code = codegen.visit(expected_ast)
expected_code = expected_verilog
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:14，代码来源:test_embeddedcode.py
示例16: test
def test():
veriloggen.reset()
test_module = simulation_simulator_iverilog.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
sim = simulation.Simulator(test_module, sim='iverilog')
rslt = sim.run()
assert(expected_rslt == rslt)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:18，代码来源:test_simulation_simulator_iverilog.py
示例17: test
def test():
veriloggen.reset()
test_module = simulation_simulator_vcs.mkTest()
code = test_module.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
try:
from shutil import which
except:
# from distutils.spawn import find_executable as which
print('no which command')
return
if which('vcs'):
sim = simulation.Simulator(test_module, sim='vcs')
rslt = sim.run()
new_rslt = []
for line in rslt.split('\n'):
if line.count('LED:') > 0:
new_rslt.append(line)
new_rslt.append('')
rslt = '\n'.join(new_rslt)
assert(expected_rslt == rslt)
else:
print("'vcs' not found")
开发者ID:PyHDI，项目名称:veriloggen，代码行数:36，代码来源:test_simulation_simulator_vcs.py
示例18: test
def test():
veriloggen.reset()
test_modules = from_verilog_branchpredunit.mkMips()
code = ''.join([ m.to_verilog() for m in test_modules.values() if not m.used ])
from pyverilog.vparser.parser import parse
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
import sys
import tempfile
# encoding: 'utf-8' ?
encode = sys.getdefaultencoding()
tmp = tempfile.NamedTemporaryFile()
tmp.write(expected_verilog.encode(encode))
tmp.read()
filename = tmp.name
print(filename)
expected_ast, _ = parse([ filename ])
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:24，代码来源:test_from_verilog_branchpredunit.py
示例19: test
def test():
veriloggen.reset()
test_module = simulation_simulator_verilator.mkTest()
sim = simulation.Simulator(test_module, sim='verilator')
rslt = sim.run(outputfile='verilator.out', sim_time=1000 * 20)
assert(expected_rslt == rslt)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:6，代码来源:test_simulation_simulator_verilator.py
注：本文中的veriloggen.reset函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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