def __init__(self, name, library, verilog_parser, include_dirs=None, defines=None):
     SourceFile.__init__(self, name, library, 'verilog')
     self.package_dependencies = []
     self.module_dependencies = []
     self.include_dirs = include_dirs if include_dirs is not None else []
     self.defines = defines.copy() if defines is not None else {}
     code = ostools.read_file(self.name, encoding=HDL_FILE_ENCODING)
     self._content_hash = hash_string(code)
     for key, value in self.defines.items():
         self._content_hash = hash_string(self._content_hash + hash_string(key))
         self._content_hash = hash_string(self._content_hash + hash_string(value))
     self.parse(code, verilog_parser, include_dirs)

    def _create_test_mapping_file(self, test_suites):
        """
        Create a file mapping test name to test output folder.
        This is to allow the user to find the test output folder when it is hashed
        """
        mapping_file_name = join(self._output_path, "test_name_to_path_mapping.txt")

        # Load old mapping to remember non-deleted test folders as well
        # even when re-running only a single test case
        if exists(mapping_file_name):
            with open(mapping_file_name, "r") as fptr:
                mapping = set(fptr.read().splitlines())
        else:
            mapping = set()

        for test_suite in test_suites:
            name_hash = hash_string(test_suite.name)
            HASH_TO_TEST_NAME[name_hash] = test_suite.name
            mapping.add("%s %s" % (name_hash, test_suite.name))

        # Sort by everything except hash
        mapping = sorted(mapping, key=lambda value: value[value.index(" "):])

        with open(mapping_file_name, "w") as fptr:
            for value in mapping:
                fptr.write(value + "\n")

 def __init__(self, name, library, vhdl_parser):
     SourceFile.__init__(self, name, library, 'vhdl')
     self.dependencies = []
     self.depending_components = []
     code = ostools.read_file(self.name)
     self._content_hash = hash_string(code)
     self.parse(code, vhdl_parser)

 def _hash_file_name_of(self, source_file):
     """
     Returns the name of the hash file associated with the source_file
     """
     library = self.get_library(source_file.library.name)
     prefix = hash_string(dirname(source_file.name))
     return join(library.directory, prefix, basename(source_file.name) + ".vunit_hash")

    def _compile_options_hash(self):
        """
        Compute hash of compile options

        Needs to be updated if there are nested dictionaries
        """
        return hash_string(repr(sorted(self._compile_options.items())))

    def parse(self, code, parser, include_dirs):
        """
        Parse Verilog code and adding dependencies and design units
        """
        try:
            design_file = parser.parse(code, self.name, include_dirs, self.defines)
            for included_file_name in design_file.included_files:
                self._content_hash = hash_string(self._content_hash +
                                                 ostools.read_file(included_file_name, encoding=HDL_FILE_ENCODING))
            for module in design_file.modules:
                self.design_units.append(ModuleDesignUnit(module.name, self, module.parameters))

            for package in design_file.packages:
                self.design_units.append(VerilogDesignUnit(package.name, self, "package"))

            for package_name in design_file.imports:
                self.package_dependencies.append(package_name)

            for package_name in design_file.package_references:
                self.package_dependencies.append(package_name)

            for instance_name in design_file.instances:
                self.module_dependencies.append(instance_name)

        except KeyboardInterrupt:
            raise
        except:  # pylint: disable=bare-except
            traceback.print_exc()
            LOGGER.error("Failed to parse %s", self.name)

def create_output_path(output_file, test_suite_name):
    """
    Create the full output path of a test case.
    Ensure no bad characters and no long path names.
    """
    hash_name = hash_string(test_suite_name)
    return join(output_file, hash_name)

 def _content_hash(self, file_name):
     """
     Hash the contents of the file
     """
     if file_name is None or not exists(file_name):
         return None
     if file_name not in self._content_cache:
         self._content_cache[file_name] = "sha1:" + hash_string(read_file(file_name))
     return self._content_cache[file_name]

    def parse(self, code, file_name, content_hash=None):
        """
        Parse the VHDL code and return a VHDLDesignFile parse result
        parse result is re-used if content hash found in database
        """
        file_name = abspath(file_name)

        if content_hash is None:
            content_hash = "sha1:" + hash_string(code)
        key = ("CachedVHDLParser.parse(%s)" % file_name).encode()

        if key in self._database:
            design_file, old_content_hash = self._database[key]
            if content_hash == old_content_hash:
                LOGGER.debug("Re-using cached VHDL parse results for %s with content_hash=%s",
                             file_name, content_hash)
                return design_file

        design_file = VHDLDesignFile.parse(code)
        self._database[key] = design_file, content_hash
        return design_file

 def content_hash(self):
     """
     Compute hash of contents and compile options
     """
     return hash_string(self._content_hash + self._compile_options_hash() + hash_string(self._vhdl_standard))