本文整理汇总了Python中vunit.project.Project类的典型用法代码示例。如果您正苦于以下问题：Python Project类的具体用法？Python Project怎么用？Python Project使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了Project类的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的Python代码示例。
示例1: test_compile_project_vhdl_coverage
def test_compile_project_vhdl_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
开发者ID:suoto，项目名称:vunit，代码行数:25，代码来源:test_modelsim_interface.py
示例2: test_compile_project_verilog_hdlvar
def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
开发者ID:mark-newsam，项目名称:vunit，代码行数:33，代码来源:test_incisive_interface.py
示例3: test_compile_project_verilog_define
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access
开发者ID:suoto，项目名称:vunit，代码行数:25，代码来源:test_modelsim_interface.py
示例4: test_compile_project_vhdl_2002
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])
开发者ID:barri，项目名称:vunit，代码行数:28，代码来源:test_incisive_interface.py
示例5: test_compile_project_vhdl_2002
def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
开发者ID:mark-newsam，项目名称:vunit，代码行数:30，代码来源:test_incisive_interface.py
示例6: test_compile_project_verilog_hdlvar
def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])
开发者ID:barri，项目名称:vunit，代码行数:31，代码来源:test_incisive_interface.py
示例7: test_add_source_file_detects_illegal_vhdl_standard
def test_add_source_file_detects_illegal_vhdl_standard(self):
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
self.assertRaises(ValueError, project.add_source_file, "file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard='2007')
开发者ID:go2sh，项目名称:vunit，代码行数:7，代码来源:test_project.py
示例8: test_recompile_when_updating_defines
def test_recompile_when_updating_defines(self):
contents = """
module mod;
endmodule
"""
self.project = Project()
self.project.add_library("lib", "lib_path")
mod1 = self.add_source_file("lib", "module1.v", contents)
mod2 = self.add_source_file("lib", "module2.v", contents)
self.assert_should_recompile([mod1, mod2])
self.update(mod1)
self.update(mod2)
self.assert_should_recompile([])
self.project = Project()
self.project.add_library("lib", "lib_path")
mod1 = self.add_source_file("lib", "module1.v", contents,
defines={"foo": "bar"})
mod2 = self.add_source_file("lib", "module2.v", contents)
self.assert_should_recompile([mod1])
self.update(mod1)
self.update(mod2)
self.assert_should_recompile([])
self.project = Project()
self.project.add_library("lib", "lib_path")
mod1 = self.add_source_file("lib", "module1.v", contents,
defines={"foo": "other_bar"})
mod2 = self.add_source_file("lib", "module2.v", contents)
self.assert_should_recompile([mod1])
self.update(mod1)
self.update(mod2)
self.assert_should_recompile([])
开发者ID:darwinbeing，项目名称:vunit，代码行数:33，代码来源:test_project.py
示例9: test_compile_project_vhdl_extra_flags
def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
开发者ID:KevinKes，项目名称:vunit，代码行数:25，代码来源:test_modelsim_interface.py
示例10: test_compile_project_verilog_coverage
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-work',
'lib',
'file.v',
'-L', 'lib'])
开发者ID:KevinKes，项目名称:vunit，代码行数:25，代码来源:test_modelsim_interface.py
示例11: test_order_of_adding_libraries_is_kept
def test_order_of_adding_libraries_is_kept(self):
for order in itertools.combinations(range(4), 4):
project = Project()
for idx in order:
project.add_library("lib%i" % idx, "lib%i_path" % idx)
library_names = [lib.name for lib in project.get_libraries()]
self.assertEqual(library_names, ["lib%i" % idx for idx in order])
开发者ID:go2sh，项目名称:vunit，代码行数:8，代码来源:test_project.py
示例12: test_compile_project_verilog_error
def test_compile_project_verilog_error(self):
simif = GHDLInterface(prefix="prefix")
write_file("file.v", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.v", "lib", file_type="verilog")
self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")
开发者ID:suoto，项目名称:vunit，代码行数:8，代码来源:test_ghdl_interface.py
示例13: test_add_source_file_has_vhdl_standard
def test_add_source_file_has_vhdl_standard(self):
write_file("file.vhd", "")
for std in ('93', '2002', '2008'):
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard=std)
self.assertEqual(source_file.get_vhdl_standard(), std)
开发者ID:go2sh，项目名称:vunit，代码行数:9，代码来源:test_project.py
示例14: test_compile_project_93
def test_compile_project_93(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=93', '-Plib_path', 'file.vhd'])
开发者ID:KevinKes，项目名称:vunit，代码行数:11，代码来源:test_ghdl_interface.py
示例15: test_compile_project_2002
def test_compile_project_2002(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2002")
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=02', '-Plib_path', 'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
开发者ID:suoto，项目名称:vunit，代码行数:12，代码来源:test_ghdl_interface.py
示例16: test_compile_project_extra_flags
def test_compile_project_extra_flags(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib', '--std=08',
'-Plib_path', 'custom', 'flags', 'file.vhd'])
开发者ID:KevinKes，项目名称:vunit，代码行数:12，代码来源:test_ghdl_interface.py
示例17: test_compile_source_files_run_command_error
def test_compile_source_files_run_command_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.return_value = False
self.assertRaises(CompileError, simif.compile_source_files, project)
run_command.assert_called_once_with(["command"])
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
开发者ID:KevinKes，项目名称:vunit，代码行数:13，代码来源:test_simulator_interface.py
示例18: test_should_recompile_files_after_changing_vhdl_standard
def test_should_recompile_files_after_changing_vhdl_standard(self):
write_file("file_name.vhd", "")
self.project = Project()
self.project.add_library("lib", "lib_path")
source_file = self.project.add_source_file("file_name.vhd", library_name="lib", vhdl_standard='2008')
self.assert_should_recompile([source_file])
self.update(source_file)
self.assert_should_recompile([])
self.project = Project()
self.project.add_library("lib", "lib_path")
source_file = self.project.add_source_file("file_name.vhd", library_name="lib", vhdl_standard='2002')
self.assert_should_recompile([source_file])
开发者ID:go2sh，项目名称:vunit，代码行数:14，代码来源:test_project.py
示例19: test_add_source_file_has_no_parse_vhdl
def test_add_source_file_has_no_parse_vhdl(self):
for no_parse in (True, False):
project = Project()
file_name = "file.vhd"
write_file(file_name, """
entity ent is
end entity;
""")
project.add_library("lib", "work_path")
source_file = project.add_source_file(file_name,
"lib",
file_type=file_type_of(file_name),
no_parse=no_parse)
self.assertEqual(len(source_file.design_units), int(not no_parse))
开发者ID:go2sh，项目名称:vunit，代码行数:15，代码来源:test_project.py
示例20: test_compile_source_files_create_command_error
def test_compile_source_files_create_command_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.return_value = True
def raise_compile_error(*args, **kwargs):
raise CompileError
simif.compile_source_file_command.side_effect = raise_compile_error
self.assertRaises(CompileError, simif.compile_source_files, project)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
开发者ID:KevinKes，项目名称:vunit，代码行数:16，代码来源:test_simulator_interface.py
注：本文中的vunit.project.Project类示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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