本文整理汇总了Python中rhea.utils.test.run_testbench函数的典型用法代码示例。如果您正苦于以下问题:Python run_testbench函数的具体用法?Python run_testbench怎么用?Python run_testbench使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了run_testbench函数的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的Python代码示例。
示例1: test_spi_slave
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus = SPIBus()
fifobus = FIFOBus()
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield clock.posedge
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
assert spibus.get_read_data() == 0x55
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_spi_slave, args=args)
开发者ID:hstarmans,项目名称:rhea,代码行数:26,代码来源:test_spi_slave.py
示例2: testbench_memmap
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
@myhdl.block
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
开发者ID:FelixVi,项目名称:rhea,代码行数:25,代码来源:test_memmap.py
示例3: test_prbs_word_lengths
def test_prbs_word_lengths(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
@myhdl.block
def bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
for wl in [2**ii for ii in range(11)]:
prbs = Signal(intbv(0)[wl:])
run_testbench(bench_prbs, timescale='1ps', args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:31,代码来源:test_prbs.py
示例4: test_known_prbs5
def test_known_prbs5(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
expected_pattern = (0xC7, 0xAE, 0x90, 0xE6,)
@myhdl.block
def bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs5, timescale='1ps', args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:33,代码来源:test_prbs.py
示例5: test_spi_models
def test_spi_models(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
ibus = Barebone(glbl)
spibus = SPIBus()
def bench():
tbdut = spi_controller_model(clock, ibus, spibus)
tbspi = SPISlave().process(spibus)
tbclk = clock.gen()
@instance
def tbstim():
yield clock.posedge
yield ibus.writetrans(0x00, 0xBE)
yield delay(100)
yield ibus.readtrans(0x00)
raise StopSimulation
return tbdut, tbspi, tbclk, tbstim
run_testbench(bench, args=args)
开发者ID:Godtec,项目名称:rhea,代码行数:26,代码来源:test_spi_models.py
示例6: test
def test():
clock = Clock(0)
reset = Reset(0, active=0, async=False)
sdi, sdo = [Signal(bool(0)) for _ in range(2)]
pin = [Signal(intbv(0)[16:]) for _ in range(7)]
pout = [Signal(intbv(0)[16:]) for _ in range(3)]
def _bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
# @todo: actually test something
for ii in range(1000):
yield clock.posedge
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_serio)
开发者ID:gbin,项目名称:rhea,代码行数:25,代码来源:test_serio.py
示例7: test_known_prbs7
def test_known_prbs7(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# computed by hand
expected_pattern = (0x3F, 0x10, 0x0C, 0xC5, 0x13, 0xCD, 0x95, 0x2F)
@myhdl.block
def bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs7, timescale='1ps', args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:31,代码来源:test_prbs.py
示例8: test_spi_cso_config
def test_spi_cso_config(args=None):
args = tb_default_args()
# get an instance of the control-status object
cso = spi_controller.cso()
assert isinstance(cso, spi.cso.ControlStatus)
# set a default configuration
cso.loopback.initial_value = False
cso.clock_polarity.initial_value = True
cso.clock_phase.initial_value = True
cso.clock_divisor.initial_value = 2
cso.slave_select.initial_value = 0x10
cso.isstatic = True
def bench():
tbdut = cso.get_generators()
@instance
def tbstim():
yield delay(10)
assert not cso.loopback
assert cso.clock_polarity
assert cso.clock_phase
assert cso.clock_divisor == 2
assert cso.slave_select == 0x10
yield delay(10)
raise StopSimulation
return tbdut, tbstim
run_testbench(bench, args)
开发者ID:Godtec,项目名称:rhea,代码行数:32,代码来源:test_spi_cso_config.py
示例9: testbench_streamer
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
def _bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(_bench_streamer, args=args)
myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
if args.keep:
myhdl.toVerilog.name += '_keep'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)
开发者ID:Godtec,项目名称:rhea,代码行数:59,代码来源:test_streamers.py
示例10: test_elink_interfaces
def test_elink_interfaces(args=None):
""" test the ELink interface """
args = tb_default_args(args)
clock = Signal(bool(0))
# create the interfaces
elink = ELink() # links the two components (models)
emesh = EMesh(clock) # interface into the Elink external component
@myhdl.block
def bench_elink_interface():
tbnorth = elink_external_model(elink, emesh)
tbsouth = elink_asic_model(elink)
@always(delay(2500))
def tbclk():
clock.next = not clock
@instance
def tbstim():
yield delay(1111)
yield clock.posedge
# send a bunch of write packets
print("send packets")
save_data = []
yield emesh.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
save_data.append(0xDECAFBAD)
for ii in range(10):
addr = randint(0, 1024)
data = randint(0, (2**32)-1)
save_data.append(data)
yield emesh.write(addr, data, ii)
# the other device is a simple loopback, should receive
# the same packets sent.
while emesh.txwr_fifo.count > 0:
print(" waiting ... {}".format(emesh))
yield delay(8000)
print("get packets looped back, ")
while len(save_data) > 0:
yield delay(8000)
pkt = emesh.get_packet('wr')
if pkt is not None:
assert pkt.data == save_data[0], \
"{} ... {:08X} != {:08X}".format(
pkt, int(pkt.data), save_data[0])
save_data.pop(0)
for ii in range(27):
yield clock.posedge
raise StopSimulation
return tbclk, tbnorth, tbsouth, tbstim
run_testbench(bench_elink_interface, timescale='1ps', args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:58,代码来源:test_elink_interfaces.py
示例11: test_adc128s022
def test_adc128s022():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
glbl = Global(clock, reset)
fifobus = FIFOBus(width=16)
spibus = SPIBus()
channel = Signal(intbv(0, min=0, max=8))
step = 3.3/7
analog_channels = [Signal(3.3 - step*ii) for ii in range(0, 8)]
print(analog_channels)
assert len(analog_channels) == 8
def check_empty(clock, fifo):
for ii in range(4000):
if not fifo.empty:
break
yield clock.posedge
@myhdl.block
def bench_adc128s022():
tbdut = adc128s022(glbl, fifobus, spibus, channel)
tbmdl = adc128s022_model(spibus, analog_channels,
vref_pos=3.3, vref_neg=0.)
tbclk = clock.gen()
@instance
def tbstim():
sample = intbv(0)[16:]
yield reset.pulse(33)
yield clock.posedge
# check the conversion value for each channel, should get
# smaller and smaller
for ch in range(0, 8):
channel.next = (ch+1) % 8 # next channel
yield check_empty(clock, fifobus)
# should have a new sample
if not fifobus.empty:
fifobus.read.next = True
sample[:] = fifobus.read_data
yield clock.posedge
fifobus.read.next = False
yield clock.posedge
print("sample {:1X}:{:4d}, fifobus {} \n".format(
int(sample[16:12]), int(sample[12:0]), str(fifobus)))
assert fifobus.empty
else:
print("No sample!")
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tbstim
run_testbench(bench_adc128s022)
开发者ID:FelixVi,项目名称:rhea,代码行数:56,代码来源:test_adc128s022.py
示例12: test_ibh
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
def _bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(_bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(icestick_blinky_host, clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts)
开发者ID:Godtec,项目名称:rhea,代码行数:55,代码来源:test_blinky_host_icestick.py
示例13: test_btn_led
def test_btn_led():
clock = Clock(0, frequency=500e3)
reset = Reset(0, active=0, async=False)
leds = Signal(intbv(0)[8:])
btns = Signal(intbv(0)[4:])
@myhdl.build
def bench_btn_led():
# bus_type = ('A', 'B', 'W', 'X') # avalon, barebone, wishbone, AXI
tbdut = button_led_mm(clock, reset, leds, btns, bus_type='wishbone')
def dumpg(glist):
for gg in glist:
if isinstance(gg, (list,tuple)):
dumpg(gg)
elif gg is not None:
print("{:16}: {}".format(gg.func.__name__,
gg.func.__module__))
dumpg(tbdut)
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(10)
reset.next = not reset.active
yield clock.posedge
# assert leds == 0
for ii in range(3):
# simulate a button press
btns.next = 1 << ii
yield delay(12)
btns.next = 0
for cc in range(8):
yield clock.posedge
# @todo: a more interesting check
# assert leds != 0
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_btn_led)
# currently an error when converting to both at once,
# only convert to one at a time.
inst = button_led_mm(clock, reset, leds, btns)
inst.convert(hdl='Verilog', directory='output')
开发者ID:FelixVi,项目名称:rhea,代码行数:55,代码来源:test.py
示例14: test_spi_slave
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus, fifobus = SPIBus(), FIFOBus()
# monitor the FIFOBus signals
data = Signal(intbv(0)[8:])
rd, wr, full, empty = Signals(bool(0), 4)
@myhdl.block
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield delay(1000)
yield clock.posedge
# @todo: make generic
# @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
yield spibus.writeread(0xCE)
assert spibus.get_read_data() == 0x55
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xAA
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xCE
raise StopSimulation
@always_comb
def tb_fifo_loopback():
if not fifobus.full:
fifobus.write.next = not fifobus.empty
fifobus.read.next = not fifobus.empty
fifobus.write_data.next = fifobus.read_data
# monitors
@always_comb
def tbmon():
data.next = fifobus.read_data
rd.next = fifobus.read
wr.next = fifobus.write
full.next = fifobus.full
empty.next = fifobus.empty
return tbdut, tbclk, tbstim, tb_fifo_loopback, tbmon
run_testbench(bench_spi_slave, args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:54,代码来源:test_spi_slave.py
示例15: test_memmap_command_bridge
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fbtx, fbrx = FIFOBus(), FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fbtx.clock = clock
fbrx.clock = clock
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
开发者ID:gbin,项目名称:rhea,代码行数:54,代码来源:test_memmap_command_bridge.py
示例16: test_elink_io
def test_elink_io(args=None):
args = tb_default_args(args)
def _bench_elink_io():
@instance
def tbstim():
yield delay(10)
return tbstim
run_testbench(_bench_elink_io, timescale='1ps', args=args)
开发者ID:Godtec,项目名称:rhea,代码行数:12,代码来源:test_elink_io.py
示例17: test_spi_cso
def test_spi_cso(args=None):
args = tb_default_args(args)
def bench():
@instance
def tbstim():
# @todo: add test stimulus
yield delay(10)
raise StopSimulation
return tbstim
run_testbench(bench, args)
开发者ID:Godtec,项目名称:rhea,代码行数:12,代码来源:test_spi_cso_config.py
示例18: test_hdmi
def test_hdmi():
""" simple test to demonstrate test framework
"""
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
# this currently tests a Verilog version
# tbdut = prep_cosim(clock, reset, args=args)
tbdut = hdmi()
def _bench_hdmi():
# tbdut = mm_hdmisys(glbl, vselect, hdmi,
# resolution=res,
# line_rate=line_rate)
# clock for the design
@always(delay(5))
def tbclk():
clock.next = not clock
@instance
def tbstim():
yield delay(13)
reset.next = reset.active
yield delay(33)
reset.next = not reset.active
yield clock.posedge
try:
for ii in range(100):
yield delay(100)
except AssertionError as err:
print("@E: assertion error @ %d ns" % (now(),))
print(" %s" % (str(err),))
# additional simulation cycles after the error
yield delay(111)
raise err
except Exception as err:
print("@E: error occurred")
print(" %s" % (str(err),))
raise err
raise StopSimulation
return tbclk, tbstim
# run the above test
run_testbench(_bench_hdmi)
开发者ID:gbin,项目名称:rhea,代码行数:52,代码来源:test_hdmi.py
示例19: test
def test(args=None):
if args is None:
args = Namespace(trace=False)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
sdi, sdo = Signals(bool(0), 2)
pin = Signals(intbv(0)[16:0], 1)
pout = Signals(intbv(0)[16:0], 3)
valid = Signal(bool(0))
@myhdl.block
def bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
for pp in pout:
pp.next = 0
sdi.next = False
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert not sdo
assert pin[0] == 0
for pp in pout:
pp.next = 0xFFFF
sdi.next = True
yield valid.posedge
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo
assert pin[0] == 0xFFFF
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_serio, args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:51,代码来源:test_serio.py
示例20: test_elink_io
def test_elink_io(args=None):
args = tb_default_args(args)
@myhdl.block
def bench_elink_io():
@instance
def tbstim():
yield delay(10)
raise StopSimulation
return tbstim
run_testbench(bench_elink_io, timescale='1ps', args=args)
开发者ID:FelixVi,项目名称:rhea,代码行数:14,代码来源:test_elink_io.py
注:本文中的rhea.utils.test.run_testbench函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台,相关代码片段筛选自各路编程大神贡献的开源项目,源码版权归原作者所有,传播和使用请参考对应项目的License;未经允许,请勿转载。 |
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