Welcome To Ask or Share your Answers For Others

Recent articles tagged hdl

0 votes

1 reply 971 views

hdl - What is the difference between reg and wire in a verilog module

posted Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1 reply 1.1k views

hdl - How does adding 1'b1 to 8 bit reg work in Verilog?

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1 reply 854 views

hdl - What is the difference between reg and wire in a verilog module

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1 reply 1.2k views

hdl - Implementing a Repetition error correcting code in Verilog

posted Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1 reply 4.4k views

hdl - chip Mux4way16 not run ontil the end on ?HardwareSimulator (VHDL)

posted Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

To see more, click for the full list of articles or popular tags.

Recent articles tagged hdl

...