hdl - Implementing a Repetition error correcting code in Verilog

Question

I want to use an FPGA to implement an error correction code but I'm running into some issues. I started with the simplest one, R(3), which simply repeats each bit of the message three times and decodes the codeword by a majority decision:

https://en.wikipedia.org/wiki/Repetition_code

I implemented the encoder and decoder in verilog in a straight-forward way, for a 128-bit message:

Encoder

`timescale 10ns / 10ns
module Encoder(
input [127 : 0] key,
output reg [383 : 0] c
);
integer j;
always @* begin
 for (j = 0; j < 128; j=j+1) begin
  c[j * 3 +: 3] = key[j] ? 3'b111 : 3'b000;
 end
end

endmodule

Decoder

`timescale 10ns / 10ns
module Decoder(
input [383 : 0] c,
output reg [127 : 0] key
);
reg x1, x2, x3;
integer j;
always @* begin
 for (j = 0; j < 128; j=j+1) begin
   x1 =c[j * 3]&c[j * 3+1];
   x2 =c[j * 3]&c[j * 3+2];
   x3 =c[j * 3+1]&c[j * 3+2];
   key[j]=x1|x2|x3;
 end
end

endmodule

They work well under behavioral simulation, but when I synthesize the design each bit is separated into a wire and processed independently. For the decoder, 128 majority gates are synthesized, instead of just one. This is naturally very expensive to implement for what should be rather simple in terms of hardware. I believe this is due to the use of the for loop, but I am not very experienced in verilog and I don't know another way to code it that would result in a synthesizable code in practical terms. Perhaps I should use some kind of counter with sequential logic instead of combinational logic, I would appreciate any help regarding this issue.

Answer 1

等待大神答复