Why am I getting this error Makefile: No rule to make target 'timer.c', needed by 'timer.o'. Stop

Question

My working directory looks like this:

• main.c
• Makefile
• my_memmove.h
• my_memmove.c
• c-timer-lib
  • timer.c
  • timer.h

My makefile looks like this:

CC := gcc
CFLAGS := -std=gnu99 -g -Wall -Wextra -Ic-timer-lib
TARGET := output

output: main.o my_memmove.o timer.o
        $(CC) $(CFLAGS) main.o my_memmove.o timer.o -o $(TARGET)

main.o: main.c
        gcc -c main.c

my_memmove.o: my_memmove.c my_memmove.h
        gcc -c my_memmove.c

timer.o: c-timer-lib/timer.c c-timer-lib/timer.h
        gcc -c c-timer-lib/timer.c -o $@

clean:
        rm *.o $(TARGET)

I don't understand why I keep getting the "Makefile: No rule to make target 'timer.c', needed by 'timer.o'. Stop." error. I believe that it's because the timer.c and timer.h files can't be found.

question from:https://stackoverflow.com/questions/65864361/why-am-i-getting-this-error-makefile-no-rule-to-make-target-timer-c-needed-b

Answer 1

So much confusion here! :)

First, this is definitely wrong:

$(CC) $(CFLAGS) -I main.o ...

The -I main.o tells the compiler that it should use main.o as the name of a directory to search for include files. That clearly won't work. You should remove the -I here.

On to your problem: you have to realize that there are two completely different programs at play here: make which figures out how to run commands, and the commands that are being run, in this case the compiler gcc.

The -I option is an option to the compiler so that the compiler knows where to look for header files that are included by your source code with #include.

That option means nothing to make; it doesn't understand that option. It's just some text to pass to the compiler. Make is looking for the source file timer.c and it can't find it because you haven't told make where it is.

You have to write your rule to look in the correct place, like this:

timer.o: c-timer-lib/timer.c c-timer-lib/timer.h
            gcc -c c-timer-lib/timer.c -o $@

(you should always use -o $@ so that your compile line puts the output file where make expects to find it, which will be put into the $@ variable by make before it evaluates your recipe.)

ETA

Also, are you sure that -DUNITS="ms" is right? We can't tell without seeing how UNITS is used in the source, but I suspect you probably need an extra level of quotes here, like -DUNITS='"ms"'

Really, you are trying to do too much in this makefile. Make already knows how to correctly build object files from source files. If you don't force the issue by writing your own rules, then make's built-in rules will do the job for you. Your makefile can be written like this:

CC := gcc
CFLAGS := -std=gnu99 -g -Wall -Wextra -Ic-timer-lib -DUNITS='"ms"'
TARGET := output

$(TARGET): main.o my_memmove.o c-timer-lib/timer.o
        $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)

my_memmove.o: my_memmove.h
c-timer-lib/timer.o: c-timer-lib/timer.h

clean:
        rm *.o $(TARGET)

make doesn't know which headers your source requires so you have to add the prerequisites by hand, although you can add extra rules to allow it to figure that out for itself.