Enabling Instruction Cache Prefetching in GEM5

Question

I noticed that in the GEM5 full system provided by ARM (fs.py), the HPI CPU instruction cache does not use a prefetcher. The source code specifically states # No prefetcher, this is handled by the core (HPI.py).

I tried adding a prefetcher to the ICache to look into this issue. The config.ini output showed that the prefetcher was indeed included in the system, but examining stats.txt I saw that it did not issue any prefetch requests. I also spent some time reading through the core source code, but could not identify any component that seemed to handle instruction prefetching.

I was wondering why this is. I can think of scenarios where instruction prefetching could benefit the CPU performance, and am not aware of a technical problem implementing it. This is especially confusing to me since it seems the system was built to allow using instruction prefetching: the configuration scripts allow setting a prefetcher for the ICache from the command line, the ICache class is derived from Cache and so can incorporate a prefetcher, and prefetchers in GEM5 have a on_inst property which supposedly controls instruction prefetching.

Can anyone explain the logic behind this, and possibly suggest ways to enable prefetching for the instruction cache?

question from:https://stackoverflow.com/questions/65886414/enabling-instruction-cache-prefetching-in-gem5

Answer 1

Waitting for answers