x86 64 - How is CR8 register used to prioritize interrupts in an x86-64 CPU?

Question

I'm reading the Intel documentation on control registers, but I'm struggling to understand how CR8 register is used. To quote the docs (2-18 Vol. 3A):

Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corresponding to the highest- priority interrupt to be blocked. A value of 0 means all interrupts are enabled. This field is available in 64- bit mode. A value of 15 means all interrupts will be disabled.

I have 3 quick questions, if you don't mind:

1. So bits 3 thru 0 of CR8 make up those 16 levels of priority values. But priority of what? A running "thread", I assume, correct?

2. But what is that priority value in CR8 compared to when an interrupt is received to see if it has to be blocked or not?

3. When an interrupt is blocked, what does it mean? Is it "delayed" until later time, or is it just discarded, i.e. lost?

Answer 1

CR8 indicates the current priority of the CPU. When an interrupt is pending, bits 7:4 of the interrupt vector number is compared to CR8. If the vector is greater, it is serviced, otherwise it is held pending until CR8 is set to a lower value.

Assuming the APIC is in use, it has an IRR (Interrupt Request Register) with one bit per interrupt vector number. When that bit is set, the interrupt is pending. It can stay that way forever.

When an interrupt arrives, it is ORed into the IRR. If the interrupt is already pending (that is, the IRR bit for that vector is already set), the new interrupt is merged with the prior one. (You could say it is dropped, but I don't think of it that way; instead, I say the two are combined into one.) Because of this merging, interrupt service routines must be designed to process all the work that is ready, rather than expecting a distinct interrupt for each unit of work.